JPS62224043A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To increase the freedom of position and number of introduce power source leads without decreasing the number of peripheral circuit parts available to be used, by arranging a semiconductor base under the whole region where power source leads can be introduced to constitute a wiring. CONSTITUTION:Internal circuit parts 7, peripheral circuit parts 3 and terminal pad parts 4 are arranged in a gate array IC. Circuit elements capable of constituting arbitrarily either one of an input buffer circuit and an output buffer circuit on an input/output buffer circuit are previously formed in the respective peripheral circuit parts 3 as a semiconductor base. A terminal pad part 4A for a power source lead is arbitrarily selected out of many terminal pad parts 4, and power leads are introduced to the internal circuit parts 7 through power leads introducing wirings 8, which are arranged on a surface insulating film of the part where circuit elements of the peripheral circuit parts 3 are formed. Thereby, freedom of position to introduce the power leads can be increased without decreasing the number of peripheral circuits available to be used and almost without producing useless dead space.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor integrated circuit technology, and further to technology that is effective when applied to gate array LSIs (large scale integrated circuit devices).

[Conventional technology]

Gate array ICs (semiconductor integrated circuit devices) are, for example, published by Nikkei McGraw-Hill [Nikkei Electronics 19
June 3, 1985 issue, pages 151-177 (commentary: 100
Gate arrays, which are about to reach a billion yen market, realize desired circuit functions by arbitrarily wiring a large number of circuit elements prepared in the form of bases on a semiconductor substrate. Therefore, it is also called a so-called semi-custom IC.

Here, the inventor studied the layout configuration of the gate array IC. Although the following is not a publicly known technique, it is a technique developed and studied by the present inventor, and its outline is as follows.

FIG. 3 shows layout configurations of gate array ICs studied by the present inventors.

The gate array IC shown in the figure is provided with an internal circuit section 7, a peripheral circuit section 3, and a terminal pad section 4, which constitute an arbitrary logic circuit network.

The internal circuit section 7 is arranged in a large portion at the center of the semiconductor substrate 1. A large number of basic cell arrays 5 are arranged in this internal circuit section 7.

Each basic cell array 5 is arranged parallel to each other. Along with this, a wiring region 7 having a predetermined width is provided between each basic cell array 5.

The basic cell array 5 has a large number of basic cells 6 arranged in one direction (in the row direction in the figure). In each basic cell 6, circuit elements for forming a logic gate are formed in advance in the form of a semiconductor base. The type and number of circuit elements formed in each basic cell 6, their arrangement, etc. are standardized in advance.

On the other hand, a large number of peripheral circuits s surround the internal circuit section 7.
3 are arranged, and terminal pad parts 4 for bonding are arranged on the outside of each peripheral circuit part 3, respectively.

In each peripheral circuit section 3, circuit elements are formed in advance in the form of a semiconductor base to form any one of an input buffer circuit, an output balance circuit, or an input/output buffer circuit. Input/output signals of the internal circuit section 7 are led out or introduced from the outside via the buffer circuit constituted by the peripheral circuit section 3 and the terminal pad section 4.

Here, the operating power supply VCC of the gate array IC is supplied to the internal circuit section 7 and the peripheral circuit section from the terminal pad section 4A at a specific position designated as a power supply via the power supply terminal pad section 4A through the power lead-in wiring 8. Drawn to 3. There is an empty space 9 under the power supply terminal pad portion 4A for passing the power supply lead-in wiring N8. This empty space 9 is originally where the peripheral circuit section 3 will be formed, but since the wide power supply lead-in wiring #8 with a large current capacity is passed through, it can be used as a base for forming the peripheral circuit section 3. However, the base was not formed because it was thought that there was no point in forming the wiring for configuring this peripheral circuit.

[Problem that the invention seeks to solve]

However, the inventors have found that the above-mentioned technique has the following problems.

That is, although the position of the power supply wiring line 8 is fixed in advance as described above, it may sometimes be necessary to change the position due to customer requests or mounting reasons. If this change is made, there is no base layer formed under the original planned area for wiring the power supply wiring, so that area cannot be used to form the input/output buffer, so it is a waste of time. This results in empty space.

An object of the present invention is to greatly increase the degree of freedom in the position and number of power supply connections without reducing the number of usable peripheral circuit sections in a gate array IC and without creating nearly any wasted empty space. This technology provides the technology to do this.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief summary of typical inventions disclosed in this application is as shown below.

That is, a semiconductor base is provided entirely under the area where the power supply wiring can be laid extending from the terminal pad portion. The power lead-in wiring line is wired on the optical surface insulating film, and the semiconductor element is also arranged under the surface insulating film of the peripheral circuit section where the power lead-in wiring is wired.

[Effect]

According to the above-mentioned means, even if the power supply wiring position is changed, the original space can be used as a human output buffer because the base has been formed, and the number of input/output buffers can be reduced. can be prevented.

〔Example〕

Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

In each figure, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows the layout configuration of a gate array IC to which the technology according to the present invention is applied.

First, the gate array IC shown in the figure is provided with an internal circuit section 7, a peripheral circuit section 3, and a terminal pad section 4, in which an arbitrary logic circuit network is constructed.

The internal circuit section 7 is arranged in a large portion at the center of the semiconductor substrate 1. A large number of basic cell arrays 5 are arranged in this internal circuit section 7.

Each basic cell array 5 is arranged parallel to each other. In addition, a wiring region 7 having a predetermined width is provided between each basic cell array 5.

The basic cell array 5 has a large number of basic cells 6 arranged in one direction (in the row direction in the figure). In each basic cell 6, circuit elements for forming a logic gate are formed in advance in the form of a semiconductor base. The type and number of circuit elements formed in each basic cell 6, their arrangement, etc. are standardized in advance.

On the other hand, a large number of peripheral circuit sections 3 are arranged surrounding the internal circuit section 7, and terminal pad sections 4 for bonding are arranged on the outside of each peripheral circuit section 3, respectively.

Each of the peripheral circuits s3 has circuit elements formed in advance in the form of a semiconductor base to form any one of an input buffer circuit, an output buffer circuit, or an input/output 7277 circuit. Internal circuit s20
Input/output signals are led out or introduced from the outside via the buffer circuit constituted by the peripheral circuit section 3 and the terminal pad section 4.

Further, a terminal pad section 4A for power supply is arbitrarily selected from among the large number of terminal pad sections 4, and this terminal pad section 4A for power supply is arbitrarily selected.
Power is drawn into the internal circuit section 2 through a power supply lead-in wiring 8 .

Here, the power lead-in wiring 8 from the power supply terminal pad section 4A to the internal circuit section 2 is laid out on the surface insulating film of the portion of the peripheral circuit section 3 where the circuit elements are formed, although the details will be described later. Ru.

FIG. 2 shows a cross-sectional state near the power supply terminal pad section 4A and the peripheral circuit section 3 in an exaggeratedly enlarged manner.

In the figure, a gate array IC is formed on a semiconductor substrate 1 using a p-type silicon semiconductor substrate 10. As shown in FIG. In the area of the peripheral circuit section 3, there is an n* type buried layer (n”BL).
), n-type Z/L' diffusion layer (nWE L L ) 12,
p-type isolation diffusion layer (pISO) 13, p-type well diffusion layer 1
4 and the like are selectively formed to form active element regions such as bipolar transistors and MOS transistors. 15 is a p-type base diffusion layer, 16 is an n-medium emitter diffusion layer, 17 is an n-medium collector connection diffusion layer, 18 is an n-type source/drain diffusion layer, and 19 is a gate electrode. Further, 20 indicates a surface insulating film made of an oxide film. The power supply lead-in Al wiring 8 is passed over this surface insulating film 20. The power lead-in wiring 8 is formed of the first layer of aluminum wiring, and one end thereof is connected to the terminal pad portion 4.
A and the other end is connected to the Vcc line (2). Second-layer aluminum wiring A/2 is used for the terminal pad portion 4A, the VCC line (2), and the GND line (2), respectively.

As explained above, even if the power supply lead-in wiring 8 is passed through an arbitrary position, no empty space is created.

Above, the invention made by the present inventor has been specifically explained based on the examples, but it should be noted that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Not even. For example, the circuit elements of the peripheral circuit section 3 below the power lead-in wiring 8 may be used in addition to the input/output buffer, for example, to configure a circuit for preventing noise from entering the power line via xf.

In the above explanation, we have mainly explained the case where the invention made by the present inventor is applied to the Bi-CMO8 type gate array IC, which is the field of application that is the background of the invention.
For example, it is not limited to micro-
It can also be applied to random logic ICs such as processors.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

In other words, the effect is that it becomes possible to increase the degree of freedom in the position of power supply lead-in without reducing the number of peripheral circuit sections that can be used in a semiconductor integrated circuit device and without creating almost any wasted empty space. is obtained.

[Brief explanation of drawings]

FIG. 1 is a plan view showing the layout configuration of a gate array IC to which the technology according to the present invention is applied, FIG. 2 is an enlarged cross-sectional view showing a moving surface state in a part of FIG. 1 is a plan view showing a layout configuration of a gate array IC developed and studied by the applicant before the invention; FIG. DESCRIPTION OF SYMBOLS 1... Half-bedded board, 3... Peripheral circuit section, 4... Terminal pad section, 4A... Terminal pad section selected for power supply, 5... Basic cell array, 6... Basic cell, 7.
...Internal circuit, 8...Power lead-in wiring, 9...Wiring manager, 20...Surface insulating film (surface oxide film), 21...
Interlayer insulating film, All...first layer aluminum wiring,
A72...2nd layer aluminum wiring, Vcc...
power supply. Agent: Patent Attorney / Katsuo Togawa (, 1st
figure

Claims (1)

[Claims] 1. A semiconductor integrated circuit device in which a large number of peripheral circuit parts are arranged surrounding an internal circuit part arranged in the center of a semiconductor substrate, and a terminal pad part is arranged outside the peripheral circuit part, and the terminal pad part is arranged outside the peripheral circuit part. A semiconductor integrated circuit device, characterized in that circuit elements of the peripheral circuit section are formed below a region where power supply wiring can be wired, which is connected to the pad section and wired on the surface insulating film.