JPS62285443A - Master-slice integrated circuit device - Google Patents

Abstract

PURPOSE:To predetermine input and output characteristics optionally by a method wherein respective peripheral I/O cells have a plurality of input buffers with required input and output characteristics and a plurality of output buffers with required input and output characteristics and both the buffers are interconnected by wirings optionally. CONSTITUTION: Pads 10 for input and output are provided on the circumference of a chip 9 and peripheral I/O cells 12 are provided between a reference cell 11 which is not wired yet and provided at the center and the pads 10. The respective cells 12 have output buffers 13 and input buffers 14. If a necessary number of buffers 13 are connected in parallel and the output terminals are connected to the pads 10 and the input terminals are connected to the reference cell 11, the required output can be obtained from the pad 10 and, on the other hand, if a suitable number of the buffers 14 are connected in parallel and the input terminals are connected to the pads 10 and the output terminals are connected to the reference cell 11, the pads 10 can be used for signal input. With this constitution, the output and input power can be arbitrarily set from small capacity to large capacity by wirings so that the degree of freedom of design can be improved.

Description

[Detailed Description of the Invention] &Detailed Description of the Invention (Industrial Application Field) The present invention provides a method for attaching standard single semiconductor elements to a semiconductor substrate in advance! The present invention relates to a master slice integrated circuit device in which a predetermined semiconductor integrated circuit device can be formed simply by preparing a formed master wafer and later wiring the semiconductor elements according to specifications.

(Conventional example) Conventionally, such a master slice integrated circuit device has a third
There is one shown in the figure.

This figure is a configuration explanatory diagram showing the structure of a semiconductor chip 1 in which standard single semiconductor elements are regularly formed. A wafer that has not been individually separated (scribed) is called a master wafer.

The master wafer is constructed using a well-known manufacturing process of semiconductor integrated circuit technology, and each semiconductor chip 1 has a bonding pad 2 for power supply and a bonding pad 3 for grounding on the outer periphery, as shown in FIG. Input/output bonding pads 4 for exchanging signals with the outside are formed, and a reference cell 5 is formed in the center of the semiconductor chip 1.

Each bonding parameter r2, 3.4 is slightly larger than the diameter of the bonding wire to be connected in the assembly process described later, for example, the vertical and horizontal width is /O0μ77LX
/O0μm. Further, in order to prevent adjacent rebonding wires from coming into contact with each other during the assembly process, they are spaced apart by a certain distance or more.

Each reference cell 5 includes a plurality of semiconductor elements whose size and shape are predetermined, such as transistors, capacitors, etc.
Resistors and other components are formed as a single unit without being wired together.

In the area between the reference cell 5 and the input/output bonding pad 4, each bonding pad 4 is provided as shown by the dotted line.
Surrounding around 1. /O cells 6 are formed, and each peripheral force cell 6 has a plurality of output buffer circuits 7 and an input buffer circuit 8 formed therein. The output 7777 circuit 7 is a circuit that amplifies the power of the output signal from the circuit formed by the reference cell 5 and outputs it by wiring to be described later, and the input buffer circuit 8
is a circuit that receives an input signal inputted from the outside via the attendance pad 4.

At the master wafer stage, the input terminals and output terminals of the output 7777 circuit 7 and the input buffer circuit 8 are not wired and are in an open state.

Output buffer circuits 7 that are not connected to each other in this way
The wiring between the input buffer circuit 8 and the semiconductor elements in the reference cell 5 and the wiring with the bonding pads are formed according to the specifications of the customer, etc., as described later, and an arbitrary integrated circuit device can be formed according to the wiring pattern. It is now possible to do so.

Next, in order to form an integrated circuit device according to specifications using a master wafer that does not have a specific circuit configured in advance, the semiconductor elements in the reference cell 5 are At the same time, the circuit formed by the reference cell 5 and the input/output terminal of the output buffer circuit 7 or the input buffer circuit 8 are connected by the aluminum layer wiring. This later wiring is called personalized wiring. Here, the input/output bonding pad 4 connected to the input terminal of the input buffer circuit 80 serves as a bonding pad for signal input, and the input/output bonding pad 4 connected to the output terminal of the output buffer circuit 7 serves as a signal input bonding pad. It will be used as a bonding pad for output. Although not shown, the input buffer circuit 8 is connected to the input bonding pad 4 via an input protection circuit for protecting internal circuits from high-voltage static electricity from the outside.

After completing this hawk-sonization wiring and separating (scribing) the master wafer into individual semiconductor chips 1, each semiconductor chip 1 is housed in a package in the assembly process, and the bonding pads 2, 3.4 are By connecting to predetermined lead terminals of the package via bonding wires, an integrated circuit device that meets specifications can be completed.

In this way, with a master slice integrated circuit device, the desired integrated circuit device can be formed by preparing a master wafer in advance and then wiring it according to the specifications, so that the entire process from specification determination to completion can be completed. It takes only a short time, and because it is only necessary to design the mask turn for wiring, the turn around time from design to mass production is shortened.
) has the advantage of being short.

(Problems to be Solved by the Invention) However, in such a master slice integrated circuit device, one
Since the paired input buffer circuit and output sofa circuit have a uniform circuit configuration, the power amplification factor is constant. For this reason, even if a high-power output buffer circuit is required to directly drive an externally connected device such as a monitor, there are problems in which it cannot be changed, and in order to solve this problem, multiple output buffer circuits are required. If an attempt is made to obtain a large amount of power by connecting the input/output bonding pads 9 and the output buffer circuit in parallel, there is a problem that the number of input/output bonding pads is substantially reduced.

Conversely, even if a low power output signal is sufficient, the output sofa circuit cannot be changed to a low power output signal.
There was a problem that power consumption could not be reduced.

Furthermore, there was a similar problem with the bag 77 circuit.

(Means for Solving the Problems) The present invention has been made in view of the above problems, and it is possible to set the input/output characteristics of the input cutoff circuit and/or the output balance circuit by personalized wiring. The purpose of the present invention is to provide a master slice integrated circuit device that can be used as a master slice integrated circuit device.

To achieve this objective, the present invention provides a plurality of input buffer circuit groups having predetermined input/output characteristics and/or a plurality of input buffer circuit groups having predetermined input/output characteristics around bonding pads formed on each semiconductor chip at the master wafer stage. Input/output characteristics can be set appropriately by providing peripheral cells forming a plurality of output buffer circuit groups and connecting an appropriate number of input buffer circuits and/or output balance circuits in parallel during normalization wiring. The technical point is that this was done.

(Embodiment) Hereinafter, one embodiment of a master slice integrated circuit device according to the present invention will be described with reference to the drawings. FIG. 1 shows the main structure related to the present invention. Regarding the structure, the difference from the conventional one is that bonding pads/O for input/output are formed on the outer periphery of each semiconductor chip 9 at the master wafer stage, and unwired pads/O are formed in the center of the semiconductor chip 9. A peripheral cell 12 is formed in a region between the reference cell 11 and the bonding pad /O.

A plurality of output buffer circuits 13 and a plurality of input buffer circuits 14 are formed in each peripheral vO cell 12. Each output buffer circuit 13 is a small circuit having a capacity of about 2 mA, whereas the maximum output current of the conventional output bag 77 circuit 7 shown in FIG. 3 is about 5 mA. Similarly, the input buffer circuit 14 has a smaller capacity than the conventional input buffer circuit 8.

The input terminals and output terminals of all the output buffer circuits 13 and input buffer circuits 14 are not wired and are in an open state.

Next, when performing personalized wiring, a plurality of output buffer circuits 13 are wired in parallel according to the required output current using a manufacturing process using conventional semiconductor integrated circuit technology, and their output terminals are connected to input/output bonding pads/O By connecting the input terminal to the circuit of the reference cell 11, the input/output bond/pad/O can be used as an output pad from which a predetermined current output can be obtained.

On the other hand, when the input/output bonding pad /O is used for inputting signals from the outside, input buffer circuits 14 are connected in parallel as appropriate, and their input terminals are connected to the input/output bonding pad /O, and the output terminal is connected to the reference cell. Connect each to the 11 side.

In this way, by forming the small-capacity human cover sofa circuit 14 and the output buffer circuit 13 in advance around the input/output bonding pad/O, the output power and Input power can be set, improving design freedom.

Although this embodiment includes the output sofa circuit 13 and the input buffer circuit 14, either one of the buffer circuits may be formed.

FIG. 2 shows still another embodiment, in which the arrangement of the output buffer circuit 13 and input buffer circuit 14 provided in the peripheral cells 12 of the embodiment shown in FIG. A group of input buffer circuits 13 and a group of input buffer circuits 14 are formed so as to face each other.

According to this embodiment, when the output 7777 circuits 14 or the input buffer circuits 13 for each desired power type are formed in parallel by personalized wiring, the wiring can be easily performed.

In the above two embodiments, when performing personalized wiring, the input buffer circuit 14 and the input/output bonding pad 1o are connected via an input protection circuit to protect the internal circuit from external static electricity, etc. shall be carried out. Although not shown, the input protection circuit is formed near each input/output bonding pad /O, for example.

(Effects of the Invention) As explained above, according to the present invention, for each bonding layer formed on each semiconductor chip at the master wafer stage, a plurality of input buffer circuit groups and/or By providing a peripheral cell in which a plurality of output buffer circuit groups having predetermined input/output characteristics are formed, and by connecting an appropriate number of input buffer circuits and/or output buffer circuits in parallel when wiring Since the output characteristics can be set appropriately, design flexibility is increased, and a master slice integrated circuit device that can be used in a wide range of fields can be provided.

[Brief explanation of drawings]

FIG. 1 is a block diagram of main parts showing one embodiment of a master slice integrated circuit device according to the present invention, FIG. 2 is a block diagram of main parts showing another embodiment, and FIG. 3 is a block diagram of main parts of a conventional mask slice integrated circuit device. FIG. 9: Semiconductor chip/O: Input/output bonding pad 11: Reference cell 12: Peripheral force cell 13: Output cover sofa circuit 14: Input buffer circuit (and 2 others) 1st Figure 1X2rl! J

Claims (1)

[Claims] It is equipped with an input/output bonding pad, a reference cell having a plurality of semiconductor elements, and a peripheral I/O cell with personalized wiring for transmitting and receiving signals between the input/output bonding pad and the reference cell. In the master slice integrated circuit device, the peripheral I/O cells include a plurality of input buffer circuit groups having predetermined input/output characteristics and/or a plurality of output buffer circuit groups having predetermined input/output characteristics, and the peripheral I/O cells are provided with a plurality of input buffer circuit groups having predetermined input/output characteristics, and are connected to A master slice integrated circuit device characterized by having a configuration in which an input buffer circuit and/or an output buffer circuit are connected in parallel.