JPH0438869A - Master slice semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To greatly enhance the degree of design freedom by allowing at least one of a plurality of cell arrays to make different the size of a circuit device in a unit cell which constitutes said cell arrays from the size of a circuit device in other cell arrays. CONSTITUTION:A plurality of input/output cells 4 are formed on each end of the four sides of a single semiconductor chip 1. Inside these I/O cells 4 are laid out in parallel first cell arrays 20A, where first unit cells 2A containing a smaller-sized circuit device are arrayed unidimensionally, and second cell arrays 20B, where second unit cells 2B containing a larger-sized circuit device are arrayed. Three first arrays 20A are arranged to be present between two second cell arrays 20B. Each unit cell, say, 2A and 2B is designed to provide equivalent functions respectively. However, since the circuit device for the second unit cell 2B is larger-sized than that of the first unit cell 2A, a larger capacity load drive power is embodies here.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a master slice type semiconductor integrated circuit.

[Conventional technology]

As a design method for semi-custom ICs (integrated circuits), the mass-slice method, which requires a short development period and is low in development cost, is widely used. Usually multiple transistors (
In ECL circuits, unit cells (including resistive elements) are arranged in an array on a semiconductor chip, and ICs with various specifications can be realized by simply changing the connections between the elements and the connections between the unit cells. can.

Specifically, as shown in FIG. 3, a cell array 20 in which a plurality of unit cells 2 are arranged one-dimensionally is formed on a semiconductor chip 1, and a plurality of cell arrays 20 are arranged in parallel to form a plurality of units. Cell 2 is arranged two-dimensionally. Then, wiring 3 is formed in the area between the cell arrays 20 to interconnect each unit cell 2, and input/output cells 4 provided at the end of the chip 1.
It is also connected to realize an IC consisting of cells shown with diagonal lines.

FIG. 4 shows a master slice type semiconductor integrated circuit of a type in which a cell array 20 is also formed in the wiring area, and this is called a Sea or Gate 11.

Here, the operating frequency of devices in which semi-custom ICs are used is increasing year by year, and the speed required of semi-custom ICs is also increasing.

[Problem to be solved by the invention]

However, in master slice type semiconductor devices, connections between cells are generally made by automatic wiring, so the wiring length tends to be long, and the resulting increase in wiring capacity makes it difficult to increase the operating speed of the IC by fully customizing the design. It decreases in comparison. Therefore, the above problem can be alleviated by allocating circuits with high capacitive load driving power in advance to important parts that determine the operating speed of the IC. However, in a conventional master slice type semiconductor device in which unit cells of one type are arranged in an array, there is little freedom in design, and no major improvement can be expected.

An object of the present invention is to provide a master slice type semiconductor integrated circuit that achieves the above-mentioned problems.

Means for Solving Problem C] The master slice type semiconductor integrated circuit according to the present invention is configured to include a plurality of circuit elements, and is arranged in a cell array by arranging a plurality of unit cells, each having an equivalent function, in one dimension. In a device in which unit cells are arranged two-dimensionally by arranging a plurality of cell arrays in parallel, at least one of the plurality of cell arrays is connected to a circuit element in the unit cell constituting the cell array. The size of the cell array is different from the size of circuit elements in other cell arrays.

[Effect]

According to the present invention, a circuit that requires high load driving power can be assigned to a cell array that includes large-sized circuit elements.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 and FIG. 2 are plan views of a master slice type semiconductor integrated circuit according to an embodiment, and FIG.
The figure corresponds after wiring. As shown in FIG. 1, a plurality of input/output cells 4 are formed at each end of the four sides of a single semiconductor chip 1. As shown in FIG. Inside these, there is a first cell array 20A in which two first unit cells containing small-sized circuit elements are arranged in one dimension, and a second unit cell 2B containing large-sized circuit elements. The second one that is arranged in one dimension
The cell arrays 20B are arranged in parallel to each other. And between the two second cell arrays 20B, there are 3
A first cell array 2OA is interposed therebetween.

Here, the above-mentioned circuit elements include transistors, diodes, and also resistive elements as necessary.

Each unit cell 2A, 2B is designed to have an equivalent function. However, compared to the first unit cell 2A, the second unit cell 2B has more circuit elements (
e.g. MESFET) is larger (e.g. twice)
Therefore, larger capacitive load driving force is achieved.

FIG. 2 shows a state in which a desired circuit is realized by wiring the Sea of Gate type semiconductor chip 1 for master marization as described above. As shown in the figure, a desired IC is realized by connecting the circuit elements of cells indicated by diagonal lines with wiring 3. Here, the normal I
In C, the gate usage rate is 40-50%, so
A cell area not actually used for the IC is used as an interconnection area. That is, by using planarization technology in the semiconductor process, the cell area can also be easily used as a wiring area. Then, the first unit cell 2A and the second unit cell 2B are selected and used according to the operating speed and load driving force required of the IC to be realized. This makes it possible to greatly improve the degree of freedom in design without being affected by the degree of integration of the IC.

The present invention is not limited to the above embodiments, and various modifications are possible.

For example, in the embodiment, one second cell array 20B is provided between three first cell arrays 2OA, but the ratio may be one in every two, or one in every four.

〔Effect of the invention〕

As described above in detail, according to the present invention, a circuit requiring high load driving power can be assigned to a cell array including large-sized circuit elements. For this reason, I
The design freedom of C can be greatly improved.

20B...Second cell array, 3...Wiring, 4
...Input/output cell.

Claims (1)

[Scope of Claims] A cell array is constructed by arranging a plurality of unit cells that include a plurality of circuit elements and each having the same function in one dimension, and a plurality of the cell arrays are arranged in parallel. In the master slice type semiconductor integrated circuit in which the unit cells are arranged two-dimensionally, at least one of the plurality of cell arrays has a size of the circuit elements in the unit cells constituting the cell array. A master slice type semiconductor integrated circuit having a size different from that of the circuit elements in the cell array.