JPS6381945A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To improve the utilization of the area of a semiconductor chip, and to scale down the size of the chip by fractionating and forming the size of a fundamental cell constituting a peripheral circuit section to small sections in the same manner as a fundamental cell organizing an internal circuit section and using an arbitrary number of the fundamental cells. CONSTITUTION:An internal circuit section 2 is constituted arbitrarily of a large number of fundamental cells 21, to each of which predetermined circuit elements are shaped. The internal circuit sec tion 2 can have an optional logic circuit function by determining only wiring patterns in the fundamental cells and among the fundamental cells in response to order specifications from users. A peripheral circuit section 3 is positioned among the internal circuit section 2 and terminal pads 4. The peripheral circuit section 3 has a large number of fundamental cells 51, 52 in the same manner as the internal circuit section 2. A large number of the fundamental cells 51, 52 formed to the peripheral circuit section 3 are each disposed under the state in which two kinds of the fundamental cell 51 for an input buffer and the fundamental cell 52 for an output buffer are paired.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to semiconductor integrated circuit device technology, and further to technology that is effective when applied to logic semiconductor integrated circuit devices. It is about effective techniques.

[Prior Art] When configuring a semiconductor integrated circuit device for logic, if it is a high-mix, low-volume production device, for example, the method described in "Nikkei Electronics," published by Nikkei McGraw-Hill, June 1985, is used.
It is advantageous to use a gate array such as that described in "Monthly 3rd issue", pages 151-177 (Explanation: Gate array market approaching 100 billion yen). By using this gate array, it is possible to easily meet a wide variety of specification requests from users simply by changing the wiring pattern.

FIG. 10 shows an outline of the planar layout configuration of the gate array.

As shown in the figure, the gate array 1 includes an internal circuit section 2,
It has a peripheral circuit section 3 and a terminal pad 4.

The internal circuit section 2 is arbitrarily constituted by a large number of basic cells 21 each having a predetermined circuit element formed therein. This internal circuit section 2 can have any logic circuit function by determining only the wiring patterns within the basic cells and between the basic cells according to the specifications ordered by the user.

Note that 22 is a wiring area, which is used for wiring between basic cells.

The peripheral circuit section 3 has a large number of input/output buffer circuits 31. This input/output buffer circuit 31 forms a kind of interface between the internal circuit section 2 and the terminal pad 4, and the input/output buffer circuit 31 provided for each terminal pad 4 is Depending on the wiring pattern determined according to the specifications ordered by the user, it can function as an input-only buffer, an output-only buffer, or an input/output buffer.

In this case, the size of each output buffer circuit 31 is determined by the maximum rated output capacity Ji(L(
It is formed sufficiently large so that the maximum sink current capacity at the time of output (low level) can be obtained. This allows any input/output buffer circuit 31 to function as an output buffer with a large output capacity.

[Problems to be Solved by the Invention] However, the inventors have found that the above-mentioned technique has the following problems.

In other words, in a gate array that is provided with a wide variety of functions according to the specifications ordered by the user, all of the numerous input/output buffer circuits provided therein are configured as output buffers with the maximum rated output capacity. In most cases, only some human output buffer circuits require an output capacity close to the maximum rating, and most other human output buffer circuits do not. In many cases, an output capacitance much smaller than the maximum rating is sufficient. In such cases, all input/output buffer circuits should be made large from the beginning to accommodate the maximum rated output capacitance. The present inventors have clarified that this wastes the limited area of a semiconductor chip, and is one of the major factors preventing the reduction of the chip area.

An object of the present invention is to optimize the size of the input/output buffer circuit portion of the gate array without sacrificing the inherent advantage of being able to easily respond to a wide variety of customer specifications. Improves the efficiency of chip area utilization and enables reduction of its size.
Our goal is to provide this technology.

The above and other objects and novel features of the present invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for Solving the Problems] A brief overview of typical inventions disclosed in this application is as follows.

That is, the peripheral circuit section is made up of basic cells in the same way as the internal circuit section, and the size of the basic cells making up the peripheral circuit section is further subdivided into smaller sizes in the same way as the basic cells making up the internal circuit section. By using an arbitrary number of these subdivided basic cells, an appropriately sized human output buffer circuit having necessary and sufficient output capacity can be arbitrarily constructed.

[Operation] According to the above-described means, an input/output buffer circuit having an arbitrary output capacity can be configured by using a plurality of basic cells in parallel.

Therefore, depending on the number of basic cells used to configure the input/output buffer circuit, each input/output buffer circuit can have an optimal output capacity according to the user's various order specifications. . Also,
Since the output capacity of the human output buffer circuit can be selected depending on the number of basic cells used in parallel, it is possible to construct an economical human output buffer circuit with a small output capacity and small size, while still exceeding the conventional maximum rating. It also becomes possible to construct a human output buffer circuit with a larger output capacity than that of the present invention. Furthermore, the remaining basic cells can be effectively used as logic circuits that supplement the functions of the internal circuit section or as independent buffer circuits.

In this way, the size of the output buffer circuit can be optimized without sacrificing the inherent advantage of gate arrays that they can easily accommodate a wide variety of customer specifications, and this allows semiconductor chips to Improve the efficiency of use of area and enable reduction of its size.
That purpose is achieved.

[Examples] Hereinafter, preferred embodiments of the present invention will be described based on the drawings.

In each figure, the same reference numerals indicate the same or corresponding parts.

FIG. 1 shows an example of a planar layout state of a gate array to which the technology according to the present invention is applied.

The gate array 1 shown in the figure first has an internal circuit section 2, a peripheral circuit section 3, and a terminal pad 4.

The internal circuit section 2 is arbitrarily constituted by a large number of basic cells 21 each having a predetermined circuit element formed therein. This internal circuit section 2 can have any logic circuit function by determining only the wiring patterns within the basic cells and between the basic cells according to the specifications ordered by the user.

Note that 22 is a wiring area, which is used for wiring between basic cells.

The peripheral circuit section 3 is located between the internal circuit section 2 and the terminal pad 4. This peripheral circuit section 3 has a large number of basic cells 51 and 52 similarly to the internal circuit section 2. A large number of basic cells 51 and 52 formed in the peripheral circuit section 3 are arranged in pairs of two types: input buffer basic cells 51 and output buffer basic cells 52. Each of the basic cells 51 and 52 is formed by being subdivided into sizes that are approximately the same size as the basic cell 21 in the internal circuit section 2. In this case, the input buffer basic cell 51 includes circuit elements necessary to configure the interface section, such as a diode for forming an electrostatic breakdown prevention element. On the other hand, the output buffer basic cell 52 includes circuit elements for configuring an output interface, and these circuit elements are equivalent to those included in the basic cell 21 in the internal circuit section 2. That's fine.

Here, basic cells 51 and 52 arranged in the peripheral circuit section 3
As exemplified below, is used to configure interface circuits such as output buffers and input buffers, and if necessary, configures a logic circuit that supplements the circuit function of the internal circuit section 2 or an independent buffer circuit. It is also used to.

FIGS. 2(a) and 2(b) show a first usage example of the basic cell 52 of the peripheral circuit section 3 described above. An output buffer is formed.

3(a) and 3(b) show a second usage example of the basic cell 52 of the peripheral circuit section 3 described above. In the example shown in the figure, two sets of output buffer basic cells 52 are operated in parallel. By connecting them in such a manner, an output buffer with a medium output capacity having an output capacity approximately twice that shown in FIGS. 2(a) and 2(b) is formed.

FIGS. 4(a) and 4(b) show a third usage example of the basic cell 52 of the peripheral circuit section 3 described above. In the example shown in the figure, three sets of output buffers, one set more than those described above, By connecting the basic cells 52 so as to operate in parallel, an output buffer with a large output capacity having an output capacity approximately three times that shown in FIGS. 2(a) and 2(b) is formed.

FIGS. 5(a) and 5(b) show a fourth usage example of the basic cells 51 and 52 of the peripheral circuit section 3 described above.
The two sets of input buffer basic cell 51 and output buffer basic cell 52 form an independent buffer circuit that passes from terminal pad 4 to terminal pad 4 without passing through internal circuit section 2.

FIGS. 6(a) and 6(b) show a fifth usage example of the basic cells 51 and 52 of the peripheral circuit section 3 described above.
Three sets of input buffer basic cells 51 and output buffer basic cells 52 form an independent buffer circuit with a larger capacity than those shown in FIGS. 5(a) and 5(b).

FIGS. 7(a) and 7(b) show a sixth usage example of the basic cells 51 and 52 of the peripheral circuit section 3 described above.
Three sets of input buffer basic cells 51 and output buffer basic cells 52 independently form a three-person logic circuit.

FIGS. 8(a) and 8(b) show a seventh usage example of the basic cell 52 of the peripheral circuit section 3 described above. In the example shown in the figure, three sets of output buffer basic cells 52 constitute an output buffer circuit having a three-manpower type logic function.

FIG. 9 (a>(b) shows an eighth usage example of the basic cells 51 and 52 of the peripheral circuit section 30 described above. In the example shown in the figure,
The input buffer basic cell 51 and the output buffer basic cell 52 of the peripheral circuit section 3 are used to configure a logic circuit that supplements the circuit function of the internal circuit section 2. In this case, the output signal from the internal circuit section 2 is transferred to the output buffer basic cell 5.
2 to the input buffer basic cell 51, and the output signal from the input buffer basic cell 51 is input again to the internal circuit section 2. As a result, the input/output buffer basic cells 51 and 52 have a level conversion function, and there is no level change between the input signal of the output buffer basic cell 52 and the output signal from the input buffer basic cell 51. 2. In fact, the input buffer basic cell 51 has the function of converting the TT level to the CMOS level, and the output buffer basic cell 52 has the function of converting the CMOS level to the TTL level. Basic cell 51 for input/output buffer
．． If the 52 does not have a level conversion function, there is not much need to do the above.

As described above, by using a plurality of basic cells 51 and 52 in parallel, an input/output buffer circuit having an arbitrary output capacity can be constructed. Therefore, the basic cell 5 used to configure the input/output buffer circuit
By using the number 1.52, each input/output buffer circuit can be arbitrarily provided with an optimal output capacity according to a wide variety of user's order specifications. In addition, since the output capacity of the input/output buffer circuit can be selected depending on the number of basic cells 51 and 52 used in parallel, an economical input/output buffer circuit with small output capacity and small size can be constructed. It also becomes possible to construct a human output buffer circuit with a large output capacity exceeding the conventional maximum rating. Furthermore, the remaining basic cells 5], , 52 can be effectively used as logic circuits to supplement the functions of the internal circuit section or as independent buffer circuits.

As described above, it is possible to optimize the size of the human output buffer circuit portion in the peripheral circuit section 3 without sacrificing the inherent advantage of the gate array that it can easily accommodate a wide variety of ordered specifications from users. . This achieves the objective of increasing the utilization efficiency of the semiconductor chip area and making it possible to reduce its size.

Above, the invention made by the present inventor has been specifically explained based on the examples, but it should be noted that the present invention is not limited to the above examples and can be modified in various ways without departing from the gist thereof. Needless to say, for example, the basic cells 51 and 52 of the peripheral circuit section 2 are replaced with the basic cells 2 of the internal circuit section 2.
1 may be arranged together in the same area.

In other words, the distinction between the peripheral circuit section 2 and the internal circuit section 3 may be eliminated, or the contents of the basic cells 21 in the internal circuit section 2 may be the same as the contents of the basic cells 51 and 52 in the peripheral circuit section 3. In other words, the types of cells formed in the gate array 1 may be unified to only one.

In the above explanation, the invention made by the present inventor was mainly applied to gate arrays, which is the background field of application, but the invention is not limited to this. For example, PLA (programmable logic・It can also be applied to standard cell type semiconductor integrated circuit devices, etc.

[Effects of the Invention] The effects obtained by typical inventions disclosed in this application are briefly explained below.

In other words, the size of the output buffer circuit can be optimized without sacrificing the inherent advantage of gate arrays, which is that they can easily accommodate a wide variety of customer specifications. The effect is that the efficiency can be increased and the size can be reduced.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a planar layout state of a gate array to which the technology according to the present invention is applied, and FIGS. 3(a) and 3(b) are diagrams showing a second usage example of the basic cell formed in the peripheral circuit portion of the gate array shown in FIG. 4(a) and 4(b) are diagrams showing a third usage example of the basic cell formed in the peripheral circuit portion of the gate array shown in FIG. 1, and FIG. Figures 6(a) and 6(b) show a fourth usage example of basic cells formed in the peripheral circuit part of the gate array shown in Figure 1. 7(a) and 7(b) are diagrams showing a sixth usage example of the basic cell formed in the peripheral circuit portion of the gate array shown in FIG. 1; Figures (a) and (b) are diagrams showing a seventh usage example of the basic cell formed in the peripheral circuit section of the gate array shown in Figure 1, and Figures 9 (a) and (b) are shown in Figure 1. FIG. 10 is a diagram showing a planar layout state of a gate array studied prior to the present invention. 1...Semiconductor integrated circuit device (gate array), 2...
- Internal circuit section, 21... Basic cell formed in the internal circuit section, 3... Peripheral circuit section, 51... Basic cell for input buffer formed in the peripheral circuit section, 52... Peripheral circuit Output buffer basic cell formed in the section, 4...terminal pad. Fig. 1 Fig. 2 Crt) Fig. 3 (Regigu Fig. (b, 1 Fig. 5 6 (6L) (b)

Claims (1)

[Claims] 1. An internal circuit section in which an arbitrary circuit function is configured by a large number of basic cells each having a predetermined circuit element formed therein; a terminal pad for external connection; the internal circuit section and the above; A semiconductor integrated circuit device comprising an input/output buffer circuit interposed between a terminal pad and an input/output buffer circuit, the basic cell for an input buffer including circuit elements for configuring an input interface section, and a circuit element for configuring an output interface section. A large number of output buffer basic cells including circuit elements are formed in each subdivided section, and by using any number of these buffer basic cells, an output buffer circuit having an arbitrary output capacity can be constructed. A semiconductor integrated circuit device characterized by: 2. The semiconductor integrated circuit device according to claim 1, wherein the buffer basic cell constitutes an independent logic circuit outside the internal circuit section. 3. The basic cell for buffer is formed by being subdivided into the same size as the basic cell of the internal circuit section, as set forth in claim 1 or 2. semiconductor integrated circuit devices.