JPH02143458A - Gate array device - Google Patents

Abstract

PURPOSE:To improve gate transmission efficiency, and reduce delay time by arranging basic cells for logic and basic cells for driver in two different arrays, and connecting the basic cells for driver only with logic gates requiring high operating power. CONSTITUTION:A basic cell is separated by basic cells 11 for logic constituted of C-MOS's and basic cells 13 for driver constituted of bipolar transistors, which are arranged as arrays 12a-12e and 14a, 14b, respectively. The cell 13 is connected only with logic gate parts requiring high driving power at the time of operation. Thereby, the bipolar transistors for driver use can be effectively utilized, and the increase of delay time caused by connecting drivers with low load logic gates can be avoided.

Description

Detailed Description of the Invention (Industrial Application Field) The present invention relates to a gate array device with an improved basic cell structure, and particularly to a BiCMO3 type gate array in which complementary MOS transistors and bipolar transistors are integrated. Concerning improvements to equipment.

(Prior Art) In a conventional BiCMO3 type gate array device, as shown in FIG. 2, a column array 2 composed of a plurality of basic cells 1 is arranged on a wafer 3. Reference numeral 4 indicates an input/output interface cell. A space for wiring is provided around each column array 2. As the arrangement structure of the basic cells 1, various arrangement structures such as a matrix arrangement are adopted in addition to the column arrangement shown in the figure.

By the way, the B iCMO3 type gate agate array device cell 1 includes a plurality of MOs for forming a logic gate.
It has a structure in which an S transistor and a plurality of bipolar transistors for drivers are integrated. This is to reduce power consumption by assembling the logic using CMOS, and to enable driving of high loads by using bipolar transistors for drivers.

(Problem to be Solved by the Invention) Gates that need to be driven using bipolar transistors in a circuit, that is, gates that require high driving ability, are input-connected to a bus driver, clock driver, or logic gate. The number of output gates and the like is not that large, so a considerable number of bipolar transistors could not be used. That is, the number of bipolar transistors that is equal to the number of conventional BiCMO3 type gate agate array devices is often mounted, resulting in unnecessary bipolar transistors.

This pressure will be explained in more detail with reference to the drawings. A conventional BiCMO3 type gate agate array device has a configuration shown in FIG. 4, for example.

This basic cell includes six MOS transistors 21 to 26 for logic configuration and two bipolar transistors 27 .
It has 28. When configuring the D-type flip-flop shown in FIG. 3 using such basic cells,
A basic cell of 4fl must be used. In two of these basic cells, driver bipolar transistors 27 and 28 are used, but in the remaining two basic cells, bipolar transistors 27 and 28 are not used.

In this way, one or more bipolar transistors exist in one basic cell, so if many basic cells are used to configure a logic gate with few output terminals, many bipolar transistors was not used and wasted.

Furthermore, even though the load gate is low, when a bipolar transistor for the driver is used, the delay time may become longer.

Therefore, in the conventional BiCMO3 type gate array device,
Since the driver bipolar transistor is integrated within the basic cell, there is a problem that the gate usage efficiency is not sufficient and the delay time becomes long in some cases.

Furthermore, there is a problem in that it is difficult to design the logic cell, and the logic cell must be designed in accordance with the position where the bipolar transistor is provided.

SUMMARY OF THE INVENTION An object of the present invention is to provide a gate array device having a structure that has excellent gate usage efficiency, can shorten delay time, and can easily design logic cells.

(Means for Solving the Problems) A gate array device of the present invention includes a first array in which a plurality of basic logic cells for forming a logic gate are arranged, and a gate array device for driving high-load gates in a circuit. and a second array in which a plurality of driver basic cells are arranged, thereby achieving the above object.

(Function) The present invention has been achieved by focusing on the fact that a driver cell is not necessarily required for all logic gates.
The basic cells are divided into logic basic cells and driver basic cells, which are arranged separately to form first and second arrays. That is, since the logic basic cells and the driver basic cells are arranged separately in the first and second arrays, it is only necessary to connect the driver basic cells to the logic gates that require high driving capability. Therefore, the driver basic cell can be effectively utilized. Further, since it is not necessary to connect the driver basic cell to the low load logic gate, there is no increase in delay time due to the driver basic cell connected to the low load gate portion.

(Example) FIG. 1 shows an example of the present invention. In this embodiment, a first array 12 in which a plurality of logic basic cells 11 for configuring logic gates are arranged on a silicon wafer 10.
a to 12e are arranged. Further, in order to drive the high-load gate, the second arrays 14a and 14b in which a plurality of driver basic cells 13 are arranged are connected to the first array 1.
2a to 12e are arranged separately.

That is, in this embodiment, in the BiCMO3 type gate agate array device, the basic cells are separated into a logic basic cell 11 made up of CMO8 and a driver basic cell 13 made up of bipolar transistors. and are arranged as first arrays 12a to 12e and second arrays 14a and 14b, respectively. Each array 12a-12e, 14a, 14b is spaced apart. This is to provide space for wiring.0, t, symbols 15a and 15b are respectively
Input cuff/output interface cell is shown.

In this embodiment, among the parts constituting the basic cell, a logic basic cell 11 consisting of a logic gate CMO 8 and a driver basic cell 13 consisting of a bipolar transistor are arranged separately, so that high It is sufficient to connect the driver basic cell 13 only to the logic gate portion that requires driving capability. That is, since the driver basic cell 13 is connected only to the necessary logic basic cell 11,
It becomes possible to effectively utilize the driver bipolar transistor. In addition, the logic basic cell 1 of the low load part
Since there is no need to connect the driver basic cell 13 to the logic gate 1, there is no risk of an increase in delay time caused by connecting the driver to the low-load logic gate.

Furthermore, since the number of logic basic cells 11 that need to be connected to the driver basic cells 13 is relatively small, the number of driver basic cells 13 can be reduced compared to the logic basic cells 11. Specifically, it is possible to reduce the number of unused elements, thereby increasing the degree of integration and gate usage efficiency.

The effects of this embodiment will be explained in more detail with reference to the drawings.

In this embodiment, the logic basic cell 11 shown in FIG.
and the basic driver cells 13 shown in FIG. 13(b) are arranged separately as first and second arrays.

The logic basic cell 11 consists of four MOS) transistors 3
1 to 34. On the other hand, the driver basic cell 13 in FIG. 5(b) is provided with two bipolar transistors 36 and 37.

As mentioned above, when constructing, for example, the D-type flip-flop shown in FIG. 3 using a conventional gate array device, there will be unused driver transistors in the basic cell. In contrast, in this embodiment, the third
When constructing the D-type flip-flop shown in the figure, five logic basic cells 11 and two driver basic cells 13 are used. In this way, in this embodiment, only the necessary number of bipolar transistors need be connected, so that it is possible to increase the usage efficiency of the bipolar transistors.

In the illustrated embodiment, the logic basic cells 11 and the driver basic cells 13 are arranged in rows in the horizontal direction in the drawing.
, the second arrays 12a to 12e, 14a, and 14b have been shown, but it goes without saying that the arrangement B of each array is not limited to the columnar arrangement shown, but may be arbitrarily changed in addition to the matrix arrangement.

(Effects of the Invention) As described above, according to the present invention, the logic basic cells and the driver basic cells are arranged separately as the first and second arrays. A driver basic cell can be connected and used only to logic basic cells that require driving capability.

Therefore, in the conventional example, a driver is connected to a low-load logic gate, which may increase the delay time, whereas in the present invention, a driver basic cell is used without connecting a low-load logic basic cell. Since it is easy to do this, it becomes possible to effectively prevent such an increase in delay time, and furthermore, the number of driver basic cells that need to be connected to the logic basic cells can be relatively reduced. If the number of driver basic cells is made smaller than the number of logic basic cells, the number of unused elements can be reduced and gate usage efficiency can be increased.

Furthermore, in conventional gate array devices, the logic cells had to be designed according to the positions where the bipolar transistors were formed, but in the present invention, the driver basic cells are designed separately from the logic basic cells. Since the logic cells are arranged as an array, it is easy to design the logic cells.

4,...'LM day Figure 1 is a plan view showing a part of an embodiment of the present invention, Figure 2 is a schematic plan view of a conventional example, and Figure 3 is a circuit diagram showing an example of a logic gate. FIG. 4 is a plan view showing an example of the structure of a basic cell in the conventional example, FIG. 5(a) is a plan view showing a logic basic cell, and FIG. 5(b) is a plan view showing a driver basic cell. It is.

11...Logic basic cells, 12a to 12e...first
array, 13...driver basic cell, 14a, 1
4b...Second array.

that's all

Claims (1)

[Claims] 1. A first array in which a plurality of logic basic cells are arranged to form a logic gate, and a second array in which a plurality of driver basic cells to drive high-load gates in the circuit are arranged. A gate array device comprising an array of.