JP3335460B2 - Semiconductor device with standard cell - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a master slice standard cell, and more particularly to a structure of a basic cell constituting a standard cell and a semiconductor device in which the basic cell is arranged and wired.

[0002]

2. Description of the Related Art In general, a basic cell constituting a standard cell has a structure shown in FIG. 5A, and has a drain electrode (hereinafter referred to as VDD) and a ground electrode (hereinafter referred to as GND). Are unified in the Y direction, and the layout is extended in the X direction according to the circuit configuration of the cell. Note that the Y direction refers to the direction of the channel width (also referred to as a transistor width) of a transistor constituting a basic cell, in other words, the height direction, and the X direction refers to the channel length direction. For example, when the transistor width W is doubled in the inverter, as shown in FIG.
The layout is such that the cell is extended in the direction and the transistor is divided. Further, even in the prior art, a power supply line is extended in the Y direction to form cells having different heights in the Y direction. Bends and the cell arrangement area is lost. FIG. 5D shows a legend of the diagrams shown in FIGS. 5 and 6.

Further, when an inverter serves as a buffer,
As shown in FIG. 5C, the cell is further extended in the X direction. Here, in the case of FIG.
Assuming that the wiring use layer is metal 1, metal 2, and a via connecting between metal 1 and metal 2 when the wiring area is considered to be a wiring area other than DD and GND, as shown in FIG. In other words, although the transistor region can protrude in the Y direction, when the wiring region between cells is narrower than the protruding region 100, as shown in the wiring region A in FIG.
There is a drawback determined by the 0 placement restriction. Further, since the protruding region cannot be used because the metal 1 and the contact layer are wiring regions, only the extension of the transistor width W (field, poly) can be protruded and the source and drain regions of the transistor can be contacted. Therefore, when the transistor width is large, the transistor characteristics may vary depending on the arrangement of the contacts with respect to the field width as shown in FIG.

For example, in a processor layout,
An interface circuit provided between an instruction control unit having a microcode ROM, a PLA, and the like, and a data bus unit that latches an instruction control signal and creates a control signal for the data bus unit via a random circuit (such as a decoder). In the case of using the standard cell layout in the layout of FIG. 1, the interface circuit is composed of an instruction control signal latch circuit 101 and a random circuit 10 as shown in FIG.
2. The data bus section is classified into the drive buffer section 103 and has the following circuit configuration. The latch circuit unit 101 includes a flip-flop circuit (hereinafter, referred to as FF) 104 or a latch, and receives a clock from outside the interface circuit. In order to avoid a malfunction due to skew between clocks, the latch circuit unit 101 is arranged as close to the microcode ROM and PLA as possible and at an equal position, for example, arranged in the same column (row: ROW), or makes the clock supply line one. An arrangement in two rows is preferred.

[0005] The random circuit section 102 includes a latch circuit section 1
01 is an area in which wiring load is increased due to decoding, pitch matching to a data bus, decoding, and the like. The driving buffer unit 103 requires a buffer having a large transistor width to drive the data bus unit. When a conventional basic cell is used, the above-described cell extended in the X direction or a protruding cell is used. Is used. Further, when considering signal propagation, it is desirable that the buffer be disposed on the data bus side as much as possible.

When the interface circuit is laid out by the standard cell method, the layout density may be reduced depending on the circuit scale of the latch circuit section 101, the random circuit section 102, and the buffer circuit section 103. For example, as shown in FIG. 10, when the number of the latch circuit units 101 is larger than that of the other random circuit units 102 and the buffer circuit unit 103, the size of the latch circuit unit 101 in the X direction is limited. Further, when the buffer circuit unit 103 is small,
Since the buffer circuit portion 103 has a small wiring load, the wiring region is wasted due to the above-mentioned protrusion, and furthermore, the wiring region portion due to the above-mentioned protrusion cannot be contacted, so that the performance may be insufficient as a buffer for the data bus portion. . In FIG. 10, "B" is a buffer circuit,
"R" indicates a random circuit, "FF" indicates a latch circuit, wiring in the X direction is metal 1, wiring in the Y direction is metal 2, black circles indicate output terminal positions, and thick lines indicate VDD and GND. The present invention has been made to solve such a problem, and an object of the present invention is to provide a semiconductor device having standard cells effective for circuit layout.

[0007]

SUMMARY OF THE INVENTION The present invention is a semiconductor device having a standard cell including a basic cell in which an N-channel transistor and a P-channel transistor are arranged in a channel width direction between a drain electrode region and a ground electrode region. A first basic cell in which the layout of the N and P channel transistors is extended in the channel length direction without changing the size in the channel width direction; and the basic cell in which the size in the channel width direction is constant is connected to the drain electrode region. Alternatively, there is provided a second basic cell which is extended by a natural number times in the channel width direction with the ground electrode region as a target portion.

[0008]

With this configuration, when the standard cells are laid out by mixing the first basic cells and the second basic cells, the difference in the length in the channel width direction between the first basic cells and the second basic cells. As a result, an empty area is generated in the semiconductor device. This empty area can be used, for example, as a wiring area. As described above, the first basic cell and the second basic cell work to effectively perform a circuit layout. In the embodiment, the first basic cell corresponds to a single cell, and the second basic cell corresponds to a multiple of 2 or more.

[0009]

FIG. 1 shows a basic cell configuration in one embodiment of a semiconductor device having a standard cell according to the present invention. The basic cell shown in FIG. 1 has a layout configuration which is twice the height of the conventional basic cell shown in FIG. 5A in the channel width direction, which is folded around the VDD portion. Hereinafter, such a basic cell having twice the height in the channel width direction is referred to as a “double cell”, and the basic cell shown in FIG. 5A is referred to as a “single cell”. In FIG. 1, a portion indicated by reference numeral “1” is a 1 × cell, and a portion indicated by reference numeral “2” is a 2 × cell. Further, in a double-height cell, each VDD, GN
D has the same position and the same width in the channel width direction as the 1 × cell, and can be adjacently connected to either the basic cell located below or above the 2 × cell shown in FIG. And

In the above-described example of the inverter and the FF circuit having a large transistor width, for example, the FF shown in FIG.
Like a circuit, it is a basic cell having a height twice the normal in the channel width direction. Also, within the double cell, all layout layers can be arranged in the same manner as a normal single cell, and there is no restriction as a wiring area. Therefore, the degree of freedom in the arrangement of the contacts in the contact arrangement of the source and drain regions of the transistor portion is higher than that in the case of the conventional cell in which the contact extends to the wiring region. Further, it is also possible to arrange a circuit area including wirings other than protrusions, such as a slave part of an FF circuit. Further, the double cell has a height twice as large as a normal single cell, so that the size can be reduced by about 1/2 in the channel length direction.

Further, in this embodiment, the basic cell has an example of twice the height in the channel width direction. However, as shown in the CONT5 signal portion shown in the interface circuit example of FIG.
When the F circuits are connected in two stages, a configuration that is four times as high can be employed. That is, the number N of stages in the channel width direction is a natural number.

FIG. 3 shows an equivalent arrangement and wiring example in the case where the basic cell according to the present embodiment is used for the conventional interface circuit shown in FIG. In the arrangement of the standard cells, for example, double cells such as the buffers B0 to B7 and the FF circuit FF0 are dispersed and arranged at the left and right edges of the entire semiconductor device, and a portion sandwiched between these double cells. A random circuit R0 or the like, which is a one-time cell, is arranged in the memory. In column 0 and column 2, the 1 × cell is adjacently connected to either the lower 1 × cell or the upper 1 × cell. Therefore, a vacant area 10 in which no standard cell is arranged is generated between the double cell and the single cell due to the difference in length in the channel width direction between the double cell and the single cell per single column, This empty area 10 can be used as a wiring area. The free area 10 is effectively used for connection between random circuits (R0 and the like), and a dead area generated by the free area 10 can be used.

FIG. 4 shows an example of an arrangement using a cell four times the size of the height (hereinafter referred to as a quadruple cell).
As in the case of using the double cell, the quadruple cell 11 is arranged at the left and right edge portions of the semiconductor device, and the quadruple cell 12 is formed by the quadruple cell.
Or one-time cell 13 is interposed. By arranging in this manner, a vacant area 14 is generated as in the semiconductor device of FIG. 3 due to the difference in length in the channel width direction. In such an empty area 14, standard cells are arranged as well as used as a wiring area. However, the wiring area is based on the basic cell height in the embodiment, but it is easy to narrow the wiring area by performing VDD and GND shift connections at the left and right ends in column units where cells are arranged. is there.

In the above-described embodiment, the double cell and the quadruple cell are arranged at the left and right edges of the semiconductor device. However, the present invention is not limited to this. The quadruple cells may be collected and arranged. Even with such an arrangement, the empty areas 10 and 14 can be formed, and can be used as a wiring area and an arrangement area of standard cells and basic cells.

As described above, in the layout of the standard cell type constituted by the double cell and the single cell which can be adjacent to the lower cell or the upper cell of the double cell, the space generated due to the arrangement of the standard cell is generated. By using the region as a wiring region, it is possible to reduce the area of the entire semiconductor device in the layout in the channel width direction.

Further, by employing a double cell, the size can be reduced by about 1/2 in the channel length direction, and the size in the channel length direction is limited by the latch circuit as shown in the above interface circuit example. In such a case, the channel length direction can be reduced by using a double cell for the FF circuit.

In the embodiment shown in FIG. 3, the area can be reduced by one unit in each of the X and Y directions as compared with the conventional example shown in FIG. In addition, one unit refers to the length in the channel width direction of the one-time cell. In addition, the double cell does not use the inside of the cell as a wiring region, so that a contact layer can be used, and a contact can be arranged in the source and drain regions of the transistor. Can be prevented. Further, FF circuits can be arranged in the same column by reducing the size in the channel length direction, and malfunction such as clock skew can be prevented.

[0018]

As described above in detail, according to the present invention, by laying out standard cells by mixing first and second basic cells, the channel between the first and second basic cells can be obtained. Since a vacant area is generated in the semiconductor device due to the difference in length in the width direction, the vacant area can be used as, for example, a wiring area, and a circuit layout can be effectively performed.

Further, by setting the extension multiple in the channel width direction to a natural number, the wiring in the X direction of the drain electrode and the ground electrode becomes straight, and the power supply wiring can be easily performed.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a basic cell used in a semiconductor device of the present invention, in which an inverter is configured.

FIG. 2 is a diagram illustrating a configuration of a basic cell used in the semiconductor device of the present invention, in which a flip-flop is configured;

FIG. 3 is a diagram showing a layout when a semiconductor device is configured by standard cells using the basic cells shown in FIGS. 1 and 2;

FIG. 4 is a diagram showing a layout of a basic cell used in the semiconductor device of the present invention, in which the semiconductor device is configured using a basic cell that is four times expanded in the channel width direction.

FIG. 5 is a diagram showing a configuration in a case where a conventional basic cell is used to configure an inverter and a buffer.

FIG. 6 is a diagram illustrating a case where a wiring region protrudes from a transistor region in a conventional basic cell.

FIG. 7 is a diagram showing a layout in a semiconductor device using the basic cell shown in FIG. 6;

FIG. 8 is a circuit diagram showing a configuration of an interface circuit.

9 is a circuit diagram showing a configuration of the FF circuit shown in FIG.

FIG. 10 is a circuit diagram showing a layout configuration of an interface circuit.

[Explanation of symbols]

10: empty area, 11: quadruple cell, 12: double cell, 1
3: 1 time cell, 14: Empty area.

Claims (6)

(57) [Claims] 1. A semiconductor device having a standard cell including a basic cell in which an N-channel transistor and a P-channel transistor are arranged in a channel width direction between a drain electrode region and a ground electrode region, wherein the semiconductor device has a size in the channel width direction. And a first basic cell in which the layout of the N and P channel transistors is extended in the channel length direction without changing, and the basic cell in which the size in the channel width direction is constant is set with the drain electrode region or the ground electrode region as a target portion. A semiconductor device having a standard cell, comprising: a second basic cell expanded by a natural number times in the channel width direction. 2. A standard cell comprising the first basic cell and the second basic cell is arranged in a column direction,
In addition, in the semiconductor device having a plurality of second basic cells having different values of the natural number multiple in the second basic cell, the standard cell having the second basic cell having a larger natural number multiple in the same column 2. The standard cell according to claim 1, wherein the standard cell having the second basic cell having a large natural number value is sandwiched between the standard cells, or the standard cell having the second basic cell having a large natural number value is arranged on one side. A semiconductor device having: 3. A standard cell comprising the first basic cell and the second basic cell is arranged in a column direction,
In the semiconductor device having a plurality of second basic cells having different values of the natural number multiple in the second basic cell, a standard cell having a second basic cell having a smaller natural multiple in the same column 2. The standard according to claim 1, wherein a standard cell having a second basic cell having a large natural number value is sandwiched between the standard cells, or a standard cell having a second basic cell having a small natural number value is arranged on one side. A semiconductor device having a cell. 4. A standard cell having a basic cell having a large natural number multiple and a standard cell having a basic cell having a small natural multiple are arranged in the same column as described in claim 2 or 3. 4. The semiconductor device having a standard cell according to claim 2, wherein the space generated due to the difference of the natural multiple is a wiring region of the standard cell. 5. The semiconductor device having a standard cell according to claim 4, wherein said space is further an area where standard cells are arranged. 6. The standard cell arrangement region, wherein the space is replaced with a standard cell wiring region.
A semiconductor device having the standard cell as described above.