JPH07249747A - Semiconductor device having standard cell - Google Patents

Abstract

PURPOSE:To lay out a circuit effectively by laying out a standard cell while mixing first and second basic cells thereby producing an idle region in the semiconductor device caused by the difference of length in the direction of channel width between the first and second basic cells. CONSTITUTION:In the placement of standard cell, double cells, e.g. buffers BO-B7 and FF circuits FFO, are distributed to the right and left end parts of the entire semiconductor device. Single cells, e.g. random circuits RO, are disposed at the parts sandwiched by the double cells. In rows 0 and 2, the single cells are connected contiguously at any one of upper or lower single cell. Consequently, an idle region 10 where no standard cell is disposed between single and double cells can be produced due to the difference of length in the direction of channel width between the single and double cells for each row. The idle region 10 can be used as a wiring region.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a master slice standard cell, and more particularly to a structure of a basic cell constituting the standard cell and a semiconductor device having the basic cell arranged and wired.

[0002]

2. Description of the Related Art Generally, a basic cell, which constitutes a standard cell, has a structure shown in FIG. 5A, a drain electrode (hereinafter referred to as VDD), and a ground electrode (hereinafter referred to as GND). The length in the Y direction is unified, and the layout configuration extends in the X direction according to the circuit configuration of the cell. Note that the Y direction means a channel width (also referred to as a transistor width) direction of a transistor included in a basic cell, in other words, a height direction, and the X direction means a channel length direction. For example, when the transistor width W is doubled in the inverter, as shown in FIG.
The layout is such that cells are extended in the same direction and transistors are divided. Further, although there are some conventional ones in which the power supply line is extended in the Y direction to form cells having different heights in the Y direction, a dead region is generated in the wiring area and the power supply is connected in the X direction connection of the cells. Causes a problem that the cells are bent and the cell arrangement area is lost. Further, FIG. 5D shows a legend of the diagrams shown in FIGS. 5 and 6.

Further, when the inverter becomes a buffer,
As shown in FIG. 5C, the cell is further extended in the X direction. Here, in the case of FIG. 5B, V of the basic cell is
Assuming that the wiring use layer is a metal 1, a metal 2, and a via connecting the metal 1 and the metal 2 when a portion other than the portions of DD and GND is considered as a wiring region, as shown in FIG. That is, the transistor region can be protruded in the Y direction, but when the wiring region between cells is narrower than the protrusion region 100, the basic cell interval is protruded region 10 as shown in the wiring region A in FIG.
There is a drawback, which is determined by the placement constraint of zero. Further, since the protruding area cannot be used because the metal 1 and the contact layer are wiring areas, the protruding area can be extended only by expanding the transistor width W (field, poly), and the source and drain areas of the transistor can be contacted. Therefore, when the transistor width is large, the transistor characteristics may vary depending on the contact arrangement with respect to the field width as shown in FIG.

In the layout of a processor, for example,
An interface circuit which is provided between an instruction control unit having a microcode ROM, PLA and the like and a data bus unit, and which is a circuit for latching an instruction control signal and generating a control signal for the data bus unit through a random circuit (decoder or the like). In the case of using the standard cell layout in the above layout, the interface circuit includes an instruction control signal latch circuit 101 and a random circuit 10 as shown in FIG.
2, the data bus section drive buffer section 103 is classified into the following circuit configuration. The latch circuit unit 101 is composed of a flip-flop circuit (hereinafter referred to as FF) 104 or a latch, and a clock is supplied from outside the interface circuit. In order to avoid malfunction due to clock-to-clock skew, the latch circuit unit 101 is arranged at equal positions as close to the microcode ROM and PLA as possible, for example, arranged in the same column (row: ROW), or the clock supply line is set to 2 Placement in two rows is preferred.

The random circuit section 102 includes a latch circuit section 1
This is an area in which the wiring load becomes high due to the output of 01, decoding, etc., and decoding and pitch matching to the data bus. The drive buffer unit 103 needs a buffer having a large transistor width in order to drive the data bus unit, and when a conventional basic cell is used, the above-described cell extended in the X direction or the protruding cell is used. Is used. Further, when considering signal propagation, it is desirable that the buffer is arranged on the data bus side as much as possible.

When the interface circuit is laid out by the standard cell method, the layout density may be lowered depending on the circuit scale of the latch circuit section 101, the random circuit section 102, and the buffer circuit section 103. For example, as shown in FIG. 10, when the latch circuit unit 101 is larger in number than the other random circuit unit 102 and the buffer circuit unit 103, the size in the X direction is limited by the latch circuit unit 101. Furthermore, when the buffer circuit unit 103 is small,
Since the wiring load of the buffer circuit section 103 is small, the wiring area is wasted due to the above-mentioned protrusion, and the wiring area section due to the above-mentioned protrusion cannot be contacted, which may result in insufficient performance as a buffer of the data bus section. . In FIG. 10, “B” is a buffer circuit,
“R” indicates a random circuit, “FF” indicates a latch circuit, wiring in the X direction is metal 1, wiring in the Y direction is metal 2, black circles are output terminal positions, and thick lines indicate VDD and GND. The present invention has been made to solve such a problem, and an object thereof is to provide a semiconductor device having a standard cell effective for a circuit layout.

[0007]

The present invention relates to a semiconductor device having a standard cell including a basic cell in which an N-channel transistor and a P-channel transistor are arranged in a channel width direction between a drain electrode region and a ground electrode region. The drain electrode region includes the first basic cell in which the layout of the N and P channel transistors is extended in the channel length direction without changing the size in the channel width direction and the basic cell in which the size in the channel width direction is constant. Alternatively, it is characterized in that it is provided with a second basic cell in which the ground electrode region is expanded as a natural number times in the channel width direction.

[0008]

With this structure, when the standard cell is laid out by mixing the first basic cell and the second basic cell, the difference in the length in the channel width direction between the first basic cell and the second basic cell Due to this, an empty area is generated in the semiconductor device. This empty area can be used, for example, as a wiring area. In this way, the first basic cell and the second basic cell act to effectively perform the circuit layout. In the embodiment, the first basic cell corresponds to a 1 × cell and the second basic cell corresponds to a cell having a multiple of 2 or more.

[0009]

FIG. 1 shows the basic cell structure of an embodiment of a semiconductor device having a standard cell of the present invention. The basic cell shown in FIG. 1 has a layout configuration having a doubled height in the channel width direction, which is obtained by folding back the conventional basic cell shown in FIG. In addition, hereinafter, such a basic cell having a doubled height in the channel width direction is referred to as a "doubled cell", and the basic cell shown in FIG. In FIG. 1, a portion indicated by reference numeral “1” is a 1 × cell, and a portion indicated by reference numeral “2” is a 2 × cell. In addition, in a double-height cell, each VDD, GN
D has the same position and the same width in the channel width direction as the 1x cell, and can be adjacently connected to either the basic cell located below the double cell shown in FIG. 1 or the basic cell located above it. And

In the example of the inverter and the FF circuit having the large transistor width, for example, the FF shown in FIG.
It is a basic cell having a height twice as high as usual in the channel width direction like a circuit. Further, in the double cell, all layout layers can be arranged in the same manner as in the normal single cell, and there is no restriction as a wiring area. Therefore, the degree of freedom in arranging the contacts in the contact arrangement of the source and drain regions of the transistor portion is higher than that in the case of the conventional cell in which the contact is protruded into the wiring region. Further, it is possible to arrange the circuit area including the wiring other than the protruding portion such as the slave portion of the FF circuit. In addition, the double cell has a height twice as high as that of the normal single cell, so that the size can be reduced by about 1/2 in the channel length direction.

Further, in this embodiment, the basic cell has an example in which it is twice as high in the channel width direction. However, as in the CONT5 signal section shown in the interface circuit example of FIG.
When the F circuits are connected in two stages, the height can be increased to four times. That is, the number N of steps in the channel width direction is a natural number.

FIG. 3 shows an equivalent layout and wiring example when the basic cell of this embodiment is used for the conventional interface circuit shown in FIG. In the standard cell arrangement, for example, double cells such as the buffer B0 to the buffer B7 and the FF circuit FF0 are dispersedly arranged on the left and right edge portions of the entire semiconductor device, and the portion sandwiched between these double cells is arranged. A random circuit R0 or the like, which is a 1-time cell, is arranged in. In column 0 and column 2, the 1 × cell is connected adjacent to either the 1 × cell below the 2 × cell or the 1 × cell above. Therefore, due to the difference in length in the channel width direction between the double cell and the single cell per single column, an empty area 10 in which the standard cell is not arranged is generated between the double cell and the single cell. This empty area 10 can be used as a wiring area. The empty area 10 is effectively used for connection between random circuits (R0, etc.), and the dead area generated by the empty area 10 can be used.

Further, FIG. 4 shows an arrangement example using a cell having a size four times as high (hereinafter referred to as a cell four times).
As in the case of using the doubling cell, the quadruple cell 11 is arranged at the left and right edge portions of the semiconductor device, and the quadruple cell is the doubling cell
The cells are arranged so as to sandwich the 1 × cell 13. By arranging in this way, the empty area 14 is generated as in the semiconductor device of FIG. 3 due to the difference in length in the channel width direction. For such an empty area 14, not only is it used as a wiring area, but also standard cells are arranged. Although the wiring area is based on the basic cell height in the embodiment, the wiring area can be easily narrowed by performing VDD and GND shift connections at the left and right ends in column units in which cells are arranged. is there.

Although the double cells and the quadruple cells are arranged at the left and right edges of the semiconductor device in the above-mentioned embodiment, the present invention is not limited to this, and the double cells and the quadruple cells are provided at either one of the left and right edges. You may collect and arrange a 4 times cell. Even with such an arrangement, the empty areas 10 and 14 can be formed and can be used as an area for arranging wiring areas, standard cells and basic cells.

In the standard cell type layout composed of the double cell and the single cell which can be adjacent to the cell below or above the double cell as described above, an empty space caused by the arrangement of the standard cells. By using the region as the wiring region, it is possible to reduce the area of the entire semiconductor device in the layout in the channel width direction.

Further, by adopting the double cell, it is possible to reduce the size by about 1/2 in the channel length direction, and the size in the channel length direction is limited by the latch circuit as shown in the above-mentioned interface circuit example. In such a case, the channel length direction can be reduced by doubling the FF circuit.

In the embodiment shown in FIG. 3, the area can be reduced by one unit in each of the X and Y directions as compared with the conventional example shown in FIG. In addition, 1 unit means the length in the channel width direction in the 1 × cell. Further, since the doubled cell does not use the inside of the cell as a wiring region, a contact layer can be used, and contacts can be arranged in the source and drain regions of the transistor, resulting in deterioration of the transistor performance as compared with the protrusion of the transistor described above. Can be prevented. Further, by reducing the size in the channel length direction, the FF circuits can be arranged in the same column, and malfunctions such as clock skew can be prevented.

[0018]

As described in detail above, according to the present invention, by laying out the standard cells by mixing the first basic cells and the second basic cells, the channels of the first basic cells and the second basic cells are laid out. Since a vacant region is generated in the semiconductor device due to the difference in length in the width direction, this vacant region can be used as, for example, a wiring region and the circuit layout can be effectively performed.

Further, by setting the extension multiple in the channel width direction to be a natural number, the wiring of the drain electrode and the ground electrode in the X direction becomes a straight line, and the power supply wiring can be easily performed.

[Brief description of drawings]

FIG. 1 is a diagram showing a configuration of a basic cell used in a semiconductor device of the present invention, in which an inverter is configured.

FIG. 2 is a diagram showing a configuration of a basic cell used in the semiconductor device of the present invention, in which a flip-flop is configured.

FIG. 3 is a diagram showing a layout in the case where a semiconductor device is configured by standard cells using the basic cells shown in FIGS. 1 and 2.

FIG. 4 is a diagram showing a layout of a basic cell used in the semiconductor device of the present invention, in which the semiconductor device is formed by using a basic cell which is expanded four times in the channel width direction.

FIG. 5 is a diagram showing a configuration when an inverter and a buffer are configured using a conventional basic cell.

FIG. 6 is a diagram showing a case where a wiring region extends beyond a transistor region in a conventional basic cell.

FIG. 7 is a diagram showing a layout in a semiconductor device using the basic cell shown in FIG.

FIG. 8 is a circuit diagram showing a configuration of an interface circuit.

9 is a circuit diagram showing a configuration of the FF circuit shown in FIG.

FIG. 10 is a circuit diagram showing a layout configuration of an interface circuit.

[Explanation of symbols]

10 ... Empty area, 11 ... 4 times cell, 12 ... 2 times cell, 1
3 ... 1 time cell, 14 ... Empty area.

Claims (6)

[Claims] 1. A semiconductor device having a standard cell including an elementary cell in which an N-channel transistor and a P-channel transistor are arranged in a channel width direction between a drain electrode region and a ground electrode region, wherein the size in the channel width direction is set. With the first basic cell in which the layout of the N and P channel transistors is extended in the channel length direction without changing, and the basic cell having the constant size in the channel width direction with the drain electrode region or the ground electrode region as a target site. A semiconductor device having a standard cell, comprising: a second basic cell which is naturally expanded by a natural number in the channel width direction. 2. A standard cell composed of the first basic cell and the second basic cell is arranged in a column direction,
Further, in the second basic cell, in the semiconductor device having a plurality of second basic cells having different natural multiples, a standard cell having a second basic cell having a large natural multiple is provided in the same column. 2. The standard cell according to claim 1, wherein the standard cell having the second basic cell having the small natural number multiple value is sandwiched, or the standard cell having the second basic cell having the large natural number multiple value is arranged close to one side. A semiconductor device having. 3. A standard cell composed of the first basic cell and the second basic cell is arranged in a column direction,
In the second basic cell, a semiconductor device having a plurality of the second basic cells having different natural multiples, the standard cell having a second basic cell having a small natural multiple in the same column. 2. The standard according to claim 1, wherein a standard cell having a second basic cell having a large natural number multiple is sandwiched between two standard cells, or a standard cell having a second basic cell having a small natural multiple is arranged on one side. A semiconductor device having a cell. 4. A standard cell having a basic cell with a large natural number multiple value and a standard cell having a basic cell with a small natural number multiple value are arranged in the same column as described in claim 2 or 3. In this case, the semiconductor device having the standard cell according to claim 2 or 3, wherein the space caused by the difference in the natural number multiples is the wiring region of the standard cell. 5. The semiconductor device having a standard cell according to claim 4, wherein the space is a standard cell disposition region. 6. The standard cell wiring region is used as the space instead of the standard cell wiring region.
A semiconductor device having the described standard cell.