JPH06232328A - Loc semiconductor device - Google Patents
Loc semiconductor deviceInfo
- Publication number
- JPH06232328A JPH06232328A JP50A JP1556993A JPH06232328A JP H06232328 A JPH06232328 A JP H06232328A JP 50 A JP50 A JP 50A JP 1556993 A JP1556993 A JP 1556993A JP H06232328 A JPH06232328 A JP H06232328A
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- signal
- pads
- lead wiring
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0555—Shape
- H01L2224/05552—Shape in top view
- H01L2224/05554—Shape in top view being square
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
Abstract
Description
【０００１】[0001]
【産業上の利用分野】この発明は、半導体チップの表面
に、電源用リード配線フレーム、信号用リード配線フレ
ーム、電源用リード配線フレームを接続するための電源
パッドおよび信号用リード配線フレームを接続するため
の信号パッドをそれぞれ配置したＬＯＣ（リード オン
チップ）型半導体装置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention connects a power supply lead wiring frame, a signal lead wiring frame, a power supply pad for connecting a power supply lead wiring frame and a signal lead wiring frame to the surface of a semiconductor chip. The present invention relates to a LOC (lead-on-chip) type semiconductor device in which signal pads are arranged respectively.
【０００２】[0002]
【従来の技術】図２は従来のＬＯＣ型半導体装置の一例
を示し、図において、符号１は半導体チップ、２は第１
電源用リード配線フレーム、３は第２電源用リード配線
フレーム、４は信号用リード配線フレーム、５ａ，５ｂ
は第１電源用リード配線用フレーム２、第２電源用リー
ド配線フレーム３をそれぞれ接続するための電源パッ
ド、そして、符号６は信号用リード配線フレーム４を接
続するための信号パッドである。2. Description of the Related Art FIG. 2 shows an example of a conventional LOC type semiconductor device. In the figure, reference numeral 1 is a semiconductor chip and 2 is a first.
Power supply lead wiring frame, 3 is a second power supply lead wiring frame, 4 is a signal lead wiring frame, 5a, 5b
Is a power supply pad for connecting the first power supply lead wiring frame 2 and the second power supply lead wiring frame 3, respectively, and reference numeral 6 is a signal pad for connecting the signal lead wiring frame 4.
【０００３】第１電源用リード配線フレーム２、第２電
源用リード配線フレーム３及び信号用リード配線フレー
ム４は、半導体チップ１の表面に配置され、また電源パ
ッド５ａ，５ｂ及び信号パッド６は半導体チップ１のほ
ぼ中央部に一列に設置されている。そして、この電源パ
ット５ａと５ｂに第１電源用リード配線フレーム２と第
２電源用リード配線フレーム３とがそれぞれ接続され、
また信号パッド６に信号用リード配線フレーム４が接続
されている。The first power supply lead wiring frame 2, the second power supply lead wiring frame 3 and the signal lead wiring frame 4 are arranged on the surface of the semiconductor chip 1, and the power supply pads 5a and 5b and the signal pad 6 are semiconductors. The chips 1 are arranged in a line at approximately the center. Then, the first power supply lead wiring frame 2 and the second power supply lead wiring frame 3 are connected to the power supply pads 5a and 5b, respectively.
The signal lead wiring frame 4 is connected to the signal pad 6.
【０００４】[0004]
【発明が解決しようとする課題】従来のＬＯＣ型半導体
装置は以上のように構成されているので、半導体チップ
の内部における電源パット５ａ，５ｂから半導体チップ
に組み込まれた回路素子（図省略）までの電源配線が長
くなり、このため電源抵抗が大きくなる等の課題があっ
た。Since the conventional LOC type semiconductor device is configured as described above, from the power supply pads 5a and 5b inside the semiconductor chip to the circuit elements (not shown) incorporated in the semiconductor chip. However, there is a problem in that the power supply wiring becomes long, which increases the power supply resistance.
【０００５】また、半導体チップ内部における信号パッ
ト６から回路素子までの信号配線も長くなり、このた
め、信号入力の入力容量が大きくなり、半導体装置が作
動しにくくなる等の課題があった。Further, the signal wiring from the signal pad 6 to the circuit element inside the semiconductor chip is also lengthened, which increases the input capacitance of the signal input, making it difficult to operate the semiconductor device.
【０００６】この発明は以上の課題を解決するためにな
されたもので、半導体チップの内部における電源抵抗の
低減及び信号入力の入力容量の低減を可能にしたＬＯＣ
型半導体装置を提供することを目的とする。The present invention has been made to solve the above problems, and it is possible to reduce the power supply resistance inside the semiconductor chip and the input capacitance of the signal input.
An object of the present invention is to provide a semiconductor device.
【０００７】[0007]
【課題を解決するための手段】この発明に係るＬＯＣ型
半導体装置は、半導体チップの表面に、電源用リード配
線フレーム及び信号用リード配線フレームをそれぞれ接
続するための電源パッドと信号パッドとを複数列に配置
し、この複数列に配置された電源パッド及び信号パッド
の間に前記電源用リード配線フレームを設置し、かつ前
記電源パッド及び信号パッドの外側に前記信号用リード
配線フレームを配置したものである。In a LOC type semiconductor device according to the present invention, a plurality of power supply pads and signal pads for respectively connecting a power supply lead wiring frame and a signal lead wiring frame are provided on the surface of a semiconductor chip. The power supply lead wiring frame is arranged between the power supply pads and the signal pads arranged in a plurality of rows, and the signal lead wiring frame is arranged outside the power supply pads and the signal pads. Is.
【０００８】[0008]
【作用】この発明に係るＬＯＣ型半導体装置において
は、電源パッド及び信号パッドが半導体チップの表面に
複数列に設置され、この複数列に設置された電源パッド
及び信号パッドの間に電源用リード配線フレームが設置
されていることにより、半導体チップ内部における電源
パッドから半導体チップの中に組み込まれた回路素子ま
での電源用配線が短くなり、これにより半導体チップ内
部の電源抵抗の低減が図れる。また、半導体チップの内
部における信号用配線も短くなり、これにより信号入力
の入力容量の低減が図れる。In the LOC type semiconductor device according to the present invention, the power supply pads and the signal pads are arranged in a plurality of rows on the surface of the semiconductor chip, and the power supply lead wiring is provided between the power supply pads and the signal pads arranged in the plurality of rows. The installation of the frame shortens the power supply wiring from the power supply pad inside the semiconductor chip to the circuit element incorporated in the semiconductor chip, thereby reducing the power supply resistance inside the semiconductor chip. Further, the signal wiring inside the semiconductor chip is also shortened, so that the input capacitance of the signal input can be reduced.
【０００９】[0009]
【実施例】図１はこの発明に係るＬＯＣ型半導体装置の
一実施例を示し、図において、符号１は半導体チップ、
２は第１電源用リード配線フレーム、３は第２電源用リ
ード配線フレーム、４は信号用リード配線フレーム、５
ａと５ｂは第１電源用リード配線用フレーム２と第２電
源用リード配線フレーム３をそれぞれ接続するための電
源パッド、そして符号６は信号用リード配線フレーム４
を接続するための信号パッドである。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 shows an embodiment of the LOC semiconductor device according to the present invention.
Reference numeral 2 is a first power supply lead wiring frame, 3 is a second power supply lead wiring frame, 4 is a signal lead wiring frame, 5
a and 5b are power supply pads for connecting the first power supply lead wiring frame 2 and the second power supply lead wiring frame 3, respectively, and reference numeral 6 is a signal lead wiring frame 4
Is a signal pad for connecting to.
【００１０】電源パッド５ａ，５ｂ及び信号パッド６
は、半導体チップ１の表面に２列に配置されている。ま
た、第１電源用リード配線フレーム２及び第２電源用リ
ード配線フレーム３は、２列に設けられた電源パッド５
ａ，５ｂ及び信号パッド６の間に、これらの電源パッド
５ａ，５ｂ及び信号パッド６に沿って設置され、かつ、
任意の部分で電源パット５ａ及び５ｂとワイヤー７によ
って電気的に接続されている。Power supply pads 5a, 5b and signal pad 6
Are arranged in two rows on the surface of the semiconductor chip 1. The first power supply lead wiring frame 2 and the second power supply lead wiring frame 3 are provided with power supply pads 5 arranged in two rows.
a, 5b and the signal pad 6 are installed along the power supply pads 5a, 5b and the signal pad 6, and
The power pads 5a and 5b are electrically connected by wires 7 at arbitrary portions.
【００１１】また、信号用リード配線フレーム４は、２
列に設けられた電極パッド５ａ，５ｂ及び信号パッド６
の外側に配置され、それぞれ信号パット６とワイヤー８
によって接続されている。Further, the signal lead wiring frame 4 has two
Electrode pads 5a, 5b and signal pads 6 provided in the row
Placed on the outside of the signal pad 6 and wire 8 respectively
Connected by.
【００１２】上記のＬＯＣ型半導体装置においては、電
源パッド５ａ、５ｂ及び信号パッド６が半導体チップ１
の表面に２列に設置され、この列の間に電源用リード配
線フレーム２，３が配置されているので、半導体チップ
１内部における電源パッド５ａ、５ｂから半導体チップ
１内部に組み込まれた回路素子までの電源配線を短くす
ることができる。In the LOC type semiconductor device described above, the power supply pads 5a and 5b and the signal pad 6 are the semiconductor chip 1.
Since the power supply lead wiring frames 2 and 3 are arranged in two rows on the surface of the semiconductor chip, the circuit elements incorporated in the semiconductor chip 1 from the power supply pads 5a and 5b in the semiconductor chip 1 are arranged. The power wiring up to can be shortened.
【００１３】また、電源パッド５ａ，５ｂと電源用リー
ド配線フレーム２，３とを電源用リード配線フレーム
２，３の任意の部分でワイヤー７を介して接続すること
ができる。Further, the power supply pads 5a and 5b and the power supply lead wiring frames 2 and 3 can be connected to each other through a wire 7 at any portion of the power supply lead wiring frames 2 and 3.
【００１４】さらに、半導体チップ１内部における信号
パッド６から回路素子までの信号用配線も短くすること
ができる。Further, the signal wiring from the signal pad 6 to the circuit element inside the semiconductor chip 1 can be shortened.
【００１５】なお、上記実施例では電源パッド５ａ，５
ｂおよび信号パッド６により形成された列は２列であっ
たが、３列以上であってもよいのは勿論である。In the above embodiment, the power supply pads 5a, 5a
The number of columns formed by b and the signal pads 6 is two, but it is needless to say that the number of columns may be three or more.
【００１６】[0016]
【発明の効果】以上説明したように、この発明に係るＬ
ＯＣ型半導体装置によれば、電源パッド及び信号パッド
が半導体チップの表面に複数列に配置され、この複数列
に配置された電源パッド及び信号パッドの間に電源用リ
ード配線フレームが設置されているので、半導体チップ
内部における電源パッドから半導体チップ内部に組み込
まれた回路素子までの電源配線を短くすることができ、
これにより半導体チップ内部の電源抵抗の低減が可能と
なる効果がある。また、電源パッドと電源用リード配線
フレームとを電源用リード配線フレームの任意の部分で
接続することができる効果がある。さらに、半導体チッ
プ内部における信号パッドから回路素子までの信号用配
線も短くすることができ、これにより信号入力の入力容
量を低減することができ、半導体装置の作動の低下を防
止することができる効果がある。As described above, the L according to the present invention is
According to the OC type semiconductor device, the power supply pads and the signal pads are arranged in a plurality of rows on the surface of the semiconductor chip, and the power supply lead wiring frame is installed between the power supply pads and the signal pads arranged in the plurality of rows. Therefore, the power supply wiring from the power supply pad in the semiconductor chip to the circuit element incorporated in the semiconductor chip can be shortened,
This has an effect that the power supply resistance inside the semiconductor chip can be reduced. In addition, there is an effect that the power supply pad and the power supply lead wiring frame can be connected at any portion of the power supply lead wiring frame. Further, it is possible to shorten the signal wiring from the signal pad to the circuit element inside the semiconductor chip, which can reduce the input capacitance of the signal input and prevent the operation of the semiconductor device from being lowered. There is.
【図１】この発明に係るＬＯＣ型半導体装置の一実施例
の平面図である。FIG. 1 is a plan view of an embodiment of an LOC semiconductor device according to the present invention.
【図２】従来のＬＯＣ型半導体装置の一例を示す平面図
である。FIG. 2 is a plan view showing an example of a conventional LOC semiconductor device.
１ 半導体チップ ２ 第１電源用リード配線フレーム ３ 第２電源用リード配線フレーム ４ 信号用リード配線フレーム ５ａ 電源パッド ５ｂ 電源パッド ６ 信号パッド 1 semiconductor chip 2 first power supply lead wiring frame 3 second power supply lead wiring frame 4 signal lead wiring frame 5a power supply pad 5b power supply pad 6 signal pad
【手続補正書】[Procedure amendment]
【提出日】平成５年１０月１３日[Submission date] October 13, 1993
【手続補正１】[Procedure Amendment 1]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】請求項１[Name of item to be corrected] Claim 1
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【手続補正２】[Procedure Amendment 2]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００４[Correction target item name] 0004
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００４】[0004]
【発明が解決しようとする課題】従来のＬＯＣ型半導体
装置は以上のように構成されているので、半導体チップ
の内部における電源パット５ａ，５ｂから半導体チップ
内に組み込まれた回路素子（図省略）までの電源配線が
半導体内の配線材料で施され、このため電源抵抗が大き
くなる等の課題があった。Since the conventional LOC type semiconductor device is configured as described above, the power supply pads 5a and 5b inside the semiconductor chip can be removed from the semiconductor chip.
Power wiring to the integrated circuit elements (FIG omitted) within the
Since the wiring material is used in the semiconductor, there is a problem that the power supply resistance increases.
【手続補正３】[Procedure 3]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００５[Name of item to be corrected] 0005
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００５】また、半導体チップ内部における信号パッ
ト６に接続される信号用リードフレーム４も長くなり、
このため、信号入力の入力容量が大きくなり、半導体装
置が作動しにくくなる等の課題があった。Further, the signal lead frame 4 connected to the signal pad 6 inside the semiconductor chip also becomes longer,
Therefore, there is a problem that the input capacitance of the signal input becomes large and the semiconductor device becomes difficult to operate.
【手続補正４】[Procedure amendment 4]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００６[Correction target item name] 0006
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００６】この発明は以上の課題を解決するためにな
されたもので、半導体チップの電源抵抗の低減及び信号
入力の入力容量の低減を可能にしたＬＯＣ型半導体装置
を提供することを目的とする。[0006] and aims this invention to provide an above problems has been made to solve the, LOC type semiconductor device that enables a reduction in the input capacitance of the reduction and the signal input of the power resistance of the semiconductor chip To do.
【手続補正５】[Procedure Amendment 5]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００７[Correction target item name] 0007
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００７】[0007]
【課題を解決するための手段】この発明に係るＬＯＣ型
半導体装置は、半導体チップの表面に、電源用リード配
線フレーム及び信号用リード配線フレームをそれぞれ接
続するための電源パッドと信号パッドとを複数列に配置
し、この複数列に配置された電源パッド及び信号パッド
の間に前記電源用リード配線フレームを設置し、これを
用いて前記複数列に配置された電源パッドに接続し、か
つ前記電源パッド及び信号パッドの外側に前記信号用リ
ード配線フレームを配置したものである。In a LOC type semiconductor device according to the present invention, a plurality of power supply pads and signal pads for respectively connecting a power supply lead wiring frame and a signal lead wiring frame are provided on the surface of a semiconductor chip. place the column, placing the power lead wire frame between the power pads and signal pads arranged in the plurality of rows, this
It is used to connect to the power supply pads arranged in the plurality of columns, and the signal lead wiring frame is arranged outside the power supply pads and the signal pads.
【手続補正６】[Procedure correction 6]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】０００８[Correction target item name] 0008
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【０００８】[0008]
【作用】この発明に係るＬＯＣ型半導体装置において
は、電源パッド及び信号パッドが半導体チップに複数列
に設置され、この複数列に設置された電源パッド及び信
号パッドの間に電源用リード配線フレームが設置されて
いることにより、半導体チップ内部における電源パッド
から半導体チップの中に組み込まれた回路素子までの電
源用配線が短くなり、これにより半導体チップ内部の電
源抵抗の低減が図れる。また、半導体チップのパッドか
ら外部への信号用配線フレームも短くなり、これにより
信号入力の入力容量の低減が図れる。[Action] In LOC type semiconductor device according to the present invention, power pads and signal pads are disposed in a plurality of rows in a semiconductor chip, power lead wire frame between the power pads and signal pads installed in the plurality of rows By installing the power supply wiring, the power supply wiring from the power supply pad inside the semiconductor chip to the circuit element incorporated in the semiconductor chip is shortened, whereby the power supply resistance inside the semiconductor chip can be reduced. Also, the pad of the semiconductor chip
Also, the signal wiring frame to the outside is shortened, whereby the input capacitance of the signal input can be reduced.
【手続補正７】[Procedure Amendment 7]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１４[Correction target item name] 0014
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１４】さらに、半導体チップ１の信号パッド６か
ら外部への信号用配線フレームも短くすることができ
る。Further, the signal wiring frame from the signal pad 6 of the semiconductor chip 1 to the outside can be shortened.
【手続補正８】[Procedure Amendment 8]
【補正対象書類名】明細書[Document name to be amended] Statement
【補正対象項目名】００１６[Correction target item name] 0016
【補正方法】変更[Correction method] Change
【補正内容】[Correction content]
【００１６】[0016]
【発明の効果】以上説明したように、この発明に係るＬ
ＯＣ型半導体装置によれば、電源パッド及び信号パッド
が半導体チップの表面に複数列に配置され、この複数列
に配置された電源パッド及び信号パッドの間に電源用リ
ード配線フレームが設置されているので、半導体チップ
内部における電源パッドから半導体チップ内部に組み込
まれた回路素子までの電源配線を短くすることができ、
これにより半導体チップ内部の電源抵抗の低減が可能と
なる効果がある。また、電源パッドと電源用リード配線
フレームとを電源用リード配線フレームの任意の部分で
接続することができる効果がある。さらに、半導体チッ
プの信号パッドから外部への信号用配線も短くすること
ができ、これにより信号入力の入力容量を低減すること
ができ、半導体装置の作動の低下を防止することができ
る効果がある。As described above, the L according to the present invention is
According to the OC type semiconductor device, the power supply pads and the signal pads are arranged in a plurality of rows on the surface of the semiconductor chip, and the power supply lead wiring frame is installed between the power supply pads and the signal pads arranged in the plurality of rows. Therefore, the power supply wiring from the power supply pad in the semiconductor chip to the circuit element incorporated in the semiconductor chip can be shortened,
This has an effect that the power supply resistance inside the semiconductor chip can be reduced. In addition, there is an effect that the power supply pad and the power supply lead wiring frame can be connected at any portion of the power supply lead wiring frame. Further, it is possible to shorten the signal wiring from the signal pad of the semiconductor chip to the outside , thereby reducing the input capacitance of the signal input and preventing the deterioration of the operation of the semiconductor device. .
Claims (1)
線フレーム、信号用リード配線フレーム、電源用リード
配線フレームを接続するための電源パッドおよび信号用
リード配線フレームを接続するための信号パッドをそれ
ぞれ配置したＬＯＣ型半導体装置において、前記電源パ
ッド、前記信号パッドを複数列に配置するとともに、こ
の複数列に配置された電源パッド、信号パッドの間に前
記電源用リード配線フレームを配置し、また前記電源パ
ッド、前記信号パッドの外側に前記信号用リード配線フ
レームを配置したことを特徴とするＬＯＣ型半導体装
置。1. A power supply lead wiring frame, a signal lead wiring frame, a power supply pad for connecting the power supply lead wiring frame, and a signal pad for connecting the signal lead wiring frame to the surface of the semiconductor chip, respectively. In the arranged LOC semiconductor device, the power supply pads and the signal pads are arranged in a plurality of columns, and the power supply lead wiring frame is arranged between the power supply pads and the signal pads arranged in the plurality of columns, and A LOC type semiconductor device, wherein the signal lead wiring frame is arranged outside a power supply pad and the signal pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50A JPH06232328A (en) | 1993-02-02 | 1993-02-02 | Loc semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP50A JPH06232328A (en) | 1993-02-02 | 1993-02-02 | Loc semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH06232328A true JPH06232328A (en) | 1994-08-19 |
Family
ID=11892377
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP50A Pending JPH06232328A (en) | 1993-02-02 | 1993-02-02 | Loc semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH06232328A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0926734A2 (en) * | 1997-12-22 | 1999-06-30 | Texas Instruments Incorporated | Method and apparatus for delivering electrical power to a semiconducteur die |
| US6016003A (en) * | 1996-10-29 | 2000-01-18 | Nec Corporation | Chip-lead interconnection structure in a semiconductor device |
| KR100401536B1 (en) * | 1997-12-31 | 2004-01-24 | 주식회사 하이닉스반도체 | Method for altering center pad type semiconductor chip to peripheral pad type semiconductor chip |
| CN103928431A (en) * | 2012-10-31 | 2014-07-16 | 矽力杰半导体技术(杭州)有限公司 | Inversion packaging device |
-
1993
- 1993-02-02 JP JP50A patent/JPH06232328A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6016003A (en) * | 1996-10-29 | 2000-01-18 | Nec Corporation | Chip-lead interconnection structure in a semiconductor device |
| EP0926734A2 (en) * | 1997-12-22 | 1999-06-30 | Texas Instruments Incorporated | Method and apparatus for delivering electrical power to a semiconducteur die |
| EP0926734A3 (en) * | 1997-12-22 | 2002-04-03 | Texas Instruments Incorporated | Method and apparatus for delivering electrical power to a semiconducteur die |
| KR100401536B1 (en) * | 1997-12-31 | 2004-01-24 | 주식회사 하이닉스반도체 | Method for altering center pad type semiconductor chip to peripheral pad type semiconductor chip |
| CN103928431A (en) * | 2012-10-31 | 2014-07-16 | 矽力杰半导体技术(杭州)有限公司 | Inversion packaging device |
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