JPH0766330A - Mounting connector for semiconductor element - Google Patents

Abstract

PURPOSE:To make a semiconductor chip which can reduce heat stresses which act on the chip when the chip is mounted on a substrate, such as the printed board, etc., and a connector used for mounting the chip on the substrate programmable. CONSTITUTION:In a semiconductor element mounting connector 3 provided with electrodes 2 connected to a semiconductor chip 1 on one surface and electrodes 4 which are electrically connected to the electrodes, provided on the other surface of the connector 3, and connected to a substrate 5, the electrodes 4 connected to the substrate 5 are formed near the central part of the connector 3 in a concentrating state. In addition, the connector 3 is a programmable inter-connector.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a connector for mounting a semiconductor chip (semiconductor element) on a board such as a printed board.

It is necessary to mount semiconductor chips on a substrate and to connect the semiconductor chips to each other and to connect them to power supply terminals, external input / output signal terminals and the like.

[0003]

2. Description of the Related Art FIG. 9 shows a conventional mounting structure on a semiconductor chip and a substrate. (a) shows a semiconductor chip. (b) shows the mounting structure.

In the figure, 1 is a semiconductor chip. Two
Is an electrode for electrically connecting the semiconductor chip 1 and the substrate 5.

Reference numeral 5 denotes a substrate, such as a printed circuit board. Reference numeral 20 denotes a pad, which constitutes an electrode of the semiconductor chip 1. In the enlarged view of the electrode portion, 20 is a pad, which is an electrode of the semiconductor chip 1.

Reference numeral 21 denotes a bump, which is composed of solder or the like for electrically and mechanically coupling the pad 20 of the semiconductor chip 1 and the pad 22 of the substrate 5.

Reference numeral 22 denotes a pad, which constitutes an electrode of the substrate 5. The pads 20 of the semiconductor chip 1 are provided in the peripheral portion of the semiconductor chip 1 as shown in the figure. The semiconductor chip 1 is mounted on the substrate 5 by electrically connecting the pads 20 of the semiconductor chip 1 and the corresponding pads 22 of the substrate 5 with bumps 21 such as solder as shown in the figure, and mechanically fixing them. .

FIG. 10 is an explanatory diagram of stress acting on a conventional semiconductor chip. (a) shows the stress (thermal stress) generated when heat is applied to the semiconductor chip.

In the figure, 1 is a semiconductor chip, 2 is an electrode, and 5 is a substrate.

O is the center of the semiconductor chip. k1, k
Reference numerals 2 are horizontal and vertical centerlines of the semiconductor chip 1, respectively. A stress F1 is stress F1 and represents stress such as thermal strain near the center of the side of the semiconductor chip in the direction parallel to the center line k1.

Reference numeral 121 denotes a stress F2, which represents a stress such as thermal strain near the periphery of the side of the semiconductor chip in the direction parallel to the center line k1. 122 is the stress F3 acting on the electrode
That is, the stress caused by the difference in thermal expansion coefficient between the semiconductor chip 1 and the substrate 5 is represented.

Reference numeral 123 denotes a stress F4 acting on the electrode, which is a stress (hereinafter referred to as a thermal stress) caused by a difference in thermal expansion coefficient between the semiconductor chip 1 and the substrate 5. Figure 10
As shown in (a) of the above, the stress (thermal stress) applied to the semiconductor chip 1 increases at the periphery of the substrate and decreases at the center.

(B) shows the stress (thermal stress) acting in the vicinity of the electrodes in the conventional mounting structure of the semiconductor chip and the substrate.
The stress F3 (stress acting in the direction toward the center of the semiconductor chip 1) and the stress F4 (stress acting in the direction toward the outside of the semiconductor chip 1) caused by the difference in the coefficient of thermal expansion between the semiconductor chip 1 and the substrate 5 are respectively Since the stress acts on the peripheral portion of the semiconductor chip 1, it is larger than the stress acting on the vicinity of the center of the semiconductor chip 1.

FIG. 11 shows a conventional method of mounting a semiconductor chip and a programmable interconnector. In the figure,
Reference numeral 5 is a substrate, 10 is a programmable interconnector, and internal wiring can be set from the outside. For example, wiring is performed by cutting internal wiring elements 56 such as fuses arranged in a matrix. Alternatively, the internal connection is determined by setting an external signal (1 or 0) to the internal wiring element 56 such as SRAM provided inside.

Reference numeral 22 is a pad. 50 is a wiring.
Reference numerals 51, 52 and 53 are semiconductor chips.

Reference numeral 55 denotes internal wiring, which represents internal wiring of the programmable interconnector 10. Reference numeral 56 is an internal wiring element, which is, for example, a fuse or SRAM arranged in a matrix, and determines the connection of the internal wiring 55.

Conventionally, the semiconductor chips 51, 52 and 53 and the programmable interconnector 10 are arranged on the substrate 5, respectively, and the internal interconnect 55 is set in advance by the internal interconnect element 56. The semiconductor chips 51, 52 and 53 are connected to each other.

[0018]

Conventional semiconductor chip 1
The mounting structure (FIG. 9) on the substrate 5 is such that the electrodes 2 provided in the peripheral portion of the semiconductor chip 1 are directly fixed to the substrate 5 as shown in FIG. The materials were also different. Therefore, the thermal expansion coefficients of the semiconductor chip 1 and the substrate 5 are different, and the thermal stress in the vicinity of the electrode 2 caused by that is large.

Further, since the semiconductor chip and the programmable interconnector for connecting the semiconductor chips via the conventional programmable interconnector are mounted on the board respectively, the mounting area becomes large and the device It was hindering miniaturization.

It is an object of the present invention to provide a semiconductor chip mounting connector capable of mounting a semiconductor chip so that the thermal stress acting on the semiconductor chip becomes small. Another object is to provide a semiconductor element mounting connector in which a connector for connecting a semiconductor chip to a substrate is programmable.

[0021]

According to the present invention, in order to connect a semiconductor chip and a substrate, a connector on which the semiconductor chip is mounted is provided, and the connector is connected to the substrate to connect the semiconductor chip and the substrate. By forming the electrodes of the connector on the side to be connected to the substrate in a concentrated manner near the center of the connector, the stress applied due to the difference in the thermal expansion coefficient from the substrate is reduced (the basic configuration of the present invention (1 )).

Also, a connector (programmable interconnector) capable of externally setting the connection between semiconductor chips
The semiconductor chip mounting electrodes and wiring are provided on the connector so that the semiconductor chip can be directly attached to the connector (basic configuration (2) of the present invention).

FIG. 1 is a diagram showing a basic configuration (1) of the present invention. In the figure, 1 is a semiconductor chip, which is a semiconductor element.

Reference numeral 2 denotes an electrode which electrically joins and fixes the semiconductor chip 1 and the chip connector 3 together. Reference numeral 3 denotes a chip connector (semiconductor element mounting connector) for electrically connecting and fixing the semiconductor chip 1 and the substrate 5.

Reference numeral 4 denotes an electrode which electrically connects and fixes the chip connector 3 and the substrate 5.
The electrode 4 is provided near the center of the chip connector 3 and is electrically connected to the electrode 2 by wiring.

Reference numeral 20 denotes a pad, which serves as the electrode 2 of the semiconductor chip (semiconductor element) 1. Reference numeral 21 'is a pad, which is a pad of a chip connector (semiconductor element mounting connector) 3 for connecting the semiconductor chip 1, and an electrode 2
It will be.

Reference numeral 22 denotes a pad, which is a pad (electrode) of the chip connector (semiconductor element mounting connector) 3 connected to the substrate 5. A description of the operation of the configuration of the figure will be given later.

FIG. 2 shows the basic configuration (2) of the present invention. In the figure, 1 is a semiconductor chip, which is a semiconductor element.

Reference numeral 2 denotes an electrode for electrically connecting and fixing the semiconductor chip 1 and the programmable interconnector (semiconductor element mounting connector) 10. Reference numeral 10 denotes a connector (programmable interconnector) capable of externally setting electrical connection between semiconductor chips, which is a semiconductor element mounting connector.

Reference numeral 21 'is a pad, which constitutes an external connection electrode which serves as a power supply terminal and an input / output signal terminal of the programmable interconnector (semiconductor element mounting connector) 10.

Reference numeral 13 denotes a wiring coupling element, which is composed of a fuse element, a memory element, etc., and is arranged in a matrix to externally set whether or not the internal wirings 12 are connected. .

Reference numeral 12 denotes an internal wiring, which is an internal wiring of the programmable interconnector 10, in which each wiring coupling is determined by the wiring coupling element 13, and the pad 2
1 ', which defines the wiring between semiconductor chips.

Note that the connection between the wiring coupling element 13 and the pad 21 'can be performed by using the electrode technology in the semiconductor integrated circuit, for example, when the wiring coupling element 13 is composed of a semiconductor memory element. it can.

The operation of the configuration of FIG. 2 will be described later.

[0035]

The operation of the basic configuration of FIG. 1 will be described. The semiconductor chip 1 is mounted on the chip connector 3 and electrically connected to the chip connector 3 by the electrodes 2. Semiconductor chip 1
And the chip connector 3 are made of the same material (silicon). Therefore, since the thermal expansion coefficients of both are the same, the thermal stress acting on the electrode 2 is small.

On the other hand, the chip connector 3 is joined to the substrate 5 by the electrode 4 and mechanically fixed. Electrode 2
Since the electrode 4 and the electrode 4 are electrically connected by the wiring provided in the chip connector 3, the semiconductor chip 1 and the substrate 5 are electrically connected via the chip connector 3.

The stress applied to the electrodes in the basic structure (1) of the present invention will be described with reference to FIG. Figure 3 (a)
Shows the case of the present invention, and (b) shows the conventional case.

In the figure, 1 is a semiconductor chip, and 2 is an electrode, which is an electrode for electrically connecting and fixing the semiconductor chip 1 and the substrate 5.

Reference numeral 3 is a chip connector. Reference numeral 4 denotes an electrode, which is an electrode for electrically connecting and fixing the chip connector 3 and the substrate 5.

Reference numeral 5 is a substrate. Since the board 5 and the chip connector 3 are usually made of different materials, they have different coefficients of thermal expansion. However, in the present invention, since the electrodes 4 are concentrated near the center of the chip connector 3, the thermal stress acting on the electrodes 4 is small as shown in (a). Therefore, the distortion caused by heat applied to the chip connector 3 is small, and the connection between the chip connector 3 and the substrate 5 is stable. On the other hand, in the conventional case, the semiconductor chip 1
Since the electrode 2 provided on the periphery of the electrode is coupled to the substrate 5 and the thermal expansion coefficients of both are different, the thermal stress acting on the electrode is large as shown in (b) and the electrode is mechanically damaged. It was easy.

Next, the operation of the basic configuration (2) of the present invention will be described. The semiconductor chip 1 is connected to the internal wiring of the programmable interconnector (semiconductor element mounting connector) 10 via the electrode 2. Then, each semiconductor chip is connected by the internal wiring set in advance by the wiring coupling element 13. In the wiring coupling element 13, a fuse element, a memory element, or the like is provided at the intersection of the internal wiring 12, and in the case of the fuse element, the wiring is set by cutting the fuse at the location where the wiring is separated. In the case of a memory device, the value of 1 or 0 is externally set to connect or disconnect the wires to determine the wires.

The programmable interconnector (semiconductor element mounting connector) 10 is mounted on a printed circuit board or the like. Alternatively, the programmable interconnector (mounting connector) 10 is fixed on the mount board, and the pad 2
1 '(external connection electrode) is connected to an external lead wire or the like to form a module.

According to the basic configuration (2) of the present invention, since the semiconductor chip 1 is directly fixed on the programmable interconnector (semiconductor element mounting connector) 10, the wiring between the semiconductor chips is not changed without changing the wiring of the substrate. Wiring can be changed. Therefore, the line can be easily changed, the mounting area on the substrate can be reduced, and the device can be downsized. Further, since the semiconductor chip 1 and the programmable interconnector (semiconductor element mounting connector) 10 are made of the same material (silicon), they are not mechanically damaged by thermal strain.

[0044]

EXAMPLE FIG. 4 shows an example of the basic configuration (1) of the present invention. In the figure, 1 is a semiconductor chip.

Reference numeral 2 is an electrode for electrically connecting and fixing the semiconductor chip 1 and the chip connector 3. 3 is a chip connector.

Reference numeral 4 is an electrode for electrically connecting and fixing the chip connector 3 and the substrate 5. 27 is a wiring.

A wiring hole 28 is provided with a wiring layer on its inner surface. In the enlarged view A of the electrode, 20 is a pad of the semiconductor chip 1.

Reference numeral 21 is a bump. Reference numeral 22 is a pad of the chip connector 3. In the enlarged view B of the electrodes, 24 is a pad of the chip connector 3.

Reference numeral 25 is a bump. Reference numeral 26 is a pad of the substrate 5. Semiconductor chip 1 and chip connector 3 have electrodes 2
Is electrically connected and mechanically coupled. The chip connector 3 and the substrate 5 are electrically connected and mechanically coupled by the electrode 4.

Pad 22 and pad 2 of chip connector 3
The wiring 4 is electrically connected to the wiring 27 by the internal wiring of the wiring hole 28. Therefore, the semiconductor chip 1 has the electrode 2-wiring 27.
-Internal wiring of the wiring hole 28-Electrode 4-Electrically connected by the substrate 5.

FIG. 5 shows an embodiment of the electrode pattern of the basic constitution (1) of the present invention. In the figure, 1 is a semiconductor chip, 3
Is a chip connector.

Reference numeral 20 is a pad of the semiconductor chip 1. Two
Reference numeral 4 is a pad on the side of the chip connector that is connected to the substrate. (a) is an example of a semiconductor chip. An example of the semiconductor chip 1 in which a 400-pin electrode is formed on a 20 mm square silicon chip is shown.

(B) is an example of a chip connector on which the semiconductor chip of the 400-pin electrode of (a) is mounted. For the 400-pin semiconductor chip 1, the pad 24 of the chip connector 3 can be configured to have a square area of 2 mm on each side of 0.1 mm.

(C) is an example of a chip connector and shows a case where the pads 24 on the side connected to the substrate are arranged in a zigzag pattern. FIG. 6 shows an embodiment of the wiring pattern of the basic configuration (1) of the present invention.

The figure shows the wiring pattern of the chip connector. (a) is an example in which wiring patterns are provided on both sides of the chip connector. (b) is a plan view of the chip connector 3 of (a).

In FIG. 6C, the wiring 29 is arranged on the side surface of the chip connector 3 to connect the pads 22 and the pads 26 on both sides. In the figure, 3 is a chip connector.

Reference numeral 22 is a pad for connecting a semiconductor chip. Reference numeral 26 is a pad that is connected to the substrate. Reference numeral 27 is a wiring arranged on the surface having the pad 22.

28 'is a wiring provided on the surface having the pad 26. Reference numeral 29 is wiring for connecting the pad 22 and the pad 26 via the upper surface, the side surface and the lower surface of the chip connector.

Reference numeral 30 denotes a wiring hole, which has a wiring layer on its inner surface and electrically connects the upper pad and the lower wiring layer. In the configurations of (a) and (b), the wiring 27 and the wiring 2
Since the wiring is divided into both sides of the chip connector 3 as in 8 ', the width of the wiring can be widened,
Wiring can be afforded.

As shown in (c), the upper pad 22 and the lower pad 26 may be connected via the side surface of the chip connector. FIG. 7 shows an embodiment (1) of the basic configuration (2).

In the figure, 1 is a semiconductor chip, and 2 is an electrode for electrically connecting and fixing the semiconductor chip 1 and the programmable interconnector 10.

Reference numeral 4 is an electrode for electrically connecting and fixing the programmable interconnector 10 and the substrate 5. Reference numeral 5 denotes a substrate, such as a printed circuit board.

Reference numeral 10 is a programmable interconnector. In the enlarged view A of the electrode, 20 is a pad of the semiconductor chip.

Reference numeral 21 is a bump for connecting the pad 20 and the pad 22. Reference numeral 22 is a pad of the programmable interconnector 10. In enlarged view B of the electrode, it is a pad of a 24 programmable interconnector.

Reference numeral 25 is a bump. Reference numeral 26 is a pad of the substrate 5. (a) is a programmable interconnector 10
And a method of integrating the substrate 5 (in the case where the surface on which the semiconductor chip 1 is mounted is faced down to be integrated with the substrate).

The semiconductor chip 1 is mounted on the programmable interconnector 10. Then, the pads 24 of the programmable interconnector 10 are connected by the bumps 25 so that the pads 24 of the programmable interconnector 10 are superposed on the pads 26 of the substrate 5 (see the enlarged view B of the electrode), and the substrate 5 and the programmable interconnector 10 are electrically connected. Fix it. The semiconductor chip 1 and the programmable interconnector 10 are coupled to each other by electrically connecting the pad 20 of the semiconductor chip 1 and the pad 22 of the programmable interconnector 10 with the bump 21 and fixing them, as shown in the enlarged view A of the electrode. By.

(B) is a programmable interconnector 1
The state where 0 and the substrate 5 are integrated is shown. FIG. 8 shows an embodiment (2) of the basic configuration (2) of the present invention.

In the figure, 1 is a semiconductor chip. Two
Is an electrode.

Reference numeral 5 denotes a substrate, which is a printed circuit board, a mount, or the like. 24 is a programmable interconnector 1
The pad of 0 serves as a power supply terminal and an input / output signal terminal.

Reference numeral 26 is a pad on the substrate. 42 is a wire for electrically connecting the pad 24 and the pad 26.

According to the present invention, the programmable interconnector 10 having the semiconductor chip 1 mounted thereon is fixed to the substrate 5 such as a mount as shown in (b), and the wire 42 is electrically connected to the electrode of the substrate 5 and then hermetically sealed. It can be made into a module by using the above method.

[0072]

According to the basic configuration (1) of the present invention, the stress applied to the connector due to the difference in the thermal expansion coefficient between the board and the connector can be reduced. Therefore, it is possible to obtain an integrated structure of the semiconductor chip and the substrate which is not mechanically damaged by thermal strain without changing the configuration of the semiconductor chip.

Further, according to the basic configuration (2) of the present invention, since the programmable interconnector and the semiconductor chip are made of the same material, thermal strain between them is small and mechanical damage is not caused. Further, since the wiring between the semiconductor chips is made by the internal wiring of the programmable interconnector, even if the wiring is changed between the semiconductor chips, it is easy to change the wiring of the programmable interconnector without changing the wiring of the substrate. Wiring can be changed.

[Brief description of drawings]

FIG. 1 is a diagram showing a basic configuration (1) of the present invention.

FIG. 2 is a diagram showing a basic configuration (2) of the present invention.

FIG. 3 is a diagram for explaining the operation of the basic configuration (1) of the present invention.

FIG. 4 is a diagram showing an embodiment of the basic configuration (1) of the present invention.

FIG. 5 is a diagram showing an example of an electrode pattern of the basic configuration (1) of the present invention.

FIG. 6 is a diagram showing an example of a wiring pattern of the basic configuration (1) of the present invention.

FIG. 7 is a diagram showing an embodiment (1) of the basic configuration (2) of the present invention.

FIG. 8 is a diagram showing an embodiment (2) of the basic configuration (2) of the present invention.

FIG. 9 is a diagram showing a conventional semiconductor chip and a mounting structure.

FIG. 10 is an explanatory diagram of stress acting on a conventional semiconductor chip.

FIG. 11 is a diagram showing a conventional method of mounting a semiconductor chip and a programmable interconnector.

[Explanation of symbols]

 1: Semiconductor chip (semiconductor element) 2: Electrode 3: Chip connector (semiconductor element mounting connector) 4: Electrode 5: Board 10: Programmable interconnector 12: Internal wiring 13: Wiring coupling element

Claims (3)

[Claims] 1. A substrate (5) provided on a surface provided with an electrode (2) for connecting a semiconductor chip (1) and on a surface different from the surface electrically connected to the electrode (2) on the surface. In a semiconductor device mounting connector (3) having an electrode (4) connected to the substrate, the electrode (4) connected to the substrate (5) is formed near the center of the semiconductor device mounting connector (3). A semiconductor element mounting connector characterized in that 2. An electrode for connecting a plurality of semiconductor chips (1)
(2) and an external connection electrode (21) connected to the electrode (2),
A semiconductor device is provided with a wiring coupling element (13) for connecting the electrode (2) connecting the semiconductor chip (1) and the external connection electrode (21), and changing the wiring of the wiring coupling element (13). Tip
A semiconductor element mounting connector capable of changing the electrical connection between the electrode (2) for connecting (1) and the external connection electrode (21). 3. The semiconductor element mounting connector according to claim 2, wherein the semiconductor element mounting connector (10) is a programmable interconnector.