JPH02192144A - Gate array type semiconductor device - Google Patents

Abstract

PURPOSE:To make it possible to form many basic cells on one chip in the limit of manufacture of the dimension of the chip by a method wherein peripheral circuit chips, which are respectively constituted of each peripheral circuit comprising a static breakdown strength protective circuit, a latch-up protective circuit, an output transistor and the like, and an internal circuit chip comprising basic cells other than the above circuits, transistor and the like are connected to each other on a package. CONSTITUTION:A P-channel output transistor, an N-channel output transistor and a latch-up protective circuit are contained in respective peripheral circuit cells 501. Static protective circuits are respectively constituted of part of the respective output transistors and peripheral circuit chips 5 are provided arranging a necessary number of the cells 501 on each one side. An internal circuit chip 4 and the chips 5 are conformed to lead patterns 1 and peripheral internal patterns (wirings) 2 and are mounted on a package main body 3 in such a way that pads face downward to make the leads 1 and pads 502 and pads 503 and the wirings 2 correspond to each other to connect. Moreover, a power conductor 6 and pads 504 and a grounding conductor 7 and pads 505 are connected to each other to feed a power supply to the chips 5. Thereby, an internal circuit region is made wide within the limited dimension of a chip and the improvement of an integration degree can be attained.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a GaI array type semiconductor device.

[Conventional technology]

As shown in FIG. 8, a conventional gate array type semiconductor device includes an internal circuit area 803 provided in the center of a semiconductor chip 801 and a peripheral circuit cell 802 for inputting and outputting external signals.
have. As shown in FIG. 9, the peripheral circuit cell 802 includes an input buffer and an output buffer 905. Output buffer transistors 902, 903. It consists of functional blocks of an electrostatic voltage protection circuit and a latch-up protection circuit 904, and is formed on the same semiconductor chip 801 as an internal circuit area 803 that implements functions other than an interface.

[Problem to be solved by the invention]

In the conventional gate array type semiconductor device described above, the peripheral circuit cells and the internal circuit area are configured on the same chip.
Sufficient output drive capacity and electrostatic withstand voltage.

In order to ensure latch-up tolerance, a large area is required for the peripheral circuit cells. In addition, in order to minimize the pad spacing in order to accommodate a large number of pins, the height of the peripheral circuit cell increases, and the internal circuit area becomes narrower within the limited chip dimensions.
This has the disadvantage that it hinders the improvement of the degree of integration. Furthermore, the input buffer and output pre-buffer sections are equipped with a large number of transistors to accommodate the maximum functionality of the peripheral circuit cells, but in actual products, not all of them are used, which hinders the improvement of integration density. It has the disadvantage of becoming. In addition, it has the necessary number of peripheral circuit cells to be mounted on a package with the maximum number of external terminals, but if it is mounted on a package with fewer external terminals than the maximum number of external terminals, unused peripheral circuit cells occurs, which hinders the improvement of the degree of integration. On the other hand, products with a large number of external terminals and a small number of used internal circuit cells have the disadvantage that unused internal circuit cells are generated, which also hinders the improvement of the degree of integration.

[Means to solve the problem]

A gate array semiconductor device of the present invention includes an internal circuit chip having a basic cell mounted in the center of a package body;
A peripheral circuit that processes input/output signals of the gate array type semiconductor device is arranged around the internal circuit chip, and a peripheral circuit chip that is mounted on the package body around the internal circuit chip. wiring that is provided to electrically connect the internal circuit chip and the peripheral circuit chip;
The device includes a power supply line and a ground line provided on the outer periphery of the wiring and connected to the peripheral circuit chip, and a lead for external circuit connection connected to the peripheral circuit chip and provided outside the peripheral circuit chip.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a plan view showing a first embodiment of the present invention, FIG. 2 is a bottom view of a peripheral circuit chip of the first embodiment of the present invention, and FIG.
The figure is a schematic diagram showing the configuration of the peripheral circuit cell of the first embodiment of the present invention, FIG. 4 is a layout diagram of the internal circuit chip of the first embodiment of the present invention, and FIG. FIG. 3 is a wiring layout diagram of the package body of the embodiment.

As shown in FIG. 3, peripheral circuit cell 501 includes P-channel output transistors 511 . N-channel output transistor 513. A latch-up protection circuit 512 is built-in. The electrostatic protection circuit is composed of a portion of the output transistors 511 and 513. The peripheral circuit chip 5 has one peripheral circuit cell 501.
The required number is arranged on each side. Pad 502 for connection with lead 1. Pad 503 for connection with wiring 2. Pad 504 for connection to power supply line 6. Pad 505 for connection with ground wire 7. Each of the pads 401 of the internal circuit chip 4 forms a bump. As shown in FIG. 5, the package body 3 has lead patterns 1. Wiring 2. Power line 6. A grounding wire 7 is provided respectively, and the internal circuit chip 4 and the peripheral circuit chip 5 are mounted on the package body 3 with the pads facing downward in alignment with the lead pattern 1 and the peripheral internal pattern 2 formed on the package body 3. and lead 1 and pad 502. Pad 503 and wiring 2. Wiring 2 and pad 4
01 in correspondence with each other. Similarly, the power line 6 and the pad 504. The ground line 7 and the pad 505 are connected to supply power to the peripheral circuit chip 5.

FIG. 6 is a plan view showing a second embodiment of the present invention, and FIG. 7 is a wiring layout diagram of the package body of the second embodiment of the present invention.

The internal circuit chip 8 is formed into a rectangle, and the wiring 2 of the package body 3 is aligned with the pad of the internal circuit chip 8.
This embodiment has the same configuration as the first embodiment except that the layout is set.

In this embodiment, since a product having the same number of external terminals as in the first embodiment is formed using a rectangular internal circuit chip, the area of the internal circuit chip can be reduced. Therefore, products with a large number of pins and a small number of gates have the advantage that the manufacturing cost of internal circuit chips can be reduced. Compared to the area of the internal circuit chip of the first embodiment, the second embodiment cannot achieve a 24% reduction in area.

〔Effect of the invention〕

As explained above, the present invention provides a gate array semiconductor device that includes a peripheral circuit chip consisting of peripheral circuits including an electrostatic voltage protection circuit, a latch tube protection circuit, an output transistor, etc., and an internal circuit including other basic cells. By electrically connecting the circuit chip to the package, it is possible to form a large number of basic cells on one chip within the manufacturing limit of the chip size. Furthermore, since the peripheral circuit chips are independent, it is possible to improve electrostatic withstand voltage, latch-up tolerance, and output drive capability without sacrificing the number of internal cells. Furthermore, for products that use fewer internal cells than the number of external terminals, it is possible to reduce the internal circuit chip to an appropriate area while securing the necessary number of external terminals.

Furthermore, as in Example 1, if the wiring patterns connecting the internal circuit chip and the peripheral circuit chip are created in parallel on each side, the same peripheral circuit chip and the package with the same wiring pattern 1 may have internal circuits with different dimensions. This has the effect of making the chip compatible.

[Brief explanation of the drawing]

FIG. 1 is a plan view showing a first embodiment of the present invention, FIG. 2 is a bottom view of a peripheral circuit chip of the first embodiment of the present invention, and FIG.
The figure is a schematic diagram showing the configuration of the peripheral circuit cell of the first embodiment of the present invention, FIG. 4 is a layout diagram of the internal circuit chip of the first embodiment of the present invention, and FIG. FIG. 6 is a plan view showing the second embodiment of the present invention; FIG. 7 is a layout diagram of the wiring of the package body of the second embodiment of the present invention; Figure 8 shows layouts 1 to 9 showing an example of a conventional semiconductor chip.
The figure is a schematic diagram showing the configuration of a conventional peripheral circuit cell. 1... Lead, 2... Wiring, 3... Package body, 4... Internal circuit chip, 5... Peripheral circuit chip,
6...Power supply line, 7...Grounding line, 8...Internal circuit chip, 50]...Peripheral circuit cell, 502.503,5
04゜505...Pad, 506...Power line, 50
7...Grounding wire, 508...Latch-up protection circuit,
510... Pad, 511... P channel output transistor, 512... Latch-up protection circuit, 513
...N-channel output transistor, 401...pad, 402...basic cell, 801...semiconductor chip,
802... Peripheral circuit cell, 803... Internal circuit area, 901... Honing pad, 902... P channel output transistor, 903... N channel output transistor, 904... Latch-up protection circuit, 9
05...Input buffer and output buffer.

Claims (1)

[Claims] In a gate array type semiconductor device, an internal circuit chip having a basic cell mounted in the center of a package body;
A peripheral circuit chip having a peripheral circuit for processing input/output signals of the gate array type semiconductor device and disposed around the internal circuit chip, and a peripheral circuit chip disposed on the package body around the internal circuit chip. Wiring for electrically connecting the internal circuit chip and the peripheral circuit chip;
A power supply line and a ground line provided on the outer periphery of the wiring and connected to the peripheral circuit chip, and a lead for external circuit connection connected to the peripheral circuit chip and provided outside the peripheral circuit chip. A gate array type semiconductor device.