JPH0272659A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To increase signal wiring patterns and to implement a compact configuration by supplying power to an outermost logic block group in a semiconductor chip through power source wirings which are provided individually from chip power feeding terminals directly without providing main power source lines. CONSTITUTION:A semiconductor chip 1 has a plurality of logic blocks 2 which are arranged in a matrix pattern. A plurality of power feeding terminals 3 for feeding power to the logic blocks 2 are provided around the logic blocks 2. The block power feeding terminals 3 are connected to chip shaped power feeding terminals 4. At least one main power source line 8 is regularly provided for every power potential in a wiring region 5 between the blocks. The main power source line 8 is not provided at the outside of the peripheral logic blocks 2 in the semiconductor chip 1. The block power feeding terminals 3 are directly connected to the chip power feeding terminals 4. Since the number of the main power source lines 8 as the first wirings can be decreased in this way, the signal wiring patterns can be increased by that amount, and the circuit can be made compact.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit (
Hereinafter, it will be referred to as Lsi. ), and particularly relates to improvements in power supply wiring for semiconductor circuit elements irregularly arranged on a semiconductor chip.

[Conventional technology]

In conventional LSIs, in order to increase the packaging density of chips, an LSI design method that allows semiconductor circuit elements to be placed anywhere within the chip is being adopted. Furthermore, in conventional LSIs, power supply wiring to semiconductor circuit elements is wired in a regular array. The above-mentioned prior art is disclosed in, for example, Japanese Patent Laid-Open No. 142544/1983.

[Problem to be solved by the invention]

Although the above-mentioned conventional LSI adopts an LSI design method that allows semiconductor circuit elements to be placed anywhere within the chip, the power supply wiring to the semiconductor circuit elements is not done in a regular arrangement. Ta. Therefore, under a predetermined chip size restriction, the usage rate of the power supply wiring pattern increases and the use of the signal wiring pattern is hindered.

FIG. 2 is an explanatory diagram showing a conventional semiconductor chip, showing a semiconductor chip 1, a logic block 2, a block power supply terminal 3, a chip power supply terminal 4, an inter-block wiring area 5, a first layer wiring 6, and a second layer wiring. It consists of 7. Here, since the first layer wiring 6, which is the main power line 8 of the power source, is arranged regularly, the above-mentioned problem occurs.

The present invention has been made in view of the problems of the prior art described above, and has a power supply wiring arrangement that can reduce the number of power supply wirings for power supply, and as a result increases the capacity of the signal wiring pattern. Ls, which makes it possible to reduce the chip size
The purpose is to provide i.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention is applied to a semiconductor integrated circuit in which a large number of logic blocks are arranged on a semiconductor chip. It is characterized by being directly supplied with power through individually provided power supply wiring.

[Effect]

With the above configuration, the number of power supply main lines for the outermost logic block can be reduced, so that the area of the signal wiring pattern can be increased and the LSI can be made smaller.

[Example] Hereinafter, the present invention will be described in more detail with reference to Examples shown in the accompanying drawings.

FIG. 1 is an explanatory diagram showing an embodiment of the present invention. 1st
In the figure, a semiconductor chip 1 has a plurality of logic blocks 2 arranged in a matrix.

The logic block 2 is formed in a rectangular shape and is constructed by combining a plurality of circuit elements (hereinafter referred to as cells) that are smaller components.

A cell is a combination of one or more basic circuit elements such as transistors, resistors, and capacitors. Further, the size of each logical block 2 is usually set to be approximately equal.

A plurality of power supply terminals 3 for supplying power to the logic block 2 are provided around the logic block 2 . This block power supply terminal 3 is connected to a chip-shaped power supply terminal 4.

Between adjacent blocks, there is an inter-block wiring area 5 for wiring between the blocks. In the inter-block wiring area 5, a first
A layer wiring 6 and a second layer wiring 7 are provided. The first layer wiring 6 is a horizontal wiring, and the second layer wiring is a vertical wiring.

Further, in the inter-block wiring region 5, at least one power main line 8 is regularly provided for each potential. The power main line 8 is not provided outside the peripheral logic block 2 in the semiconductor chip 1, and the block power supply terminal 3 and the chip power supply terminal 4 are directly connected.

Regarding LSI design, there are two methods for realizing power supply wiring between cells arranged in a chip shape. The first method is called a gate array, in which the wiring area is fixed, and the second method is called a standard cell, in which the wiring area is variable and circuits are arranged to make the entire chip smaller. , wiring. The present invention is particularly effective for the standard cell system, and the peripheral logic block 2 in the semiconductor chip 1
By reducing the number of power supply main lines, it is possible to provide many signal wiring patterns.

For example, if 10 blocks are arranged in each of the X and Y directions, the number of power supply main lines (first layer wiring) on the top and bottom sides of the semiconductor chip can be reduced, so the number of power supply main lines can be reduced to about 2.
It can be reduced by 0%.

〔Effect of the invention〕

According to the present invention, it is possible to reduce the power supply main line as the first wiring in the logic block around the semiconductor chip, so it is possible to increase the number of signal wiring patterns and to reduce the size of the LSI.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing an embodiment of a semiconductor integrated circuit according to the present invention, and FIG. 2 is an explanatory diagram showing an example of a conventional semiconductor integrated circuit. 1... Semiconductor chip, 2... Logic block, 3...
・Block power supply terminal, 4...Chip power supply terminal, 5...
- Inter-block wiring area, 6... first layer wiring, 7...
2nd layer wiring, 8... power main line. Agent Patent Attorney Masami Akimoto

Claims (1)

[Claims] 1. In a semiconductor integrated circuit in which a large number of logic blocks are arranged on a semiconductor chip, the outermost logic blocks in the semiconductor chip are powered directly from the chip power supply terminal by individual power wiring, without providing a main power line. A semiconductor integrated circuit characterized by: