JPH04184936A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To reduce the peripheral cell width of a pad, by arranging pads for wire bonding at two portions on one peripheral cell, and arranging both of the pads so as to be diagonal. CONSTITUTION:A pad 1a and a pad 1b are arranged on the peripheral cell of a semiconductor integrated circuit so as to be zigzag. In order to widely form a peripheral cell logic circuit region 3 in the peripheral cell, a VSS wiring 2a, and a VDD wiring 2b are formed in shaded regions. I/O signal terminals 5a, 5b on the peripheral cell for connecting the region 3 with an inner logic circuit are arranged on one side of the inner logic side on the peripheral cell. An input signal and an output signal are delivered to the pads 1a, 1b and the terminals 5a, 5b, respectively, via the region 3. By arranging the pads 1a, 1b in this manner, the restriction of pad interval on the ajacent cells for wire bonding at the time of assembling can be evaded, and the dimension of the pad single end and the peripheral cell end is unnecessitated, so that the peripheral cell width of a pad can be reduced.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to semiconductor integrated circuits.

[Conventional technology]

FIG. 5 is a plan view showing the configuration of a conventional peripheral cell. In the figure, the peripheral cell of B is the pad (1) placed in one place on the peripheral cell, and the VS shown in (2a) and (2b).
S wiring and vDD wiring, the peripheral cell logic circuit area (3) surrounded by dotted lines, the wiring (4) connecting the pad (1) and the peripheral cell logic circuit area (3), and the peripheral cell logic circuit area ( 3) and a wiring outlet (hereinafter referred to as input/output signal terminal on the peripheral cell) for connecting with the internal logic circuit.

Next, an example of conventional peripheral cells and internal logic circuits and placement and wiring using the peripheral cells will be described with reference to FIGS. 5 and 6.

In FIG. 6, (6) is a semiconductor chip, and on this semiconductor chip (6) there is an internal logic port 11B (7) and a peripheral cell row (8a) arranged so that the peripheral cells of FIG.
), (8b) are arranged, and the internal logic circuit (7
) and peripheral cell input/output signal terminals (5
) are connected by wiring (9).

Also, VOO and V in (2a) and (2b) shown in Figure 5
As shown in Figure 6, the SS wiring is connected to adjacent peripheral cells at equivalent positions, and is further connected to horizontal peripheral cell columns (
8a) and the vertical peripheral cell row (8b) are also wired (10a)
.

(10b).

[Problem to be solved by the invention]

Problems with the conventional peripheral cell will be explained using FIG. 7.

FIG. 7 shows the peripheral cell row (8a) in FIG. 6 described above.

FIG. 8B is a plan view in which two adjacent peripheral cells in FIG. 8B are extracted and enlarged. In the figure, (12) and (13) represent the vertical and horizontal dimensions of the pad (1), which are designated a and b, respectively. (14) represents the center-to-center dimension of each pad on adjacent peripheral cells, and is denoted by C. This dimension C is set to a dimension that allows wire bonding due to restrictions during wire bonding of the assembly. (15) is the dimension from one end of the pad (1) provided to satisfy dimension C to the end of the peripheral cell, and if this is d, then d≧(c-b)/2
... (1) Dimensions as shown in formula 11 above are required.

When performing placement and wiring using this peripheral cell, if the chip size is determined by the cell width shown in (16) in Figure 7, there is a problem that the above dimension d has a large effect on the chip size. .

This invention was made to solve the above-mentioned problems, and its purpose is to reduce the cell width (16) in FIG. 5 of the peripheral cells.

[Means to solve the problem]

The semiconductor integrated circuit according to the present invention includes a pad, a peripheral cell logic circuit, a vss wiring, and a vDDti! In a peripheral cell equipped with a wire, pads are provided at two locations in the peripheral cell, and both pads are arranged in a staggered manner.

[Effect]

The peripheral cell in the invention of Party B is one peripheral cell with two pads.
By arranging them in a staggered manner, it is possible to avoid restrictions on the spacing between pads on adjacent peripheral cells due to wire bonding during assembly, and the dimensions of one end of the pad and the end of the peripheral cell are no longer required. The peripheral cell width per pad can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a plan view showing the configuration of peripheral cells of a semiconductor integrated circuit which is an embodiment of the present invention.
), (lb) are two pads arranged in a staggered manner on the peripheral cells, which are indicated by diagonal lines. (2a),
(2b) is the V device wiring and the vDD wiring, which are surrounded by dotted lines. (3) is the peripheral cell logic circuit area p vss wiring (
21) and the VDD wiring (2b) are connected to the first
It has a shape like the dotted line in the figure. Also, (4a).

(4b) is the wiring connecting the pad (1m), (lb) and the peripheral cell logic circuit (3); (5a), (5b)
) is an input/output signal terminal on the peripheral cell for connecting the peripheral cell logic circuit area (3) and the internal logic circuit, and is arranged on one side of the peripheral cell on the internal logic circuit side. Then, pads (1m), (lb) and input/output signal terminals (5m) on peripheral cells.

(5b), each input or output signal is transmitted via the peripheral cell logic circuit area (3).

Next, a peripheral cell of the present invention and an example of internal circuitry and wiring using this peripheral cell will be described with reference to FIGS. 1 and 2.

In FIG. 2, (6) is a semiconductor chip, and on this semiconductor chip (6), an internal logic circuit (7) and a peripheral cell row (8 m) are arranged so that the peripheral cells shown in FIG. 1 are arranged adjacently.
, (8b) is placed, and the internal logic port! @ (7
) and the peripheral cells on the peripheral cell rows (8m) and (8b) are connected to the input/output terminals (5a) and (5b) on the peripheral cells located at the two locations shown in Figure 1 and wiring. (9
) are connected by.

In addition, the VDD and VSS wiring (2a) shown in FIG.
As shown in Figure 2, (2b) is connected to adjacent peripheral cells at equivalent positions, and further horizontal peripheral cell rows (8
a) and the vertical peripheral cell row (8b) are also arranged @(10a
).

(10b).

Note that the two pads arranged in a staggered manner in the peripheral cell of the above embodiment were arranged so as not to overlap with each other in the height direction of the peripheral cell, but the pads were arranged in a staggered manner as shown in FIG. 2 pads (Ia), (lb)
If they are arranged so as to overlap in the direction of the peripheral cell height (15), the peripheral cell width (16) will be further reduced, and the degree of overlap may be increased as much as the wire bonding constraints of the assembly allow.

Furthermore, as shown in FIG. 4, one peripheral cell has multiple pads (la
) to (1d) can be arranged in a staggered manner with respect to adjacent pads to achieve the same effect.

〔Effect of the invention〕

As described above, according to the present invention, two pads are provided on the peripheral cells.
Since the cells are arranged in a staggered manner, the width of the peripheral cells can be smaller than the width of two conventional peripheral cells, and if the semiconductor chip size is determined by the width of the peripheral cells,
This has the advantage that a smaller chip size can be obtained than using conventional peripheral cells.

[Brief explanation of drawings]

FIG. 1 is a plan view of a peripheral cell which is an embodiment of the present invention;
FIG. 2 is a plan view of a semiconductor integrated circuit in which internal circuits and layout and wiring are performed using peripheral cells, and FIGS. 3 and 4 are plan views of peripheral cells showing other embodiments of the present invention. Fig. 5 is a plan view of a conventional peripheral cell, Fig. 6 is a plan view of a semiconductor integrated circuit when the internal circuit and layout are done using the peripheral cell shown in Fig. 5, and Fig. 7 is a plan view of a conventional peripheral cell. FIG. 4 is an explanatory diagram of various dimensions of adjacent peripheral cells. In the figure, (11, (la) to (1d) are pads on peripheral cells, (2a) and (2b) are VSS wiring and V
DD wiring, (3) is the logic circuit area on the peripheral cell, (4)
, (4a) to (4d) are the wiring connecting the pad and the peripheral cell logic circuit, f5L (5a) to (5d) are the input/output signal terminals on the peripheral cell, (6) is the semiconductor chip, and (7) is the internal logic. The circuit, (8a) and (8b) are the peripheral cell columns, (
9) is the wiring connecting the peripheral cells and the internal circuit; (10a)
) and (10b) are wirings that connect the VSS and vDD wirings of the horizontal and vertical peripheral cell columns. In addition, in the figures, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] A wire bonding pad is necessary for connecting the internal logic circuit formed by combining basic cells with a wire bonding pad that brings out the input or output signal to an external lead, and the internal logic circuit and the pad. In the peripheral cell including a peripheral cell logic circuit, a first power supply wiring, and a second power supply wiring, the pad is placed on one peripheral cell twice.
What is claimed is: 1. A semiconductor integrated circuit characterized in that pads are provided at two locations, and further, both pads are arranged diagonally.