JPH03104265A - Manufacture of semiconductor package - Google Patents
Manufacture of semiconductor packageInfo
- Publication number
- JPH03104265A JPH03104265A JP24086989A JP24086989A JPH03104265A JP H03104265 A JPH03104265 A JP H03104265A JP 24086989 A JP24086989 A JP 24086989A JP 24086989 A JP24086989 A JP 24086989A JP H03104265 A JPH03104265 A JP H03104265A
- Authority
- JP
- Japan
- Prior art keywords
- lead
- chip
- leads
- semiconductor package
- vicinity
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 23
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 22
- 238000000034 method Methods 0.000 claims description 9
- 230000000994 depressogenic effect Effects 0.000 claims description 3
- 238000005452 bending Methods 0.000 abstract description 5
- 230000010354 integration Effects 0.000 abstract description 4
- 238000005520 cutting process Methods 0.000 abstract description 3
- 238000000465 moulding Methods 0.000 abstract 1
- 238000005516 engineering process Methods 0.000 description 3
- 238000004080 punching Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 2
- 238000003780 insertion Methods 0.000 description 2
- 230000037431 insertion Effects 0.000 description 2
- 239000011347 resin Substances 0.000 description 2
- 229920005989 resin Polymers 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000003754 machining Methods 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Abstract
Description
【発明の詳細な説明】
概要
ＩＣ，ＬＳＩ等の半導体パッケージの製造方法に関し、
集積度の高い半導体パッケージの効率的な製造方法の提
供を目的とし、
ステムの両面に第ｌチップ及び第２チップを設け、複数
のリードが平面的に配列されてなるＩＪ 一ドフレーム
を、該リードの一端側が該第ｌチップの近傍に位置する
ように配置して、該第１チップとリードの一端をそれぞ
れワイヤボンディングし、該リードの他端に前記第２チ
ップ側に落ち込んだ段差をそれぞれ形戒し、該リードを
該リードの他端が前記第２チップの近傍に位置するよう
に折り曲げて、該第２チップとリードの他端をワイヤボ
ンディングし、前記第１、第２チップ及びリードのワイ
ヤボンディングした部分の近傍を外装した後に、該リー
ドの中間部分を切除して上リード及び下リードとし、該
上リードの自由端近傍を、該下リードの自由端近傍と概
略同一形状に戒形して構或する。[Detailed Description of the Invention] Summary Regarding a method for manufacturing semiconductor packages such as ICs and LSIs, the purpose of this invention is to provide an efficient method for manufacturing semiconductor packages with a high degree of integration. An IJ single frame having a plurality of leads arranged in a plane is arranged such that one end side of the leads is located near the first chip, and the first chip and one end of the leads are connected to each other using wires. bonding, form a step on the other end of the lead that is depressed toward the second chip, bend the lead so that the other end of the lead is located near the second chip, and then After wire-bonding the other ends of the chip and the lead and sheathing the vicinity of the wire-bonded parts of the first and second chips and leads, the middle part of the lead is cut off to form an upper lead and a lower lead; The vicinity of the free end of the lead is shaped into approximately the same shape as the vicinity of the free end of the lower lead.
産業上の利用分野
本発明はＩＣ，ＬＳＩ等の半導体パッケージの製造方法
に関する。INDUSTRIAL APPLICATION FIELD The present invention relates to a method for manufacturing semiconductor packages such as ICs and LSIs.
近年、コンピュータ等の高速動作性が要求される分野で
は配線パスを短くするため、あるいは、民生機器の分野
では装置を小型に仕上げるために、ＩＣＳＬＳＩ等の半
導体パッケージも高密度化、小型化が要望されている。In recent years, there has been a demand for higher density and smaller semiconductor packages such as ICSLSI in order to shorten wiring paths in fields that require high-speed operation such as computers, or to make devices smaller in the field of consumer electronics. has been done.
ＩＣを例にとれば、従来は挿入形の標準ＤＩＰパッケー
ジがほとんどであったが、上記要望に対応するために挿
入型としてはＳ − Ｄ Ｉ Ｐ （Ｓｈｒｉｎｋ−Ｄ
ＩＰ） 、Ｐ Ｇ Ａ （ＰｉｎＧｒｉｄ Ａｒｒａｙ
） 、表面実装型としてはＳ Ｏ Ｐ （ＳｍａｌｌＯ
ｕｔｌｉｎｅ Ｐａｃｋａｇｅ）、Ｑ Ｆ Ｐ （Ｑｕ
ａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）等のようにパッケー
ジは多ビン（リード）化、小型化の傾向にある。リード
フレームの加工技術としては、リードのピッチ間隔は０
．２〜０．３ｍｍと微細な加工が実現されているのに対
し、実際に採用できるビン間隔としては、挿入型ではプ
リント配線板に形或するスルーホールの加工技術の観点
から１．７８Ｍ程度であり、表面実装型については、プ
リント配線板上にハンダ付けする際のブリッジ〈短絡〉
回避の観点から、リード間ピッチは０．６叩程度となっ
ており、リードピッチ間隔の縮小による高密度化は限界
にきている状況である。このような状況下において、集
積度の高い半導体パッケージの製造方法の提供が要望さ
れている。Taking IC as an example, conventionally most standard DIP packages were insertion type, but in order to meet the above demands, S-DIP (Shrink-D
IP), PGA (PinGrid Array
), and the surface mount type is S O P (SmallO
utline Package), Q F P (Qu
There is a trend toward increasing the number of bins (leads) and downsizing of packages, such as ad flat packages. As for lead frame processing technology, the lead pitch interval is 0.
．． While fine machining of 2 to 0.3 mm has been achieved, the actual bin spacing that can be adopted is approximately 1.78 m from the viewpoint of processing technology for through-holes formed on printed wiring boards for the insertion type. Yes, for surface mount type, there is a bridge (short circuit) when soldering on the printed wiring board.
From the viewpoint of avoidance, the lead-to-lead pitch is approximately 0.6 strokes, and increasing the density by reducing the lead pitch interval is reaching its limit. Under these circumstances, there is a demand for a method of manufacturing a semiconductor package with a high degree of integration.
従来の技術
一般に、表面実装型パッケージはパッケージ側面から平
面的にあるいは段差状に折り曲げてリードを取り出して
構戊されており、リードはそのピッチ間隔を極力小さく
するとともに、パッケージの両側、あるいは、４方の側
部から取り出して多リード化に対応するようにしている
。しかし、このような構造による多リード化は限界にき
ており、このため、パッケージ側面から２段にしてリー
ドを取り出し、上段のリードと下段のリードが干渉しな
いように、その先端近傍を同一平面上に配列した構造が
採用されるようになってきた。Conventional technology Generally, a surface mount type package is constructed by taking out the leads by bending them flatly or stepwise from the side of the package. It can be taken out from one side to accommodate multiple leads. However, the ability to increase the number of leads using this structure has reached its limit, and for this reason, the leads are taken out in two stages from the side of the package, and their tips are placed on the same plane so that the upper and lower leads do not interfere with each other. The structure arranged above has come to be adopted.
このような構造の半導体パッケージの製造は、ステムの
両面にそれぞれチップ（集積回路素子）を貼設し、複数
のリードが平面的に配列され、これらリードの一部が連
結されてなるリードフレームく一般にプレスによる打ち
抜きにより成形される）を、上部チップ近傍に配置して
各リードと上部チップ間をワイヤボンディングし、同様
なリードフレームを下部チップ近傍に配置して各リード
と下部チップ間をワイヤボンディングし、これらのチッ
プと各リードのワイヤボンディングした部分の近傍を樹
脂等で外装し、上段のリードとなるべきリードフレーム
と、下段のリードとなるべきリードフレームのそれぞれ
のリード連結部を含む端都側を切断し、最後に上段及び
下段の各リードを所定の形状に折り曲げることにより製
造していた。To manufacture a semiconductor package with this structure, chips (integrated circuit elements) are pasted on both sides of the stem, a plurality of leads are arranged in a plane, and some of these leads are connected to each other to form a lead frame. A lead frame (generally formed by punching with a press) is placed near the top chip and wire bonded between each lead and the top chip, and a similar lead frame is placed near the bottom chip and wire bonded between each lead and the bottom chip. Then, the vicinity of the wire-bonded parts of these chips and each lead is covered with resin, etc., and the terminal area including the lead connection parts of the lead frame that is to become the upper lead and the lead frame that is to be the lower lead is formed. It was manufactured by cutting the sides and finally bending the upper and lower leads into a predetermined shape.
発明が解決しようとする課題
しかし、従来方法であると、１個の半導体パッケージを
製造するのに、上段のリード用及び下役のリード用の２
枚のリードフレームを用いる必要があり、製造効率及び
コストの観点から問題があった。Problems to be Solved by the Invention However, in the conventional method, two leads, one for the upper lead and one for the lower lead, are required to manufacture one semiconductor package.
It is necessary to use two lead frames, which poses problems from the viewpoint of manufacturing efficiency and cost.
本発明はこのような点に鑑みてなされたものであり、集
積度の高い半導体パッケージの効率的な製造方法の提供
を目的としている。The present invention has been made in view of these points, and an object of the present invention is to provide an efficient method for manufacturing a semiconductor package with a high degree of integration.
課題を解決するための手段及び作用
第１図（ａ）〜（ｆ）は本発明の原理を示す工程図であ
る。リードフレームは例えば、複数のり一ド４が平面的
に配列され、これらリード４の一部が連結されて構戊さ
れている。通常、各リードと連結部４Ｃはプレス打ち抜
き等により一体的に戒形される。そして、ステムｌの両
面に第１チップ２及び第２チップ３を設けておき、前記
リードフレームを、各リード４の一端が第１チップ２の
近傍に位置するように配置して（（ａ）図参照〉、第１
チップ２とリード４の一端をそれぞれワイヤボンディン
グする。次いで、リード４の他端に前記第２チップ３側
に落ち込んだ段差５をそれぞれ形戒し（（ｂ）図参照〉
、各リード４をその他端が前記第２チップ３の近傍に位
置するように折り曲げて、下部チップ３とリード４の他
端をワイヤボンディングする（（Ｃ）及び（社）図参照
）。Means and operation for solving the problem FIGS. 1(a) to 1(f) are process diagrams showing the principle of the present invention. The lead frame is constructed by, for example, having a plurality of leads 4 arranged in a plane and some of these leads 4 being connected. Usually, each lead and the connecting portion 4C are integrally formed by press punching or the like. A first chip 2 and a second chip 3 are provided on both sides of the stem l, and the lead frame is arranged so that one end of each lead 4 is located near the first chip 2 ((a) See figure>, 1st
The chip 2 and one end of the leads 4 are each wire-bonded. Next, the steps 5 falling toward the second chip 3 are shaped at the other ends of the leads 4 (see figure (b)).
, each lead 4 is bent so that the other end is located near the second chip 3, and the lower chip 3 and the other end of the lead 4 are wire-bonded (see (C) and the figure of the company).
さらに、第１チップ２、第２チップ３及びりード４のワ
イヤボンディングした部分の近傍を外装（６）Ｌ、ＩＪ
−ド４のフレームを含む中間部分を切除して上リード４
ａ及び下リード４ｂとし（（ｅ）図参照）、上リード４
ａの自由端近傍を、下り−ド４ｂの自由端近傍と概略同
一形状となるように折り曲げることにより半導体パッケ
ージを製造する（（ｆ）図参照）。Furthermore, the vicinity of the wire-bonded parts of the first chip 2, second chip 3, and lead 4 is covered with an exterior (6) L, IJ
- Cut out the middle part including the frame of lead 4 and
a and the lower lead 4b (see figure (e)), and the upper lead 4
A semiconductor package is manufactured by bending the vicinity of the free end of a to have approximately the same shape as the vicinity of the free end of the downward lead 4b (see figure (f)).
本発明方法により半導体パッケージを製造することによ
り、１枚のリードフレームを使用して、上及び下リード
の両方を形戊できるから、製造効率が高く、コストダウ
ンを図ることができる。By manufacturing a semiconductor package by the method of the present invention, both the upper and lower leads can be formed using one lead frame, resulting in high manufacturing efficiency and cost reduction.
実施例 以下本発明の実施例を図面を参照して説明する。Example Embodiments of the present invention will be described below with reference to the drawings.
第２図乃至第５図は本発明の一実施例の製造工程を説明
するための斜視図、第６図は同じく断面図、第７図は完
威した半導体パッケージを示す斜視図である。2 to 5 are perspective views for explaining the manufacturing process of an embodiment of the present invention, FIG. 6 is a sectional view, and FIG. 7 is a perspective view showing a completed semiconductor package.
まず、第２図を参照すると、１０はリードフレームであ
り、リードフレーム１０は図示の如く、フレーム１１に
複数のリード１２を所定の間隔で配列したものであり、
通常、フレーム１１及びリードｌ２はプレス打ち抜き等
により一体的に成形され、複数の半導体パッケージを連
続的に製造するために、同様の形状のものが一列に繰り
返し形成されて構威されている。１３はステムであり、
ステム１３の両面にはそれぞれチップ（集積回路素子）
１４．１５が貼設され、リードフレーム１０のフレーム
１１の一部がこのステム１３に仮固定されることにより
、各リードｌ２とチップ１４．１５が位置決めされてい
る。この状態でリードフレーム１０の各リード１２の一
端１２ａは上部チップ１４に隣接した状態となっている
。First, referring to FIG. 2, 10 is a lead frame, and as shown in the figure, the lead frame 10 is a frame 11 in which a plurality of leads 12 are arranged at predetermined intervals.
Usually, the frame 11 and the leads 12 are integrally formed by press punching or the like, and in order to continuously manufacture a plurality of semiconductor packages, similar shapes are repeatedly formed in a row. 13 is the stem;
Chips (integrated circuit elements) are installed on both sides of the stem 13.
14 and 15 are attached, and a part of the frame 11 of the lead frame 10 is temporarily fixed to this stem 13, whereby each lead l2 and the chip 14, 15 are positioned. In this state, one end 12a of each lead 12 of the lead frame 10 is adjacent to the upper chip 14.
以下、製造工程を時間の経過とともに説明する。Hereinafter, the manufacturing process will be explained over time.
ステムｌ３の上側に設けられた上部チップ１４と各リー
ド１２の一端１２ａをワイヤボンディング（１６）Ｌ、
その後プレスにより各リード１２の他端１２ｂ近傍に下
側に落ち込んだ段差を或形する。次いで、各リード１２
の他端側を折り曲げ、各リード１２の他端１２ｂを下部
チップ■５の近傍に位置せしめて、第６図の断面図に示
されているように、下部チップ１５と各リード１２の他
端１２ｂをワイヤボンディング（１７〉する。その後、
上部チップ１４、下部チップ１５及び各リ一ドｌ２のワ
イヤボンディングされた部分の近傍を樹脂等により外装
（２１）する。さらに、第３図に示されているように、
折り曲げられたリード１２の間にリード１２を支持する
ための治具１８を挿入し、回転する上側カッター１９及
び下側カッター２０でリードフレーム１０のフレーム１
１を含む中間部分１０ａを切除して第４図の状態を得る
。The upper chip 14 provided on the upper side of the stem l3 and one end 12a of each lead 12 are wire bonded (16)L,
Thereafter, a downwardly depressed step is formed near the other end 12b of each lead 12 by pressing. Then each lead 12
By bending the other end side and positioning the other end 12b of each lead 12 near the lower chip 5, the lower chip 15 and the other end of each lead 12 are bent, as shown in the cross-sectional view of FIG. 12b is wire bonded (17). Then,
The vicinity of the wire-bonded portions of the upper chip 14, the lower chip 15, and each lead 12 is covered (21) with resin or the like. Furthermore, as shown in Figure 3,
A jig 18 for supporting the lead 12 is inserted between the bent leads 12, and the rotating upper cutter 19 and lower cutter 20 cut the frame 1 of the lead frame 10.
The state shown in FIG. 4 is obtained by cutting out the intermediate portion 10a including 1.
そして、第５図に示されているように、凸状の上型２２
及びこれと嵌合する凹状の下型２３により、上リード１
２ｃをその先端が下リード１２ｄの先端の折曲部と同一
平面上に配列されるように成形する。第３図乃至第５図
においては片側のリードについてのみ示しているが、こ
れらの工程は他側のリードについても同様に実施する。Then, as shown in FIG. 5, the convex upper mold 22
The upper lead 1 is formed by the concave lower mold 23 that fits with
2c is formed so that its tip is aligned on the same plane as the bent portion of the tip of the lower lead 12d. Although only the leads on one side are shown in FIGS. 3 to 5, these steps are carried out similarly for the leads on the other side.
第７図にこれらの工程を経て製造された半導体パッケー
ジの完戊した状態の斜視図が示されている。FIG. 7 shows a perspective view of the completed semiconductor package manufactured through these steps.
本実施例によれば、半導体パッケージを１枚のリードフ
レーム１０を使用して製造することができ、従来のよう
に上リード用と下リード用の２枚のリードフレームを用
いて製造していたのに比較して、リードフレームのコス
トが安く、製造の効率を向上することができる。According to this embodiment, the semiconductor package can be manufactured using one lead frame 10, instead of the conventional manufacturing method using two lead frames, one for the upper lead and one for the lower lead. The cost of lead frames is lower than that of previous models, and manufacturing efficiency can be improved.
発明の効果
本発明方法を用いることにより、パッケージ側面から２
段にしてリードを取り出し、上段のリードと下段のリー
ドが干渉しないように、その先端部近傍を同一形状に形
戊・配列してなる半導体パッケージを、ｌ枚のリードフ
レームを使用して製造することができるから、その製造
効率が高く、安価な半導体パッケージを提供できるとい
う効果を奏する。Effects of the Invention By using the method of the present invention, two parts can be removed from the side of the package.
A semiconductor package is produced using one lead frame, in which the leads are taken out in stages, and the vicinity of their tips are shaped and arranged in the same shape so that the leads in the upper stage and the leads in the lower stage do not interfere with each other. Therefore, the manufacturing efficiency is high and it is possible to provide an inexpensive semiconductor package.
第１図は（ａ）〜（ｆ）は本発明の原理を示す工程図、
第２図乃至第５図は本発明一実施例の製造工程を説明す
るための斜視図、
第６図は同じく断面図、
第７図は完或した半導体パッケージを示す斜視図である
。
１・・・ステム、
２・・・第１チップ、
３・・・第２チップ、
４・・・リード、
４ａ・・・上リード、
４ｂ・・・下リード。In FIG. 1, (a) to (f) are process diagrams showing the principle of the present invention,
2 to 5 are perspective views for explaining the manufacturing process of an embodiment of the present invention, FIG. 6 is a sectional view, and FIG. 7 is a perspective view showing a completed semiconductor package. 1... Stem, 2... First chip, 3... Second chip, 4... Lead, 4a... Upper lead, 4b... Lower lead.
Claims (1)
（３）を設け、 複数のリード（４）が平面的に配列されてなるリードフ
レームを、該リード（４）の一端側が該第１チップ（２
）の近傍に位置するように配置して、該第１チップ（２
）とリード（４）の一端をそれぞれワイヤボンディング
し、 該リード（４）の他端に前記第２チップ（３）側に落ち
込んだ段差（５）をそれぞれ形成し、 該リード（４）を該リード（４）の他端が前記第２チッ
プ（３）の近傍に位置するように折り曲げて、該第２チ
ップ（３）とリード（４）の他端をワイヤボンディング
し、 前記第１、第２チップ（２、３）及びリード（４）のワ
イヤボンディングした部分の近傍を外装（６）した後に
、 該リード（４）の中間部分を切除して上リード（４ａ）
及び下リード（４ｂ）とし、 該上リード（４ａ）の自由端近傍を、該下リード（４ｂ
）の自由端近傍と概略同一形状に成形するようにしたこ
とを特徴とする半導体パッケージの製造方法。[Claims] A first chip (2) and a second chip (3) are provided on both sides of a stem (1), and a lead frame in which a plurality of leads (4) are arranged in a plane is connected to the leads (1). 4) one end side is the first chip (2)
), and the first chip (2
) and one end of the lead (4) are wire-bonded, a step (5) depressed toward the second chip (3) is formed at the other end of the lead (4), and the lead (4) is connected to the second chip (3). Bend the other end of the lead (4) so that it is located near the second chip (3), wire bond the second chip (3) and the other end of the lead (4), and After covering (6) the vicinity of the wire-bonded parts of the two chips (2, 3) and the leads (4), the middle part of the leads (4) is cut out to form the upper lead (4a).
and a lower lead (4b), and the vicinity of the free end of the upper lead (4a) is connected to the lower lead (4b).
) A method for manufacturing a semiconductor package, characterized in that the semiconductor package is formed into approximately the same shape as the vicinity of the free end of the semiconductor package.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24086989A JPH03104265A (en) | 1989-09-19 | 1989-09-19 | Manufacture of semiconductor package |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24086989A JPH03104265A (en) | 1989-09-19 | 1989-09-19 | Manufacture of semiconductor package |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH03104265A true JPH03104265A (en) | 1991-05-01 |
Family
ID=17065909
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24086989A Pending JPH03104265A (en) | 1989-09-19 | 1989-09-19 | Manufacture of semiconductor package |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH03104265A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0555446A (en) * | 1991-08-26 | 1993-03-05 | Matsushita Electron Corp | Semiconductor device |
| JPH05315523A (en) * | 1991-05-17 | 1993-11-26 | Fujitsu Ltd | Semiconductor device |
| US5574310A (en) * | 1991-05-17 | 1996-11-12 | Fujitsu Limited | Semiconductor package for surface mounting with reinforcing members on support legs |
| US5831332A (en) * | 1991-05-17 | 1998-11-03 | Fujitsu Limited | Semiconductor package for surface mounting |
-
1989
- 1989-09-19 JP JP24086989A patent/JPH03104265A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05315523A (en) * | 1991-05-17 | 1993-11-26 | Fujitsu Ltd | Semiconductor device |
| US5574310A (en) * | 1991-05-17 | 1996-11-12 | Fujitsu Limited | Semiconductor package for surface mounting with reinforcing members on support legs |
| US5831332A (en) * | 1991-05-17 | 1998-11-03 | Fujitsu Limited | Semiconductor package for surface mounting |
| US5861669A (en) * | 1991-05-17 | 1999-01-19 | Fujitsu Limited | Semiconductor package for surface mounting |
| JPH0555446A (en) * | 1991-08-26 | 1993-03-05 | Matsushita Electron Corp | Semiconductor device |
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