JPH0645497A - Semiconductor device and manufacture thereof - Google Patents

Semiconductor device and manufacture thereof

Info

Publication number
JPH0645497A
JPH0645497A JP19441092A JP19441092A JPH0645497A JP H0645497 A JPH0645497 A JP H0645497A JP 19441092 A JP19441092 A JP 19441092A JP 19441092 A JP19441092 A JP 19441092A JP H0645497 A JPH0645497 A JP H0645497A
Authority
JP
Japan
Prior art keywords
leads
lead
inner leads
lead frame
narrow pitch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19441092A
Other languages
Japanese (ja)
Inventor
Eiji Hagimoto
英二 萩本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP19441092A priority Critical patent/JPH0645497A/en
Publication of JPH0645497A publication Critical patent/JPH0645497A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Abstract

PURPOSE:To realize lead frames of a narrow pitch by providing upper and lower steps in a zigzag manner by a space of at least a thickness of a lead plate at its end in order to obtain an insulating space of adjacent inner leads of the frames. CONSTITUTION:Openings 10 of parts B, C are punched by pressing, and then ends 11 of inner leads of a part A are cut by shearing or laser beam machining. Thus, the inner leads are separated. Then, a plastically processed part 12 is bent by plastically deforming by a press to form an oblique part 9 to a horizontal plane 8 of leads, ends of the leads are alternately changed in different heights, and disposed in a zigzag manner. As a result, the inner leads an be disposed at narrow pitch. Even if the leads are brought into contact when the leads are resin-sealed, a sufficient insulation interval can be obtained at upper and lower rows, and hence an irregular standard of inner lead positions can be alleviated.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、半導体装置およびその
製造方法に関し、特に半導体チップのボンディングパッ
ドピッチが狭く比較的小チップサイズで多ピンの外部リ
ードを必要とする場合に効果の大きい半導体装置および
その製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly to a semiconductor device having a narrow bonding pad pitch of a semiconductor chip and a relatively small chip size and requiring a large number of external leads. And a manufacturing method thereof.

【0002】[0002]

【従来の技術】従来、半導体装置用リードフレームは、
プレス法又はエッチング法によって作られている。プレ
ス法は、製造コストが安いので、大量生産するリードフ
レーム用の製造方法として多用されている。しかし、半
導体チップの製造技術が進歩してチップの配線ルールが
1ミクロンを下回る様になると、そのチップサイズは、
小さくなり、ボンディングパッドのピッチを小さくしな
いとチップサイズを縮小しかつ歩留を向上する手法の効
果は十分に得られ無くなって来た。これに対応するリー
ドフレームの内部リードは、狭ピッチを実現しなければ
ならなくなり、細長くなってきた。
2. Description of the Related Art Conventionally, lead frames for semiconductor devices are
It is made by pressing or etching. Since the press method has a low manufacturing cost, it is widely used as a manufacturing method for mass-produced lead frames. However, as semiconductor chip manufacturing technology advances and the chip wiring rules fall below 1 micron, the chip size becomes
If the pitch of the bonding pads is not reduced, the effect of the technique for reducing the chip size and improving the yield cannot be sufficiently obtained. Corresponding to this, the inner lead of the lead frame has become slender because it is necessary to realize a narrow pitch.

【0003】現状のリードフレームの製造能力は、複数
の金型を並べリードを部分的にプレスしていく順送り方
式のプレス法では、板厚150ミクロンメートルでリー
ド幅120ミクロンメートル/スペース120ミクロン
メートルの240ミクロンメートルのピッチが可能であ
る。エッチング法の場合、リード幅110ミクロンメー
トル/スペース110ミクロンメートルの220ミクロ
ンメートルのピッチが可能である。これに対してチップ
側パッドピッチは130〜150ミクロンメートルであ
り、最近のものでは110ミクロンメートルの狭ピッチ
も検討されている。上記スペーシングを考えると内部リ
ードをアイランド周囲近傍にまで延ばしてワイヤリング
することができなくなってきたことが分かる。
The current lead frame production capacity is that in a progressive feed method in which a plurality of molds are arranged and the leads are partially pressed, a plate thickness of 150 μm and a lead width of 120 μm / space 120 μm. A pitch of 240 microns is possible. For the etching method, a 220 micron pitch with 110 micron lead width / 110 micron space is possible. On the other hand, the pad pitch on the chip side is 130 to 150 μm, and recently, a narrow pitch of 110 μm has been considered. Considering the above spacing, it can be seen that it has become impossible to extend the inner leads to the vicinity of the island periphery for wiring.

【0004】[0004]

【発明が解決しようとする課題】前記狭ピッチを実現す
るべくプレス金型のパンチ幅を狭くしていくと強度及び
製造上の制約から所期の狭ピッチ用のプレス金型が製造
できなくなるとともに打ち抜くことができなくなる。現
状技術レベルではリードフレームの板厚の80%程度が
限度となる。
If the punch width of the press die is narrowed in order to realize the narrow pitch, the desired press die for narrow pitch cannot be manufactured due to the strength and manufacturing restrictions. It becomes impossible to punch. At the current level of technology, the limit is about 80% of the thickness of the lead frame.

【0005】これはエッチング法でも同様でエッチング
レートの関係からリードフレームの板厚より狭いピッチ
ではエッチングが著しく困難になる。
This is also the case with the etching method. Due to the etching rate, etching becomes extremely difficult at a pitch narrower than the thickness of the lead frame.

【0006】したがって、この従来の製造方法であるプ
レス法を採用しようと思うと内部リードは十分アイラン
ド周囲近傍にまで近づけることができずボンディングワ
イヤーの長さで補うことが必要となる。このワイヤー長
が長いとワイヤー自身の捩じ等の変形のみならず樹脂封
止の際に充填される樹脂に流されショート、エッジタッ
チ等を生じ品質問題となる。
Therefore, if the pressing method, which is the conventional manufacturing method, is adopted, the internal leads cannot be brought sufficiently close to the vicinity of the island, and the length of the bonding wire must be compensated for. If the wire length is long, not only the deformation of the wire itself such as twisting but also the resin filled at the time of resin sealing causes a short circuit, an edge touch, etc., which causes a quality problem.

【0007】リードフレームの板厚を薄くする方法を採
用すると、リードフレームはできるが完成した製品の外
部リードの強度が十分ではなく、リード曲がり、平坦度
の規格を満たすことができない。
When the method of reducing the plate thickness of the lead frame is adopted, the lead frame can be formed, but the strength of the external lead of the completed product is not sufficient, and the lead bending and flatness cannot be satisfied.

【0008】本発明の目的はプレス加工法のような現行
技術をリファインして狭ピッチのリードフレームを実現
し、多ピン化傾向に対応することにある。
An object of the present invention is to refine a current technology such as a press working method to realize a lead frame with a narrow pitch and to cope with the tendency of increasing the number of pins.

【0009】[0009]

【課題を解決するための手段】本発明のリードフレーム
は互いに隣接する内部リードが絶縁間隔を確保するため
に、その先端部分において少なくともリード板厚以上の
スペースで上下に段差を設け千鳥配置している。このた
めプレス加工法ではプレス金型のポンチ幅は内部リード
の幅と同じに取ることができるため内部リードピッチも
リード幅と同等寸法をとることができる。
The lead frame of the present invention has a zigzag arrangement in which the inner leads adjacent to each other are provided with a step at the top and bottom thereof at a space of at least the lead plate thickness in order to secure an insulation interval. There is. Therefore, in the press working method, the punch width of the press die can be set to be the same as the width of the internal leads, and thus the internal lead pitch can also be set to the same dimension as the lead width.

【0010】プレス加工の場合、150ミクロンメート
ルの板厚であると現行の量産技術レベルからするとピッ
チはリード幅120/スペース120の240ミクロン
メートルが可能であるからその1/2の120ミクロン
メートルピッチが十分可能となる。
In the case of press working, if the thickness of the plate is 150 μm, the pitch can be 120 μm of lead width / 240 of space 120 from the current mass production technology level, so the pitch is 120 μm of 1/2 of that. Is fully possible.

【0011】[0011]

【実施例】図1は、本発明の一実施例の斜視図である。
半導体チップ1をリードフレーム2のアイランド4に搭
載し各部の相対位置関係を示す。(封止に用いた状態は
透明にし、図示しない。)内部リードのボンディングさ
れるべきA部と各リードの間隔を広げて行くB部はせん
断によって各リードを分離し、金型で打ち抜くに十分な
間隔のとれるC部が有り、これらは従来と同様金型で打
ち抜いて分離する。各リードは外部リードの方へつなが
るがこの部分は従来技術で対応できるので図示を省略す
る。
1 is a perspective view of an embodiment of the present invention.
The semiconductor chip 1 is mounted on the island 4 of the lead frame 2 and the relative positional relationship of each part is shown. (The state used for sealing is transparent and not shown.) A part of the internal lead to be bonded and the B part that widens the space between each lead are separated by shearing and are sufficient for punching with a die. There is a C portion that can be spaced at various intervals, and these are punched and separated with a mold as in the conventional case. Although each lead is connected to the external lead, this portion can be dealt with by a conventional technique, so that the illustration is omitted.

【0012】また、上下への曲げについては2つの様式
を例示する。アイランド4をリードフレームの水平面8
に対して下方にシフトさせてディンプル加工を施すと同
時にインナーリードの一部9をたがいちがいに1本おき
に下方に曲げてシフトする様式(図2(a))と、それ
と逆にインナーリードの一部9をたがいちがいに1本お
きに下方に曲げてシフトする様式(図2(b))とがあ
る。
[0012] Two modes are exemplified for the up and down bending. Island 4 to lead frame horizontal surface 8
The inner lead 9 is bent downward every other piece at the same time as the inner lead 9 is shifted and the dimple processing is performed (FIG. 2 (a)). There is a mode (FIG. 2 (b)) in which every other part of the part 9 is bent and shifted every other part.

【0013】ここでリードフレームの製造方法の一例を
述べる。リードフレーム2の外形は、まずC部のリード
フレーム間をプレス加工で打ち抜き、続いてA,B部の
リードフレーム間をせん断加工にて分離する。この時同
時にリードを1本おきにたがいちがいにシフトしたりア
イランドをシフトする曲げ加工を施しても良いし、別工
程でこの曲げ加工を施しても良い。めっき加工前に前処
理工程としてエッチング工程があり、メッキ面を洗浄に
する。この時エッチングを過多ぎみに施してせん断した
側面をエッチングする。こうすることによって相隣接す
るリードがバリ等によって絡まり組立工程内で問題を起
こすことがない。A,B部の加工にレーザー光線のよう
な高エネルギー密度の光線を使用すると、切りしろが少
々できるので上記のような絡まりがなく、エッチングで
リードフレームの面を平滑にできる。
Here, an example of a method for manufacturing a lead frame will be described. Regarding the outer shape of the lead frame 2, first, the lead frames of the C portion are punched by press working, and subsequently, the lead frames of the A and B portions are separated by shearing working. At this time, at the same time, every other lead may be bent to shift each other or the islands may be bent, or this bending may be performed in another step. Before plating, there is an etching process as a pretreatment process to clean the plated surface. At this time, etching is performed excessively to etch the sheared side surface. By doing so, adjacent leads do not get entangled by burrs or the like and cause a problem in the assembly process. When a light beam having a high energy density such as a laser beam is used for the processing of the A and B portions, the cutting margin can be slightly formed, so that the above-mentioned entanglement does not occur and the surface of the lead frame can be smoothed by etching.

【0014】ボンディングの際に内部リードをリード押
さえ治具(図示せず。)にて弾性変形させて固定するこ
とによって、全ての内部リードを同一平面上にそろえて
ボンディングすることができる。ボンディング後リード
押さえ治具を離してリードを開放すればリード材料の弾
性で曲げ形状を回復でき、隣りどうしのリードの短絡を
防ぐことができる。
When the internal leads are elastically deformed and fixed by a lead pressing jig (not shown) at the time of bonding, all the internal leads can be aligned and bonded on the same plane. After bonding, if the lead pressing jig is released and the leads are opened, the bending shape can be restored by the elasticity of the lead material, and it is possible to prevent a short circuit between adjacent leads.

【0015】内部リードの一部の曲げ加工を施すとその
リード9の全長は詰まるので必然的に曲げたリード9と
曲げなかったリードの先端は交互に長さの異なる形態と
なるので、ボンディングしたワイヤ3どうしが接触する
ことはない。なお弾性変形後のリードどうしの前後の引
き下がりが十分でない場合は、ボンディングは、各ピン
毎に千鳥状に行なうこともできる。
When a part of the inner lead is bent, the entire length of the lead 9 is clogged. Therefore, the bent lead 9 and the tip of the unbent lead inevitably have different lengths. The wires 3 do not contact each other. If the leads after elastic deformation are not sufficiently pulled back and forth, the bonding can be performed in a staggered manner for each pin.

【0016】図1には一部ボンディングしたワイヤー3
を図示する。
FIG. 1 shows a partially bonded wire 3
Is illustrated.

【0017】また、ワイヤーボンディング可能な内部リ
ード幅は100ミクロンメートルであり、チップ側のパ
ッドピッチが同じく100ミクロンメートルであればチ
ップに沿って傾くことなくボンディングできワイヤー間
の接触の可能性を最低限にすることができる。
Further, the width of the inner lead capable of wire bonding is 100 μm, and if the pad pitch on the chip side is also 100 μm, it is possible to bond without tilting along the chip and the possibility of contact between wires is minimized. Can be limited.

【0018】リードフレーム材料は、Fe/Ni合金や
銅合金が使用でき、弾性金属材料であれば基本的には制
約はない。また、メッキ金属は、従来知られている金属
が使用できる。
As the lead frame material, Fe / Ni alloy or copper alloy can be used, and basically there is no limitation as long as it is an elastic metal material. Further, as the plating metal, a conventionally known metal can be used.

【0019】図3は、本発明の他の実施例のリードの平
面図である。まず図3(a)のようにB部およびC部の
開孔10をプレス加工で打ち抜き、次にA部の内部リー
ド先端の間11をせん断加工またはレーザビーム加工で
切断する。これにより各内部リードが分離される。次に
プレスによるそ性変形加工により、図3(b),
(c),(d)のように、そ性加工部12を曲げてリー
ドの水平面8に対する傾斜面9を形成してリード先端を
たがえ違いに高さを変える。つまり先端部の配置は、図
3(d)のように千鳥配置になる。
FIG. 3 is a plan view of a lead according to another embodiment of the present invention. First, as shown in FIG. 3A, the openings 10 in the B and C portions are punched out by press working, and then the gap 11 between the inner lead tips of the A portion is cut by shearing or laser beam working. This separates each internal lead. Next, as shown in FIG.
As shown in (c) and (d), the textured portion 12 is bent to form an inclined surface 9 with respect to the horizontal surface 8 of the lead, and the height of the lead tip is changed by misalignment. That is, the arrangement of the tips is staggered as shown in FIG.

【0020】図4は、中空タイプのさらに他の実施例を
示す。キャップ2、ベース7の基材にアルミナセラミッ
クスを用い接着剤5としてAgペーストでベース7にリ
ードフレーム2をマウントし、低融点ガラス13ないし
は樹脂で封止する。短納期での対応や初期特性の評価用
に有効である。
FIG. 4 shows another embodiment of the hollow type. The lead frame 2 is mounted on the base 7 with Ag paste as the adhesive 5 using alumina ceramics as the base material of the cap 2 and the base 7, and is sealed with the low melting point glass 13 or resin. It is effective for quick delivery and evaluation of initial characteristics.

【0021】なお、一実施例や他の実施例では、放熱特
性を向上させるためアイランド4の裏面に放熱用の部材
を接着して樹脂封止しても良い。
In one embodiment or another embodiment, a heat dissipation member may be adhered to the back surface of the island 4 for resin sealing in order to improve heat dissipation characteristics.

【0022】[0022]

【発明の効果】以上、説明したように本発明は内部リー
ドを狭ピッチにできるため従来構造では小チップの場合
には内部リードが十分内部まで届かず長ワイヤーとなっ
てしまうものが従来の設計基準でワイヤリングできる。
また、リードが樹脂封入の際に左右に触れても上下の各
列では十分な絶縁間隔が確保できるので内部リード位置
の不揃い規格が緩くできリードを樹脂テープで固定する
テーピングのようなコストアップとなる構造を採用する
ピン数を押し上げることができるという効果を有する。
As described above, according to the present invention, since the internal leads can have a narrow pitch, in the conventional structure, in the case of a small chip, the internal leads do not reach the inside sufficiently and become a long wire. Wiring can be done by reference.
In addition, even if the leads touch the left and right during resin encapsulation, a sufficient insulation interval can be secured in the upper and lower rows, so that the standard of uneven internal lead positions can be loosened and the cost increase such as taping to fix the leads with resin tape is possible. This has the effect of increasing the number of pins adopting the above structure.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の半導体チップの一実施例の斜視図であ
る。
FIG. 1 is a perspective view of an embodiment of a semiconductor chip of the present invention.

【図2】本発明の半導体チップの一実施例の断面図であ
る。
FIG. 2 is a sectional view of an embodiment of a semiconductor chip of the present invention.

【図3】本発明の他の実施例の製造工程順平面図
(a),(b)と、平面図(b)の切断線A−A′での
断面図(c)と、内部リード先端の千鳥配列の図3
(d)である。
3A and 3B are plan views of manufacturing steps according to another embodiment of the present invention, and FIG. 3C is a sectional view taken along the line AA ′ in FIG. Figure 3 of the staggered array
It is (d).

【図4】本発明のさらに他の実施例の断面図である。FIG. 4 is a sectional view of still another embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1 半導体チップ 2 リードフレーム 3 ボンディングワイヤー 4 アイランド 5 接着剤 6 キャップ 7 ベース 8 水平面 9 傾斜面 10 開孔 11 間 12 そ性加工部 13 低融点ガラス DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Lead frame 3 Bonding wire 4 Island 5 Adhesive 6 Cap 7 Base 8 Horizontal surface 9 Sloping surface 10 Opening hole 11 Between 12 Soft processing part 13 Low melting point glass

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 リードフレームに設けられた互いに相隣
接する内部リードどうしの先端部分が上下に千鳥状に離
間配置されていることを特徴とする半導体装置。
1. A semiconductor device, wherein tip portions of inner leads adjacent to each other provided on a lead frame are vertically arranged in a zigzag pattern.
【請求項2】 リードフレームの内部リードの先端部分
がせん断加工で分離され前記内部リードの根本が開孔加
工されていることを特徴とする半導体装置の製造方法。
2. A method of manufacturing a semiconductor device, characterized in that the leading end portions of the inner leads of the lead frame are separated by shearing and the roots of the inner leads are perforated.
JP19441092A 1992-07-22 1992-07-22 Semiconductor device and manufacture thereof Pending JPH0645497A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19441092A JPH0645497A (en) 1992-07-22 1992-07-22 Semiconductor device and manufacture thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19441092A JPH0645497A (en) 1992-07-22 1992-07-22 Semiconductor device and manufacture thereof

Publications (1)

Publication Number Publication Date
JPH0645497A true JPH0645497A (en) 1994-02-18

Family

ID=16324142

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19441092A Pending JPH0645497A (en) 1992-07-22 1992-07-22 Semiconductor device and manufacture thereof

Country Status (1)

Country Link
JP (1) JPH0645497A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724070B2 (en) * 1997-12-18 2004-04-20 Texas Instruments Incorporated Fine pitch lead frame
KR100546696B1 (en) * 2000-10-11 2006-01-26 앰코 테크놀로지 코리아 주식회사 method for forming lead frame for fabrication of semiconductorpackage
JP2008124228A (en) * 2006-11-13 2008-05-29 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
US8049325B2 (en) 2008-11-25 2011-11-01 Samsung Electronics Co., Ltd. Integrated circuit devices having printed circuit boards therein with staggered bond fingers that support improved electrical isolation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159752A (en) * 1988-12-13 1990-06-19 Nec Corp Lead frame

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159752A (en) * 1988-12-13 1990-06-19 Nec Corp Lead frame

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6724070B2 (en) * 1997-12-18 2004-04-20 Texas Instruments Incorporated Fine pitch lead frame
KR100546696B1 (en) * 2000-10-11 2006-01-26 앰코 테크놀로지 코리아 주식회사 method for forming lead frame for fabrication of semiconductorpackage
JP2008124228A (en) * 2006-11-13 2008-05-29 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
US8049325B2 (en) 2008-11-25 2011-11-01 Samsung Electronics Co., Ltd. Integrated circuit devices having printed circuit boards therein with staggered bond fingers that support improved electrical isolation

Similar Documents

Publication Publication Date Title
US6674154B2 (en) Lead frame with multiple rows of external terminals
US6710430B2 (en) Resin-encapsulated semiconductor device and method for manufacturing the same
US7132315B2 (en) Leadframe, plastic-encapsulated semiconductor device, and method for fabricating the same
US7019388B2 (en) Semiconductor device
KR100564006B1 (en) Terminal land frame and method for manufacturing the same, and resin sealed semiconductor device and method for manufacturing the same
JPH02502323A (en) Support assembly for integrated circuits
JP2001077274A (en) Lead frame and manufacture of resin-sealed semiconductor device using the same
US20030178723A1 (en) Semiconductor device and method of manufacturing the same
JP4243270B2 (en) Manufacturing method of semiconductor device
JPH0645497A (en) Semiconductor device and manufacture thereof
JP3921880B2 (en) Manufacturing method of resin-encapsulated semiconductor device
JPH10270623A (en) Lead frame for ball grid array, semiconductor device using the same and manufacture thereof
US20060049508A1 (en) Semiconductor device, lead frame, and methods for manufacturing the same
JP4248528B2 (en) Lead frame and resin-sealed semiconductor device manufacturing method using the lead frame
JP3921885B2 (en) Manufacturing method of resin-encapsulated semiconductor device
JP3699966B2 (en) Lead frame, resin-encapsulated semiconductor device and manufacturing method thereof
JP3578236B2 (en) Manufacturing method of chip type semiconductor device
JP4266429B2 (en) Resin-sealed semiconductor device and manufacturing method thereof
JP3890822B2 (en) Manufacturing method of resin-encapsulated semiconductor device
JP3422276B2 (en) Resin-sealed semiconductor device and method of manufacturing the same
JP3928286B2 (en) Manufacturing method of resin-encapsulated semiconductor device
JP2002026192A (en) Lead frame
JP2001077275A (en) Lead frame and manufacture of resin-sealed semiconductor device using the same
JPH06350013A (en) Lead frame, semiconductor device and manufacture of semiconductor device
JP3449265B2 (en) Method for manufacturing resin-encapsulated semiconductor device

Legal Events

Date Code Title Description
A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 19980714