JP2001135671A - Method for automatic layout of pad cells - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the optimum layout of pad cells and the optimum wiring off the pad cells and butter cells, independently of the from of a lead frame. SOLUTION: In order to layout pad cells 13 along each side of an IC chip 12, a pad cell is positioned on the basis of an angle of a bonding wire 36 to be connected with each of the pad cells 13 which angle is made to each of the sides of the chip 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for automatically arranging pad cells in a layout process in VLSI design.

[0002]

2. Description of the Related Art With the advancement of VLSI miniaturization technology and multifunctional applications, circuits mounted on IC chips have become
Is growing. However, the number of inputs and outputs for connection to the outside of the IC chip is limited by the shape of the IC chip. A large number of connection pad cells are arranged around the VLSI chip, and are connected to an external drive circuit and the like via a lead frame. Each pad cell and the lead frame are connected to each other by a bonding wire.

FIG. 10 is a plan view of an IC. An integrated circuit is formed at the center of the square IC chip 12. The lead frame 35 is provided around the IC chip 12.
Are provided radially with respect to the IC chip 12.
Pad cells 13 are arranged on the IC chip 12 in a row along each side. Further, between the central portion where the integrated circuit is provided and the row of the pad cells 13, I
O-buffers 15a are arranged respectively.

The pad cell 13 is much larger than the internal circuit, and is arranged on the IC chip 12.
The number 3 is limited by the size of the IC chip 12 and also by the accuracy of a wire bonding apparatus for connecting the pad cell 13 and the lead frame 35 with the bonding wires 36. In any case, a signal to be extracted to the outside of the IC chip 12 and a signal to be input to the inside are always performed via the pad cells 13, so it is important to optimally arrange many pad cells 13 of the IC chip 12.

In this case, considering the wire bonding between the lead frame 35 and each pad cell 13 provided on the IC chip 12, the pad cell 13 existing near the corner of the IC chip 12 and the pad cell 13 existing at the center of one side of the IC chip 12 are considered. In the pad cell 13, the length of the bonding wire 36 connected from the vicinity of the corner of the IC chip 12 to the lead frame 35 tends to be longer than that of the pad cell 13 arranged at the center of one side.

As described above, when the bonding wire 36 becomes longer, the parasitic inductance of the bonding wire 36 increases, and the bonding wire 3
6 is also a problem.

[0007]

When the mounting accuracy of the IC chip 12 is considered, the buffer cell 15 and the pad cell 13
The distance between a pair of adjacent pad cells 13 in the vicinity of the corner of the IC chip 12 which is rectangular in the layout model in which the IC chip 12 is separated is made larger than the distance between the pair of pad cells 13 in the center of the side of the IC chip 12. Thus, the problem of physical contact between the bonding wires 36 can be avoided. Further, the distance between the pair of adjacent pad cells 13 can be determined based on the angle of the bonding wire 36 to one side of the IC chip 12, and the bonding wire connected to the pad cell 13 near the corner of the IC chip 12 can be determined. The length of the bonding wire 36 can be quantitatively determined so that the difference from the length of the bonding wire 36 connected to the pad cell 13 arranged at the center of one side of the IC chip 12 is reduced. That is, the angle of the bonding wire 36 with respect to the side of the IC chip 12 increases from the center of each side of the IC chip 12 to each corner, and accordingly, the bonding wire 36
What is necessary is just to increase the inclination angle with respect to one side of the C chip 12.

However, when determining the position of the pad cell 13, the shape of the lead frame 35 must be determined. For this reason, when the user uses a predetermined package (that is, a predetermined lead frame 35), each pad cell 13 must be arranged corresponding to the lead frame 35. Is not easy.

An object of the present invention is to solve such a problem. An object of the present invention is to provide an automatic arrangement method for realizing an optimum arrangement of pad cells and an optimum wiring between pad cells and buffer cells regardless of the shape of a lead frame. To provide.

[0010]

SUMMARY OF THE INVENTION A method of automatically arranging pad cells according to the present invention is a method of arranging pad cells along each side of an IC chip, wherein each pad cell has a bonding wire connected to each pad cell. It is characterized in that the pad cell is positioned based on the angle with respect to the side.

Further, the pad cell determines a connection position between a buffer cell arranged on the IC chip and a connection component connected to the buffer cell so that a wiring resistance with the connection component is minimized.

In addition, a bonding wire connected to the pad cell is connected to the IC chip by using an angle-dependent function using a variable as an angle between a straight line connecting the pad cell and the center of the IC chip and one side of the IC chip. Calculate the angle that forms one side of the chip.

Further, the arrangement interval of the pad cells is increased near the corner of the IC chip, and the inclination angle of the bonding wire with respect to one side of the IC chip is increased.

Further, the pad cells are respectively arranged at the corners and the center of each side of the IC chip, and after the pad cells are sequentially arranged from the center of each side of the IC chip toward each corner, The adjustment of the pad cells sequentially arranged from the pad cells near the corners of each side of the IC chip toward the center is performed.

[0015]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows a pad cell 1 of the present invention.
FIG. 11 is a plan view showing an example of a layout model of the IC chip 12 used in the automatic placement method 3; The square IC chip 12 has an internal core region 11 in which logic cells are arranged in a square concentric region in the center. IC chip 1 along each side of internal core region 11
2 has a number of buffer cells 15 at the side edges.
Each of the buffers 15a is provided. In each IO buffer 15a, buffer cells 15 that are each elongated in the direction orthogonal to one side of the IC chip 12 adjacent to the IO buffer 15a are arranged closely in the horizontal direction. The thickness of each buffer cell 15 is substantially equal, and their positions and directions are fixed. A pad cell arranging area 20 is formed between each buffer cell 15 and one side of the IC chip 12, and a plurality of pad cells 13 are arranged in the pad cell arranging area 20 along one side of the IC chip 12. The shape of each pad cell 13 and each buffer cell 15 is rectangular and the size is appropriately set.
Each pad cell 13 is connected to each buffer cell 15 by a connection component 14.

FIG. 2 is an enlarged view of one buffer cell 15. Each of the buffer cells 15 has an elongated rectangular shape extending between the internal core region 11 and each pad cell 13, and is electrically connected to the internal core region 11 by a signal terminal 16. Further, on each side of the buffer cell 15 in the longitudinal direction, a pair of power supply surface terminals 17 and a pair of ground surface terminals 18 respectively connected to the adjacent buffer cells 15 are provided. The pad cell 13
A pad connection surface terminal 19 is provided on the side opposite to. The pad connection surface terminal 19 and the pad cell 13 are electrically connected by the connection component 14. Then, each of the pad cells 13 is wire-bonded to the leading end of the lead frame 35 disposed around the IC chip 12 and the bonding wire 36. In such a layout model, the pad cells 13 are arranged by the automatic arrangement method of the present invention.

FIG. 3 is a flowchart showing the processing contents of the method for automatically arranging pad cells according to the present invention. Pad cell 1
The arrangement processing of No. 3 is performed independently on each side of the IC chip 12, but the following description will be made by taking one side of the lower side as an example.

First, a process of arranging a special pad cell 13a arranged near the corner of the IC chip 12 is performed.
(Step 0; see FIG. 3). That is, the IO buffer 15
A special pad cell 13a shown in FIGS. 4A and 4B is arranged corresponding to the buffer cell 15 located at the outermost position in FIG.

Each special buffer cell 13a is arranged outside each outermost buffer cell 15 so as to be connected to the outermost buffer cell 15 by a connection component 14 bent at a right angle. By arranging the special pad cells 13a on both sides in this manner, the pad cell allocable area 20 is determined.

FIG. 5 is an explanatory view showing a specific example when the arrangement of each pad cell 13 is determined by the pad cell automatic arrangement method of the present invention, and is formed by a straight line connecting the center of the IC chip 12 and the center of each pad cell 13. And the distance between adjacent pad cells 13 (space). When positioning each pad cell 13, as initial input items, the layout information of the buffer cell 15 whose absolute position is determined, the wire bonding angle dependent constraint information of the bonding wire connected to each pad cell 13, the IC chip 12. Are given in the vicinity of.

In FIG. 5, when a line passing through the center O of the IC chip 12 and parallel to the lower side is a reference line 28 and a line passing through the center O of the IC chip 12 and perpendicular to the lower side is a reference line 29, the reference line 28 and the reference line The angle between the reference line 28 and the straight line connecting the center O of the IC chip 12 and the center of any four pad cells 13 is A1de.
When gree, A2 degree, A3 degree, and A4 degree are set, the relationship between the angle and the distance between arbitrary pads is determined as shown in the table showing the pad angle dependency.

That is, when the pad-to-pad angle is 90-A1 degree and A1-A2 degree, all the pads located between these angles have pad intervals of Pad_space1 and Pad_space1, respectively.
_Space2. Pad angle A4-0deg
ree is the pad cell 13 arranged inside one of the special pad cells 13a connected to the outermost buffer cell 15.
Is an angle formed by a reference line 28 and a straight line connecting the center of the IC chip 12 and the center O of the IC chip 12. By using the special pad cell 13a, the spacing between pads near the corner of the IC chip 12 can be increased, and the angle dependency of the bonding wire 36 by the pad cell 13 during wire bonding can be reduced.

Based on such a relationship, the pad cell 1
3 is performed (Step 1; see FIG. 3).
In this process, first, as shown in FIG. 6, the IC cell 12 is placed at the center of the pad cell arrangement region 20 along the side of the IC chip 12.
A pair of pad cells 13 are arranged along a vertical reference line 29 passing through the center of the chip 12. Then, for each of the arranged pad cells 13, the angle of the bonding wire 36 connecting each pad cell 13 to the lead frame 35 with respect to one side of the IC chip 12 can be determined without actually connecting the bonding wire. An angle-dependent function is obtained based on an angle formed by a straight line connecting the center and the center of each pad cell 13 and one side of the IC chip 12, and each pad cell 13 is moved from the center of the IC chip 12 by the angle-dependent function. They are arranged sequentially toward the outside. This processing is sequentially performed from the center of the IC chip 12 to the outside based on the minimum design rule so that the adjacent pad cells 13 do not overlap the special pad cells 13a. Pp1 to pp4 shown in FIG. 6 represent inter-pad spacing, and the arrangement of the pad cells 13 is such that the inter-pad spacing 24 increases from the center of the IC chip 12 to the outside. The processing procedure will be specifically described. 1-1) The initial arrangement of the pad cells 13 is performed from the center of the lower side of the IC chip 12. One or two pad cells are arranged in the center pad cell arranging area 20 on the lower side of the IC chip 12 (the arranged pad cells are set to Pi: i = 0).

1-2) Calculate the placeable coordinates Xp _{i + 1} for the pad cell Pi. The calculation of the arrangeable coordinates at that time is performed by the following equation. _{Angle cal = D dist (Xp i} ) × atan (Xp i, Height chip / 2) ··· (1) Xp i + 1 = Xp i + Dist - func (Angle cal) ··· (2) where · D _dist (X) is an angle-dependent function, as shown in FIG.
_dist (X) shows the maximum value at the center of the arrangement of the pad cells 13 and becomes smaller toward the outside (both ends). Atan (X) is a function representing an arc tangent. Dist _- func (Angle _cal ) is a function that defines the distance between pad cells for a certain angle.

1-3) The pad cell 13 is placed at the coordinates Xp _{i + 1} that can be arranged.
Is arranged, if the connection component 14 of the special pad cell 13a and the pad cell 13 adjacent to the special pad cell 13a satisfy the minimum design rule, the pad cell 13 is arranged at the arrangeable coordinates. When the pad cell 13 is arranged, i ← i + 1 is set thereon. If the minimum design rule is not satisfied, the placement processing ends at that point. This operation is performed simultaneously in the positive and negative directions of the X coordinate, that is, from the center of the lower side toward each corner. Finally, i at the point in time when the processing that satisfies the minimum design rule with the connection component 14 of the special pad cell 13a is completed is set to N.

When the processing of arranging all the pad cells 13 is completed, the processing of improving the arrangement of the arranged pad cells 13 is performed (Step 2; see FIG. 3). In this process, as shown in FIG. 7, among the pad cells 13 arranged in Step 1, the N cells arranged inside one of the special pad cells 13 a connected to the outermost buffer cell 15.
Starting from the first pad cell 13, the pad cell 13 is arranged toward the center of the pad cell 13 arrangement in the pad cell arrangement region 20 arranged along the side of the IC chip 12.
Are sequentially performed, and similarly to Step 1, the arrangement position of each pad cell 13 is calculated using an angle-dependent function, and the arrangement position of each pad cell 13 is improved (fine adjustment).
FIG. 7 shows a specific example of this. As a result, the arrangement positions of the pad cells 13 are dispersed, and wire bonding at the center of the pad cell arrangement region 20 is facilitated. The processing procedure will be specifically described.

2-1) The pad cell 13 closest to the special pad cell 13a is moved toward the center of one side of the IC chip 12 to an arrangement position satisfying the minimum design rule. The pad cell at this time Pi (i = N), the coordinates and Xp _{i (i} = N).

2-2) Calculate the placeable coordinates Xp _i-1 for the pad cell Pi. The calculation of the arrangeable coordinates at that time is performed by the following equation. _{Angle cal = D dist (Xp i} ) × atan (Xp i, Height chip / 2) ··· (3) Xp i-1 = Xp i -Dist - func (Angle cal) ··· (4) where, D _dist (X), atan (X) and Dist _- func
(Angle _cal ) is a function defined in Step 1.

[0029] 2-3) pad cells on the arrangement can coordinate Xp _i-1 Pi-
Place one. Hereinafter, the same processing is sequentially performed, and the processing is completed when the arrangement movement processing of all the pad cells 13 is completed.

Finally, a wiring process between the pad cell and the buffer cell is performed (Step 3; see FIG. 3). In this case, I
After all the pad cells 13 have been arranged in the pad cell arrangement region 20 along the side of the C chip 12, the pad cell 1
3. The position of the connection component 14 is selected such that the wiring resistance between the buffer cells 15 is minimized.

In this process, as shown in FIG. 9, a plurality of connection positions (for example, 5
Pad wiring cells (PADA to PADE) are prepared. When the position of the pad cell 13 with respect to the buffer cell 15 is determined, each of the PADA-P
ADE is applied, and the connection state of the connection component 14 to the buffer cell 15 is examined. The smaller the deviation 47 between the center line 45 of the buffer cell 15 and the center line 46 of the connection component 14, the better the wiring condition and the lower the wiring resistance. Therefore, PADA to PADC are connected to the center line 45 of the buffer cell 15 and the connection component 14.
In the case of PADD, the misalignment 47 between the center line 45 of the buffer cell 15 and the center line 46 of the connection component 14 is small, and the wiring condition is good. I have. Further, the PADE is connected to the center line 45 of the buffer cell 15 and the connection component 14.
And the wiring resistance is minimized, which is an optimum wiring state. The wiring here is a straight line with zero bends. Connection component 14
Are set in advance.

From these, any pad cell 13
With respect to the X coordinate of the frame of the pad cell, the center line 45 of the buffer cell 15 opposed thereto, and the X coordinate of the frame.
A pattern in which the distance between the center line 45 of the buffer cell 15 and the center line 46 of the connection component 14 is the smallest is adopted after expressing the state in which the coordinates overlap with each other as a section graph.

As described above, the pad cells 13 are arranged at appropriate positions along one side of the IC chip 12. And I
Pad cells 13 are similarly arranged along other sides of the C chip 12. Each pad cell 13 arranged in this manner, when connecting the bonding wire 36, is connected to the bonding wire 3 with respect to the side of the IC chip 12.
6 is relaxed, and there is no possibility that the adjacent bonding wires 36 come into contact with each other.

[0034]

As is apparent from the above description, in the automatic pad cell arranging method of the present invention, the positioning is performed based on the angle of the bonding wire connected to each pad cell with respect to each side of the IC chip. Therefore, the pad cells to which the bonding wires are connected can be optimally arranged so that wire bonding can be easily performed without actually connecting the bonding wires.
Further, optimal wiring between the buffer cell and the pad cell can be performed.

[Brief description of the drawings]

FIG. 1 is a plan view showing a layout of an entire IC chip in which a method for automatically arranging pad cells according to the present invention is implemented.

FIG. 2 is an enlarged view of a main part thereof.

FIG. 3 is a flowchart showing a processing procedure according to the pad cell automatic wiring method of the present invention.

FIGS. 4A and 4B are plan views each showing an embodiment of a special pad cell arranged near a corner of an IC chip in the automatic pad cell arranging method of the present invention.

FIG. 5 is an explanatory diagram of processing contents when implementing the pad cell automatic arrangement method of the present invention.

FIG. 6 is a diagram showing an initial arrangement process of pad cells in the automatic pad cell arrangement method of the present invention.

FIG. 7 is a diagram showing a pad cell arrangement improvement process in the automatic pad cell arrangement method of the present invention.

FIG. 8 is a diagram showing an example of an angle-dependent function used in the automatic arrangement method of the present invention.

FIG. 9 is an explanatory diagram of a pad wiring cell used for wiring processing between a pad cell and a buffer cell in the automatic pad cell arranging method of the present invention.

FIG. 10 is a plan view showing a state where wire bonding is performed between a lead frame and an IC chip.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Internal core area 12 IC chip 13 Pad cell 13a Special pad cell 14 Connection component 15 Buffer cell 15a IO buffer 16 Signal terminal 17 Power supply plane terminal 18 Ground plane terminal 19 Pad connection plane terminal 20 Pad cell arrangement possible area 28 One side passing through the center of IC chip 29 Reference line perpendicular to one side passing through the center of IC chip 35 Lead frame 36 Bonding wire 45 Center line of buffer cell 46 Center line of connection component 47 Center line of buffer cell and center line of connection component Gap

Claims (5)

[Claims] 1. A method of arranging pad cells along each side of an IC chip, wherein the pad cells are positioned based on an angle of a bonding wire connected to each pad cell with respect to each side of the IC chip. Automatic placement method. 2. The pad cell according to claim 1, wherein the pad cell determines a connection position between the buffer cell arranged on the IC chip and a connection component connected to the buffer cell such that a wiring resistance with the connection component is minimized. Automatic pad cell placement method as described. 3. The bonding wire connected to the pad cell is connected to the IC chip by using an angle-dependent function using a variable as an angle between a straight line connecting the pad cell and the center of the IC chip and one side of the IC chip. 2. The method for automatically arranging pad cells according to claim 1, wherein an angle formed with one side of the chip is calculated. 4. The automatic arrangement of pad cells according to claim 1, wherein the arrangement interval of said pad cells is widened in the vicinity of said IC chip corner to increase the inclination angle of a bonding wire with respect to one side of said IC chip. Method. 5. The method according to claim 1, wherein the pad cells are arranged at a corner and a center of each side of the IC chip, respectively.
After the pad cells are sequentially arranged from the center of each side of the C chip toward each corner, from the pad cells near the corners of each side of the IC chip, toward the center.
2. The automatic placement method according to claim 1, wherein adjustment of the pad cells arranged sequentially is performed.