JPS6318654A - Electronic device - Google Patents

Abstract

PURPOSE:To make it possible to select each semiconductor chip and to enhance packaging density, by electrically connecting selecting lead pins and a plurality of dummy lead pins having the same serial numbers in each semiconductor device in series. CONSTITUTION:In a lead frame before assembling of a device 11, a chip selecting lead pin CSF1 and a plurality of dummy lead pins NC are provided in a specified sequence. In a lead frame 15 outside of the device 11, pins CSF2-CSF4 and pins NC are provided in a different sepcified sequence. By using the frame 15, devices 11-14 are assembled and stacked. The CSF1-CSF4 at the same position having the same numbers are electrically connected in series. The devices 11-14 are selected by the input of the chip selecting signals CSS.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an electronic device on which a plurality of semiconductor devices are mounted, and particularly to a technique that is effective when applied to a semiconductor chip selection technique.

[Prior art]

When configuring a large capacity memory using multiple memory chips in a microcomputer, etc., if you try to connect the memory chip select terminals directly, multiple memory chips will be selected by the same select signal (i.e., (enabled).

Therefore, for example, as shown in FIG. 7, memory chip select terminals cs1. cs2. It is necessary to combine the polarities of cs so that a plurality of memory chips 1, 2.3 are not selected at the same time. In order to realize this, each memory chip 1, 2.3 is provided with three memory chip select electrodes cs1.3 as shown in FIG. cs2
．． For cs and memory chip select ~ Topin C3F
Engineering.

C3F, , C3F3 are provided. In addition, in FIG. 7, 6 is a chip selector, and in FIG. 8, 5 is a bonding wire.

[Problem that the invention seeks to solve]

However, as a result of studying this technique, the inventors of the present invention found that the above method requires the preparation of a plurality of memory chips with different mask patterns used when manufacturing the memory chips.

SUMMARY OF THE INVENTION An object of the present invention is to provide a technology that allows selection terminals of semiconductor chips of a plurality of semiconductor devices to be configured in the same pattern and to select each semiconductor chip even if the respective lead pins are electrically connected in series. It is in.

Another object of the present invention is to provide a technique that can improve the packaging density of semiconductor devices.

Another object of the present invention is to provide a technique that can improve the efficiency of tests such as pellet inspection.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

An electronic device mounting a plurality of semiconductor devices.

Select lead pins and a plurality of dummy lead pins are provided in each of the semiconductor devices in different predetermined orders,
The select lead pins of each semiconductor device and a plurality of dummy lead pins having the same order number are electrically connected in series.

[Effect]

According to the above-described means, the select lead pins and the plurality of dummy lead pins are provided in each semiconductor device in different predetermined orders, and the select lead pins and the plurality of dummy lead pins of each of these semiconductor devices have the same order number. Since they are electrically connected in series, each semiconductor chip can be selected even if the select terminals of the semiconductor chips of multiple semiconductor devices are configured in the same pattern and the respective lead pins are electrically connected in series. be.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be specifically described using the drawings.

In addition, in the plan, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example I]

FIG. 1 is an explanatory diagram for explaining connection of select terminals of each semiconductor chip of an electronic device mounting a plurality of semiconductor chips according to Embodiment I of the present invention.

FIG. 2 is a plan view showing a schematic configuration of the electrodes of the semiconductor chips of each semiconductor device of Example I, and FIG. 3 is a lead electrically connected to the select electrode of each semiconductor chip shown in FIG. FIG. 4 is a plan view showing a schematic structure of an embodiment of the frame. FIG. 4 is a plan view showing the structure of the select lead portion of each semiconductor chip of the lead frame shown in FIG.

A plurality of semiconductor devices mounted on the electronic device of Example I have the same pattern of chip select a as shown in FIG.
It consists of a semiconductor chip each provided with one t-ics. Each of the semiconductor devices 11 to 14 has chip select electrodes C8 to C of the respective semiconductor chips 1 to 4.
34 (=O8) with chip select lead pins C3F, which are electrically connected to each other with dig wires 5,
~C3F4 and a plurality of dummy lead pins NC are provided in different predetermined orders as shown in FIG. are connected in series.

The lead frame of the semiconductor device 11 before assembly is
As shown in the figure (TAB is a tab), the chip select lead pin C3F and multiple dummy lead pins NC
are provided in a predetermined order. Further, the lead frame 15 other than the semiconductor device 11 before assembly is
As shown in (A), (B) and (C) of FIG. 4, respectively, the chip select lead pins C5F2. C
3F, CSF4 and a plurality of dummy lead pins NG are provided in different predetermined orders.

The semiconductor device 11 is manufactured using such a lead frame 15.
14 are assembled, and as shown in FIG. 5 (perspective view of the electronic device of this embodiment), the chip select lead pins C5F and 14 are stacked one on top of the other, and the chip select lead pins C5F, . Things are electrically connected in series.

In the selection operation of a plurality of semiconductor devices, as shown in FIGS. 1 and 5, when a chip select signal C8S, for example, a signal of 0001 is input, the semiconductor device 11 is selected. Similarly, when a signal of 0010 is input, the semiconductor device 12.

When a signal of 0100 is input, the semiconductor device 13
When a signal of 000 is input, each semiconductor device 14 is selected.

As mentioned above, the chip select lead pins C8F□ to C8F of the semiconductor devices 11 to 14 and the dummy lead pins N
By configuring a chip select circuit in which C is provided in a different predetermined order, a plurality of semiconductor devices 11
Select electrodes O81 to C84 of each of ~14 semiconductor chips
Even if the semiconductor devices 11 to 14 are configured in the same pattern C8 and the respective chip select lead pins C3F to C5F are electrically connected in series with the bonding wire 5, each of the semiconductor devices 11 to 14 can be selected with a simple configuration. . This eliminates the need to prepare a plurality of semiconductor chips with different mask patterns used during semiconductor chip manufacturing.

Also, semiconductor device 1i! By stacking 11 to 14, the packaging density can be improved.

Accordingly, when performing pellet inspection, conventionally it was necessary to prepare four types of test programs, but in this embodiment, only one type of test program is required, so that the efficiency of pellet inspection can be improved.

The present invention has been specifically explained above based on examples, but
It goes without saying that the present invention is not limited to the embodiments described above, and can be modified in various ways without departing from the spirit thereof.

For example, in the embodiment described above, the pattern of the lead frame 15 was shaped as shown in FIG. 3, but as shown in FIG. The lead pin C5F may be provided in a different pattern, and the chip select lead frame C3F0 and the chip select lead pin C3F1 may be electrically connected by one, for example, a bonding wire 5, during assembly.

Further, in the above embodiment, the semiconductor chip has one select electrode, but it is also possible to use two or more select electrodes and stack a larger number of semiconductor devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows.

(1) A chip select lead pin and a plurality of dummy lead pins are provided in each semiconductor device in different predetermined orders, and the chip select lead pins and the plurality of dummy lead pins with the same order number of each semiconductor device are electrically connected. Even if the select electrodes of the semiconductor chips of a plurality of semiconductor devices are configured in the same pattern by connecting the select terminals in series, the select terminals of the respective select terminals are electrically connected in series.

Each semiconductor device can be accurately selected by the chip select signal. This eliminates the need to prepare a plurality of semiconductor chips with different mask patterns used during semiconductor chip manufacturing.

(2) By stacking multiple semiconductor devices together.

Packaging density can be improved.

(3) According to (2) above, when performing pellet inspection, conventionally it was necessary to prepare four types of test programs, but in this embodiment, only one type of test program is required, improving the efficiency of pellet inspection. can do.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram for explaining the connection of select terminals of each semiconductor chip of an electronic device mounting a plurality of semiconductor devices according to an embodiment of the present invention, and FIG. FIG. 3 is a plan view showing a schematic configuration of the electrodes of each semiconductor chip shown in FIG. FIG. 5 is a perspective view showing the external appearance of an electronic device in which a plurality of semiconductor devices of this embodiment are mounted. FIG. 6 is a plan view showing the structure of another example of the lead frame of this example, and FIGS. 7 and 8 are for explaining the problems of a conventional electronic device in which a plurality of semiconductor devices are mounted. This is a diagram. In the figure, 1 to 4: semiconductor chip, 5: bonding wire, 6: chip selector, CS, CS engineering to C
84...Chip select electrode, C3F,...Chip select lead frame, C3F work to C3F4...
Chip select lead pin, NC...dummy lead pin, C8S...chip select signal, 11-14.
... Semiconductor device, 15... Lead frame. Agent Patent Attorney Katsuo Ogawa 7゛Figure 1//''4≦Mon1i':! F, Zero Misaki Figure 2 Figure 4 Figure 5 Figure 10σθ] Figure 6

Claims (1)

[Scope of Claims] 1. An electronic device mounting a plurality of semiconductor devices, wherein each semiconductor device is provided with select lead pins and a plurality of dummy lead pins in different predetermined orders, An electronic device characterized in that a select lead pin and a plurality of dummy lead pins having the same order number are electrically connected in series. 2. Claim 1, wherein the plurality of semiconductor devices are stacked on top of each other.
Electronic devices as described in Section.