JPS6285457A - Composite semiconductor package - Google Patents

Composite semiconductor package

Info

Publication number
JPS6285457A
JPS6285457A JP60225712A JP22571285A JPS6285457A JP S6285457 A JPS6285457 A JP S6285457A JP 60225712 A JP60225712 A JP 60225712A JP 22571285 A JP22571285 A JP 22571285A JP S6285457 A JPS6285457 A JP S6285457A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor package
package
composite
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60225712A
Other languages
Japanese (ja)
Inventor
Hiroki Ochi
越智　博樹
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60225712A priority Critical patent/JPS6285457A/en
Publication of JPS6285457A publication Critical patent/JPS6285457A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0657—Stacked arrangements of devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/0651—Wire or wire-like electrical connections from device to substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06572—Auxiliary carrier between devices, the carrier having an electrical connection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06582—Housing for the assembly, e.g. chip scale package [CSP]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

PURPOSE:To gather two types of chips in a composite package by forming the composite semiconductor package of an 'A' semiconductor package and a 'B' semiconductor package having external leads passing via a through hole of the 'A' package. CONSTITUTION:Semiconductor chip mounting surfaces 4 are recessed on the opposed surfaces of central positions of 'A' and 'B' semiconductor packages 2, 1, and semiconductor chips 3 are mounted therein. The package 2 has external leads 5a projected in a lattice shape on the opposed sides on the outer peripheral surfaces of the surfaces 4 and many through holes 6 formed on the outer peripheral surfaces of the leads 5a. Many external leads 5b to be passed via through holes 6 are projected at the positions corresponding to the holes 6 of the package 2. Accordingly, the packages 2, 1 are combined to form a composite semiconductor package 10.

Description

【発明の詳細な説明】 ［産業上の利用分野］ 本発明は半導体パッケージに関し、特に２種の半導体チ
ップを収納するため容易に組合せ可能な構造を持つ複合
形半導体パッケージに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor package, and more particularly to a composite semiconductor package having a structure that can be easily combined to accommodate two types of semiconductor chips.

［従来の技術］ 従来この種のピングリッドアレイ構造の半導体パッケー
ジは構造上１つの半導体チップを収納する状態とされ論
理回路とアナログ回路を同一半導体チップ」二で実現し
た場合であってもそれぞれ独立した外部接続リードを持
っていない状態となっていた。[Prior art] Conventionally, this type of semiconductor package with a pin grid array structure is structured to house one semiconductor chip, and even when logic circuits and analog circuits are realized on the same semiconductor chip, they are independent of each other. It was in a state where it did not have an external connection lead.

［解決すべき問題点］ 上記従来の半導体パッケージにあっては１つの半導体チ
ップしか収納出来ない欠点があった。[Problems to be Solved] The conventional semiconductor package described above has the drawback that only one semiconductor chip can be accommodated therein.

また、各半導体チップをパッケージ収容後、独立に試験
が出来ない欠点があった。Another drawback is that it is not possible to independently test each semiconductor chip after it is packaged.

更に、論理回路とアナログ回路を同一チップ上で実現し
た場合や大規模な論理回路を１半導体チップに集積した
場合、試験が難しい欠点があった。Furthermore, when a logic circuit and an analog circuit are realized on the same chip, or when a large-scale logic circuit is integrated on one semiconductor chip, there is a drawback that testing is difficult.

［問題点の解決手段］ 本発明は、上記従来の問題点に着目してなされたもので
、従来のピングリッドアレイ構造と同様の構成で複合化
が容易にでき、半導体チップをパッケージ収容後独立に
試験することができ、更には論理回路とアナログ回路と
をそれぞれ別の半導体チップに実現して各半導体チップ
を独立した半導体パッケージに収容後複合化し且つ独立
試験のできる複合形半導体パッケージを提供せんとする
ものである。[Means for Solving the Problems] The present invention has been made by focusing on the above-mentioned conventional problems, and can be easily combined with a structure similar to the conventional pin grid array structure, and can be made independent after the semiconductor chip is housed in a package. Furthermore, we provide a composite semiconductor package in which the logic circuit and the analog circuit are implemented on separate semiconductor chips, each semiconductor chip is housed in an independent semiconductor package, and then combined and independently tested. That is.

そのために、本発明は、ピングリッドアレイ構造の半導
体パッケージにおいて、半導体モップマウト面外周に格
子上に配設した外部接続リードのさらに外周にに貫通穴
を配設した甲半導体パッケージと、甲半導体パッケージ
の半導体チップマウント面と対応した半導体チップマウ
ント面を備え且つ前記した甲半導体パッケージの貫通穴
対応位置に配設した前記貫通穴に貫通される外部接続リ
ードを備える乙半導体パッケージとからなる複合形半導
体パッケージを提供するものである。To this end, the present invention provides a semiconductor package with a pin grid array structure, in which a through hole is provided on the outer periphery of external connection leads arranged in a grid on the outer periphery of the semiconductor mop mount surface; A composite semiconductor package comprising a semiconductor package B which has a semiconductor chip mounting surface corresponding to the semiconductor chip mounting surface and which is provided with an external connection lead that is passed through the through hole which is disposed at a position corresponding to the through hole of the semiconductor package A. It provides:

［実施例］ 以下、本発明の実施例を図面に基づいて説明する。[Example] Embodiments of the present invention will be described below based on the drawings.

第１図は、一実施例に係る複合形半導体パッケージの縦
断面図、第２図は、その外観斜視図、第３図は、第１図
、第２図に側に位置する乙半導体パッケージの斜視図、
そして、第４図は、第１図、第２図下側に位置する甲半
導体パッケージの斜視図である。FIG. 1 is a vertical cross-sectional view of a composite semiconductor package according to one embodiment, FIG. 2 is an external perspective view thereof, and FIG. Perspective view,
FIG. 4 is a perspective view of the first semiconductor package located on the lower side of FIGS. 1 and 2.

図中１は乙半導体パッケージ、２は甲半導体パッケージ
で、これら甲乙半導体パッケージ２．１を組合せて複合
形半導体パッケージ１０を得るものである。In the figure, 1 is a semiconductor package A and 2 is a semiconductor package A, and a composite semiconductor package 10 is obtained by combining these semiconductor packages A and B 2.1.

甲乙丙半導体パッケージ２、ｌの中央位置対向面に各々
半導体チップマウント面４が凹設され、該半導体チップ
マウント面４に各々半導体チップ３が取付けられるよう
になっている。Semiconductor chip mounting surfaces 4 are recessed in centrally opposing surfaces of the first and second semiconductor packages 2 and 1, and semiconductor chips 3 are respectively mounted on the semiconductor chip mounting surfaces 4.

また、甲半導体パッケージ２は、半導体チップマウント
面４の外周で、その反対側面に格子状に外部接続リード
５ａを突出させ、これら外部接続リード５ａの更に外周
に多数の貫通穴６を有している。Further, the first semiconductor package 2 has external connection leads 5a protruding in a grid pattern from the outer periphery of the semiconductor chip mounting surface 4 and the opposite side thereof, and has a large number of through holes 6 on the outer periphery of these external connection leads 5a. There is.

更に、乙半導体パッケージ１には、甲半導体パッケージ
２の貫通穴６対応位置に、これら貫通穴６に貫通される
多数の外部接続リード５ｂを突出させている。Further, the semiconductor package 1 has a large number of external connection leads 5b extending through the through holes 6 at positions corresponding to the through holes 6 of the semiconductor package 2.

従って、甲乙丙半導体パッケージ２．１の半導体チップ
マウント面４同士を対向させた状態で、乙半導体パッケ
ージ１の外部接続端子５ｂを、甲半導体パッケージ２の
貫通穴６に貫通、突出させて甲乙丙半導体パッケージ２
．１を組合せ複合形半導体パッケージ１０を得ることが
できるものである。Therefore, with the semiconductor chip mounting surfaces 4 of the A-B-C semiconductor package 2.1 facing each other, the external connection terminals 5b of the B-B semiconductor package 1 are penetrated and protruded into the through-holes 6 of the A-B semiconductor package 2. Semiconductor package 2
．． 1 can be combined to obtain a composite semiconductor package 10.

このように、甲乙丙半導体パッケージ２．１の外部接続
端子５ａ、５ｂが各々突出状態となるため、各々を独立
して試験することが可能となるものである。In this way, since the external connection terminals 5a and 5b of the A-B-C semiconductor package 2.1 are each in a protruding state, it is possible to test each of them independently.

［発明の効果］ 以上説明したように本発明は、ピングリッドアレイ構造
の半導体パッケージにおいて、半導体モップマウト面外
周に格子上に配設した外部接続リードのさらに外周にに
貫通穴を配設した甲半導体パッケージと、甲半導体パッ
ケージの半導体チップマウント面と対応した半導体チッ
プマウント面を備え且つ前記した甲半導体パッケージの
貫通穴対応位置に配設した前記貫通穴に貫通される外部
接続リードを備える乙半導体パッケージとからなる複合
形半導体パッケージとしたため、２種のチップを複合形
パッケージとして１つにまとめることが可能となり、ま
た、各、半導体チップを仮封止した後独立した試験が可
能となり、更には論理回路とアナログ回路をそれぞれ別
の半導体チップに実現し、各半導体チップを独立した甲
と乙半導体パッケージに収納後仮封止状態で独立試験が
可能となるため試験性が容易となる等の効果がある。[Effects of the Invention] As explained above, the present invention provides a semiconductor package having a pin grid array structure, in which a through hole is provided on the outer periphery of the external connection lead arranged in a grid on the outer periphery of the semiconductor mop mount surface. A semiconductor package comprising a package, a semiconductor chip mounting surface corresponding to the semiconductor chip mounting surface of the semiconductor package A, and an external connection lead that is passed through the through hole disposed at a position corresponding to the through hole of the semiconductor package A. Because it is a composite semiconductor package consisting of The circuit and analog circuit are realized on separate semiconductor chips, and each semiconductor chip is housed in independent semiconductor packages A and B, and then independent tests can be performed in a temporarily sealed state, making testability easier. be.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は、本発明の一実施例に係る複合形半導体パッケ
ージの縦断面図、 第２図は、その外観図、 第３図は、第１図、第２図上側に位置する乙半導体パッ
ケージの斜視図、 そして、第４図は、第１図、第２図下側に位置する中手
導体パッケージの斜視図である。 １：乙半導体パッケージ ２：中手導体パッケージ ３：半導体チップ ４：半導体チップマウント面 ５ａ、５ｂ＝外部接続リード ６：貫通穴FIG. 1 is a longitudinal sectional view of a composite semiconductor package according to an embodiment of the present invention, FIG. 2 is an external view thereof, and FIG. 3 is a semiconductor package located above FIGS. 1 and 2. FIG. 4 is a perspective view of the metacarpal conductor package located on the lower side of FIGS. 1 and 2. 1: Otsu semiconductor package 2: Middle conductor package 3: Semiconductor chip 4: Semiconductor chip mounting surface 5a, 5b = External connection lead 6: Through hole

Claims (1)

【特許請求の範囲】[Claims] ピングリッドアレイ構造の半導体パッケージにおいて、
半導体モップマウト面外周に格子上に配設した外部接続
リードのさらに外周に貫通穴を配設した甲半導体パッケ
ージと、甲半導体パッケージの半導体チップマウント面
と対応した半導体チップマウント面を備え且つ前記した
甲半導体パッケージの貫通穴対応位置に配設した前記貫
通穴に貫通される外部接続リードを備える乙半導体パッ
ケージとからなる複合形半導体パッケージ。In semiconductor packages with pin grid array structure,
A semiconductor package having through-holes arranged on the outer periphery of external connection leads arranged in a grid on the outer periphery of the semiconductor mop mount surface, and a semiconductor chip mounting surface corresponding to the semiconductor chip mounting surface of the semiconductor package A, and the above-mentioned 1. A composite semiconductor package comprising: a semiconductor package including an external connection lead that is inserted into the through hole and is disposed at a position corresponding to the through hole of the semiconductor package.
JP60225712A 1985-10-09 1985-10-09 Composite semiconductor package Pending JPS6285457A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60225712A JPS6285457A (en) 1985-10-09 1985-10-09 Composite semiconductor package

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60225712A JPS6285457A (en) 1985-10-09 1985-10-09 Composite semiconductor package

Publications (1)

Publication Number Publication Date
JPS6285457A true JPS6285457A (en) 1987-04-18

Family

ID=16833621

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60225712A Pending JPS6285457A (en) 1985-10-09 1985-10-09 Composite semiconductor package

Country Status (1)

Country Link
JP (1) JPS6285457A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01294725A (en) * 1987-10-07 1989-11-28 Nitto Denko Corp Curable silicone release agent
US5691243A (en) * 1995-05-15 1997-11-25 Nec Corporation Process for manufacturing composite semiconductor device

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01294725A (en) * 1987-10-07 1989-11-28 Nitto Denko Corp Curable silicone release agent
JP2575467B2 (en) * 1987-10-07 1997-01-22 日東電工株式会社 Curable silicone release agent
US5691243A (en) * 1995-05-15 1997-11-25 Nec Corporation Process for manufacturing composite semiconductor device

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