JPH04111328A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPH04111328A
JPH04111328A JP2229270A JP22927090A JPH04111328A JP H04111328 A JPH04111328 A JP H04111328A JP 2229270 A JP2229270 A JP 2229270A JP 22927090 A JP22927090 A JP 22927090A JP H04111328 A JPH04111328 A JP H04111328A
Authority
JP
Japan
Prior art keywords
integrated circuit
pads
pad
bonding
circuit device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2229270A
Other languages
Japanese (ja)
Inventor
Takaharu Itou
貴治 伊藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP2229270A priority Critical patent/JPH04111328A/en
Publication of JPH04111328A publication Critical patent/JPH04111328A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05554—Shape in top view being square
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/45124—Aluminium (Al) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01015—Phosphorus [P]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Of Individual Semiconductor Devices (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To easily position a probe for measurement without scratching pads for wire bonding at the time of P/W tests by providing pads for electrical tests which are connected with pads for bonding and have large areas outside an integrated circuit element. CONSTITUTION:This integrated circuit device is formed as a wafer and provided with an integrated circuit element 1, pads 2 for bonding formed around a circuit area, etc., pads 3 for P/W, and aluminum wires 4 for connecting the pads 2 and 3 with each other. The pads 3 for P/W are larger in area than the pads 2 and formed on the outside of the element 1. When this integrated circuit device is constituted in such way, a probe for electric tests can be positioned easily to the pads 3 for P/W without scratching the pads 2 for bonding.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は集積回路装置に関し、特に面積の小さいボンデ
ィングパッドを有する集積・回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to integrated circuit devices, and more particularly to integrated circuit devices having small area bonding pads.

〔従来の技術〕[Conventional technology]

従来、この種の集積回路装置は、電気的なテストをする
にあたりボンディングパッドを用いている。Conventionally, this type of integrated circuit device uses bonding pads for electrical testing.

第３図はかかる従来の一例を示す集積回路装置の平面図
である。FIG. 3 is a plan view of an integrated circuit device showing an example of such a conventional device.

第３図に示すように、従来の集積回路装置は集積回路素
子１内の回路領域等各種の領域の周囲にボンディングパ
ッド２を形成している。この集積回路素子１の電気的特
性等のテストを行なう際は、面積が極小であるこのボン
ディングパッド２を用いて試験している。すなわちボン
ディング用パッドと電気的テスト用パッドは同一である
。As shown in FIG. 3, in the conventional integrated circuit device, bonding pads 2 are formed around various areas such as circuit areas within an integrated circuit element 1. When testing the electrical characteristics of the integrated circuit element 1, the bonding pad 2, which has an extremely small area, is used. That is, the bonding pad and the electrical test pad are the same.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の集積回路装置は、ボンディング用パッド
と電気的テスト用のパッドが同一である。すなわち、ウ
ェーハ状態で行なう電気的テスト工程、いわゆるＰ／Ｗ
における測定用の探触針を当てるパッドは、組立時にボ
ンディングワイヤを圧着させるべき部分である。従って
、Ｐ／Ｗ時に針を当てた時に、そのパッドに傷がつき、
ワイヤボンディング上支障をきたすという欠点がある。In the conventional integrated circuit device described above, the bonding pad and the electrical test pad are the same. In other words, the electrical test process performed in the wafer state, so-called P/W
The pad to which the measurement probe is applied is the part to which the bonding wire is crimped during assembly. Therefore, when the needle is applied during P/W, the pad may be scratched.
This has the disadvantage of causing problems in wire bonding.

また、上述のボンディングパッドは、面積の極小化およ
び高密度化を求められているので、Ｐ／Ｗ時にパッドと
探触針との位置合せを困難にするという欠点がある。Further, since the above-mentioned bonding pad is required to have a minimized area and a high density, it has the disadvantage that it is difficult to align the pad and the probe during P/W.

本発明の目的は、かかるＰ／Ｗテスト時にもワイヤボン
ディングパッドを傷つけることなく、しかも測定用探触
針の位置合わせを容易にする集積回路装置を提供するこ
とにある。An object of the present invention is to provide an integrated circuit device that does not damage wire bonding pads even during such a P/W test, and also facilitates positioning of a measurement probe.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の集積回路装置は、ボンディングパッドを形成し
た集積回路素子の外部に前記ボンディングパッドに接続
され且つ前記ボンディングパッドよりも面積の大きい電
気的なテストパッドを有して構成される。The integrated circuit device of the present invention is configured to have an electrical test pad connected to the bonding pad and having a larger area than the bonding pad outside the integrated circuit element on which the bonding pad is formed.

〔実施例〕〔Example〕

次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.

第１図は本発明の第一の実施例を示す集積回路装置の平
面図である。FIG. 1 is a plan view of an integrated circuit device showing a first embodiment of the present invention.

第１図に示すように、本実施例はウェーハとして形成さ
れ、集積回路素子１と、回路領域等の周囲に形成される
ボンディングパッド２と、Ｐ／Ｗ用パッド３と、ボンデ
ィングパッド２とＰ／Ｗ用バッド３を相互接続するため
のアルミニウム（Ａ（）配線４とを有している。また、
このＰ／Ｗパット３はボンディングパッド２よりも面積
が大きく、しかも集積回路素子１の外部に形成される。As shown in FIG. 1, this embodiment is formed as a wafer, and includes an integrated circuit element 1, a bonding pad 2 formed around a circuit area, a P/W pad 3, a bonding pad 2, and a P/W pad 3. It has aluminum (A()) wiring 4 for interconnecting the pads 3 for /W.
This P/W pad 3 has a larger area than the bonding pad 2 and is formed outside the integrated circuit element 1.

この様な構成にすることにより、Ｐ／Ｗ時にＰ／Ｗ用の
パッド３の電気的テスト用探触針を容易台わせることが
出来、さらにボンディング用パッド２に傷をつけること
もない。With this configuration, the electrical test probe of the P/W pad 3 can be easily placed on the P/W pad 3 during P/W, and the bonding pad 2 will not be damaged.

第２図は本発明の第二の実施例を示す集積回路装置の平
面図である。FIG. 2 is a plan view of an integrated circuit device showing a second embodiment of the present invention.

第２図に示すように、本実施例は前述した第一の実施例
と比較してＰ／Ｗ用のパッド３をウェーハ５に隣接する
集積回路素子１の中央に配置し、それぞれの集積回路素
子１のボンディング用パッド２とＡＡ配線４で接続した
ものである。かかるケースはＰ／Ｗ用のパッド３を前後
左右に隣接する集積回路素子１に対して共用化すること
ができ、より効率化される。As shown in FIG. 2, in comparison with the first embodiment described above, in this embodiment, the P/W pad 3 is arranged at the center of the integrated circuit element 1 adjacent to the wafer 5, and each integrated circuit The bonding pad 2 of the element 1 is connected to the AA wiring 4. In such a case, the P/W pad 3 can be shared by the integrated circuit elements 1 adjacent to each other in the front, rear, left, and right directions, thereby improving efficiency.

〔発明の効果〕〔Effect of the invention〕

以上説明したように、本発明の集積回路装置は、集積回
路素子の外にボンディング用パッドと相互接続された面
積の大きな電気的テスト用のパッドを有することにより
、Ｐ／Ｗ用のパッドと測定用探触針の位置合わせを容易
にする上、ボンディング用パッドに傷をつけてしまうこ
とも解消されるという効果がある。As explained above, the integrated circuit device of the present invention has a large-area electrical test pad that is interconnected with a bonding pad outside the integrated circuit element. This has the effect of not only making positioning of the probe needle easier, but also eliminating the possibility of damaging the bonding pad.

３テストパツド3 test pads

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は本発明の第一の実施例を示す集積回路装置の平
面図、第２図は本発明の第二の実施例を示すウェーハの
一部分の平面図、第３図は従来の一例を示す集積回路装
置の平面図である。 １・・・集積回路素子、２・・・ポンデイグパッド、３
・・・テストパッド、４・・・ＡＪ既配線５・、・ウェ
ーハ。 第１図FIG. 1 is a plan view of an integrated circuit device showing a first embodiment of the present invention, FIG. 2 is a plan view of a portion of a wafer showing a second embodiment of the invention, and FIG. 3 is a plan view of a conventional example. FIG. 2 is a plan view of the integrated circuit device shown in FIG. DESCRIPTION OF SYMBOLS 1... Integrated circuit element, 2... Ponding pad, 3
...Test pad, 4...AJ wiring 5...Wafer. Figure 1

Claims (1)

【特許請求の範囲】[Claims] 　ボンディングパッドを形成した集積回路素子の外部に
前記ボンディングパッドに接続され且つ前記ボンディン
グパッドよりも面積の大きい電気的なテストパッドを有
することを特徴とする集積回路装置。An integrated circuit device comprising an electrical test pad connected to the bonding pad and having a larger area than the bonding pad on the outside of the integrated circuit element on which the bonding pad is formed.
JP2229270A 1990-08-30 1990-08-30 Integrated circuit device Pending JPH04111328A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2229270A JPH04111328A (en) 1990-08-30 1990-08-30 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2229270A JPH04111328A (en) 1990-08-30 1990-08-30 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPH04111328A true JPH04111328A (en) 1992-04-13

Family

ID=16889483

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2229270A Pending JPH04111328A (en) 1990-08-30 1990-08-30 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPH04111328A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007501522A (en) * 2003-08-05 2007-01-25 フリースケール セミコンダクター インコーポレイテッド Integrated circuit having inspection pad structure and inspection method

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007501522A (en) * 2003-08-05 2007-01-25 フリースケール セミコンダクター インコーポレイテッド Integrated circuit having inspection pad structure and inspection method

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