JPH046858A - Pin grid array package type semiconductor device - Google Patents
Pin grid array package type semiconductor deviceInfo
- Publication number
- JPH046858A JPH046858A JP10838390A JP10838390A JPH046858A JP H046858 A JPH046858 A JP H046858A JP 10838390 A JP10838390 A JP 10838390A JP 10838390 A JP10838390 A JP 10838390A JP H046858 A JPH046858 A JP H046858A
- Authority
- JP
- Japan
- Prior art keywords
- external lead
- semiconductor device
- substrate
- chip
- type semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 title claims description 21
- 239000000758 substrate Substances 0.000 claims description 47
- 239000011295 pitch Substances 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 abstract description 6
- 239000011347 resin Substances 0.000 abstract description 3
- 229920005989 resin Polymers 0.000 abstract description 3
- 238000007789 sealing Methods 0.000 abstract description 3
- 230000002950 deficient Effects 0.000 description 4
- 229910000679 solder Inorganic materials 0.000 description 4
- 230000007423 decrease Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000007598 dipping method Methods 0.000 description 1
- 238000005553 drilling Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000012856 packing Methods 0.000 description 1
- 238000012216 screening Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
［産業上の利用分野コ
本発明は複数のＩＣチップが搭載されるピングリッドア
レイパッケージ型半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a pin grid array package type semiconductor device on which a plurality of IC chips are mounted.
［従来の技術］
従来、この種のピングリッドアレイパッケージ型半導体
装置としては、例えばハイブリッドＩＣのように、１つ
の基板上に複数のＩＣチップが搭載されるものがある。[Prior Art] Conventionally, as this type of pin grid array package type semiconductor device, there is one in which a plurality of IC chips are mounted on one substrate, such as a hybrid IC, for example.
このハイブリッドＩＣは第４図に示すように構成されて
いる。板状の基板１１の上面には２つのＩＣチップ１２
が所定の位置に搭載されている。各ＩＣチップ１２はボ
ンディングワイヤ１３により基板１１上に形成された配
線（図示せず）に電気的に接続されている。パッケージ
１５はＩＣチップ１２を覆うようにして基板１１の上面
の縁部に固定されている。基板１１の下面には複数の外
部リードピン１４が下方に向けて設けられている。外部
リードピン１４はワイヤ１３及び前記配線を介してＩＣ
チップ１２に電気的に接続されている。This hybrid IC is constructed as shown in FIG. Two IC chips 12 are mounted on the top surface of the plate-shaped substrate 11.
is mounted in place. Each IC chip 12 is electrically connected to wiring (not shown) formed on the substrate 11 by a bonding wire 13. The package 15 is fixed to the edge of the upper surface of the substrate 11 so as to cover the IC chip 12. A plurality of external lead pins 14 are provided on the lower surface of the substrate 11 so as to face downward. The external lead pin 14 is connected to the IC via the wire 13 and the wiring.
It is electrically connected to the chip 12.
また、その他のピングリッドアレイパッケージ型半導体
装置としては、例えば特開昭５９−８４５５７号に示す
ように、１つの基板の両面にＩＣチップが搭載されるも
のもある。Further, as other pin grid array package type semiconductor devices, there is also one in which IC chips are mounted on both sides of one substrate, as shown in Japanese Patent Laid-Open No. 59-84557, for example.
［発明が解決しようとする課題］
しかしながら、上述した従来のピングリッドアレイパッ
ケージ型半導体装置においては、１つの基板に複数個の
ＩＣチップを搭載するため、全てのＩＣチップを搭載し
た後でなければ、良品及び不良品の選別試験を実施する
ことができない。この場合、例えば、１つのＩＣチップ
を基板上に搭載した後の歩留りが９８％である場合、こ
の基板上に２つのＩＣチップを搭載した後の歩留りは８
６％となり、装置全体としての製造歩留りが低下してし
まうという問題点がある。[Problems to be Solved by the Invention] However, in the conventional pin grid array package type semiconductor device described above, since a plurality of IC chips are mounted on one substrate, the , it is not possible to carry out screening tests for good and defective products. In this case, for example, if the yield after mounting one IC chip on a board is 98%, the yield after mounting two IC chips on this board is 8%.
6%, which poses a problem in that the manufacturing yield of the entire device decreases.
本発明はかかる問題点に鑑みてなされたものであって、
製造歩留りを向上させることができるピングリッドアレ
イパッケージ型半導体装置を提供することを目的とする
。The present invention has been made in view of such problems, and includes:
An object of the present invention is to provide a pin grid array package type semiconductor device that can improve manufacturing yield.
［課題を解決するための手段］
本発明に係るピングリッドアレイパッケージ型半導体装
置は、第１のＩＣチップが搭載され複数の第１の外部リ
ードピンが設けられた第１の基板と、第２のＩＣチップ
が搭載され複数の第２の外部リードピンが設けられてい
ると共に前記第１の外部リードピンが挿通されるスルー
ホールが形成された第２の基板とを有し、前記第１及び
前記第２の基板は前記第１の外部リードピンを前記スル
ーホールに挿通させて前記第２の基板から突出させた状
態で相互に固定されることを特徴とする。[Means for Solving the Problems] A pin grid array packaged semiconductor device according to the present invention includes a first substrate on which a first IC chip is mounted and a plurality of first external lead pins, and a second substrate. a second substrate on which an IC chip is mounted, a plurality of second external lead pins are provided, and a through hole through which the first external lead pins are inserted; The substrates are fixed to each other with the first external lead pin inserted through the through hole and protruding from the second substrate.
［作用コ
本発明においては、複数の第１の外部リードピンが設け
られた第１の基板に搭載された第１のＩＣチップと、複
数の第２の外部リードピンが設けられていると共に前記
第１の外部リードピンが挿通されるスルーホールが形成
された第２の基板に搭載された第２のＩＣチップとを夫
々個別的に検査して良品及び不良品を選別することがで
きる。[Operations] In the present invention, a first IC chip mounted on a first substrate provided with a plurality of first external lead pins, a plurality of second external lead pins provided, and a first IC chip mounted on a first substrate provided with a plurality of first external lead pins; It is possible to individually inspect the second IC chips mounted on the second substrate in which through-holes into which the external lead pins are inserted are formed, and to sort out non-defective products and defective products.
また、前記第１の外部リードピンを前記スルーホールに
挿通し、前記第２の基板から突出させることにより、前
記第１及び前記第２の基板を相互に固定すると、第１及
び第２の基板が組み立てられて本発明に係るピングリッ
ドアレイパッケージ型半導体装置の製品が得られる。こ
のため、従来のように、複数のＩＣチップを１つの基板
上に搭載する場合とは異なって、製造歩留りが向上する
。Further, when the first and second substrates are fixed to each other by inserting the first external lead pin into the through hole and protruding from the second substrate, the first and second substrates are fixed to each other. When assembled, a pin grid array package type semiconductor device product according to the present invention is obtained. Therefore, unlike the conventional case where a plurality of IC chips are mounted on one substrate, the manufacturing yield is improved.
また、本発明においては、前記第１及び前記第２の外部
リードピンのピッチを夫々２．５４■ｌにすると、前記
第１及び前記第２の基板を検査する場合に、従来から使
用されている検査用ソケットをそのまま使用できるにも
拘らず、製品としては、第１及び第２の基板を組み立て
て前記第１及び前記第２の外部リードピンの全てのピン
を使用することにより、ピッチが１．８＋ｍの千鳥状の
ピン配置にすることができ、実装密度を高めることがで
きる。Further, in the present invention, when the pitch of the first and second external lead pins is set to 2.54 l, respectively, when inspecting the first and second boards, it is possible to Although the test socket can be used as is, as a product, the pitch is 1.0 by assembling the first and second boards and using all of the first and second external lead pins. It is possible to have a staggered pin arrangement of 8+m, and it is possible to increase the mounting density.
［実施例コ
次に、本発明の実施例について添付の図面を参照して説
明する。[Embodiments] Next, embodiments of the present invention will be described with reference to the accompanying drawings.
第１図は本発明の第１の実施例に係るピングリッドアレ
イパッケージ型半導体装置を示す部分拡大断面図である
。FIG. 1 is a partially enlarged sectional view showing a pin grid array package type semiconductor device according to a first embodiment of the present invention.
板状の基板１ａ及び１ｂは平面視で矩形をなし、夫々上
面の略中夫に凹状のキャビティが形成されている。基板
１ａ、１ｂの前記キャビティの底面には夫々ＩＣチップ
２ａ、２ｂが搭載されている。The plate-shaped substrates 1a and 1b are rectangular in plan view, and each has a concave cavity formed approximately in the center of its upper surface. IC chips 2a and 2b are mounted on the bottom surfaces of the cavities of the substrates 1a and 1b, respectively.
ＩＣチップ２ ａ ＋ ２ ｂは夫々ボンディングワ
イヤ３ａ、３ｂにより基板１ａ、ｌｂ上に形成された配
線（図示せず）に接続されている。そして、ＩＣチップ
２ａ、２ｂ及びボンディングワイヤ３ａ。The IC chips 2 a + 2 b are connected to wiring (not shown) formed on the substrates 1 a and lb by bonding wires 3 a and 3 b, respectively. And IC chips 2a, 2b and bonding wire 3a.
３ｂは、ＩＣチップ２ａ、２ｂ上に夫々形成された封止
樹脂層４ ａ ＋ ４ ｂにより保護されている。3b are protected by sealing resin layers 4a+4b formed on the IC chips 2a and 2b, respectively.
基板１ａ、ｌｂの下面には夫々ピッチが２．５４ｍｍで
ある複数の外部リードピン５ ａ ＋ ５ ｂがその
先端を下方に向けて格子状に配設されている。この外部
リードピン５ａ、５ｂはいずれもその基端部に太径部分
を有し、この太径部分を夫々基板１ａ＋１ｂの厚さ方向
に設けられたスルーホール７ａ。A plurality of external lead pins 5 a + 5 b each having a pitch of 2.54 mm are arranged in a grid pattern on the lower surfaces of the substrates 1 a and 1 b with their tips facing downward. Each of the external lead pins 5a and 5b has a large diameter portion at its base end, and this large diameter portion forms a through hole 7a provided in the thickness direction of the substrates 1a+1b, respectively.
７ｂに押し込んで嵌合させることにより基板１ａ。The substrate 1a is pushed into and fitted into the substrate 7b.
１ｂに固定されている。この外部リードピン５ａ。It is fixed at 1b. This external lead pin 5a.
５ｂは夫々ワイヤ３ａ、３ｂ及び前記配線を介してＩＣ
チップ２ ａ ｒ ２ ｂに電気的に接続されている。5b is connected to the IC via the wires 3a, 3b and the wiring, respectively.
It is electrically connected to chips 2 a r 2 b.
また、外部リードピン５ａ、５ｂは、基板ｌａ、ｌｂを
整合させて重ね合わせた場合、基板の表面に沿う方向の
縦及び横方向に夫々１．２７ｍｍずれるようになってい
る。そして、基板１ｂには基板１ａの外部リードピン５
ａに対応する部分に厚さ方向に挿通するスルーホール７
Ｃが設けられている。そして、基板１ｂの上方から外部
リードピン５ａをスルーホール７Ｃに挿通させて基板ｆ
ａｔ１ｂを重ね合わせた後に、外部リードピン５ａ。Furthermore, when the substrates la and lb are aligned and superimposed, the external lead pins 5a and 5b are shifted by 1.27 mm in the vertical and horizontal directions along the surface of the substrates, respectively. The external lead pins 5 of the substrate 1a are attached to the substrate 1b.
Through hole 7 inserted in the thickness direction in the part corresponding to a
C is provided. Then, the external lead pin 5a is inserted into the through hole 7C from above the board 1b, and the board f is inserted into the through hole 7C.
After overlapping at1b, external lead pin 5a.
５ｂが半田６により基板１ｂに固着されるようになって
いる。また、外部リードピン５ｂの長さを通常の４乃至
５菖嘗にし、外部リードピン５ａの長さを例えば７．５
乃至８．５ｍｍにすると、外部リードピン５ａ、５ｂの
先端を揃えることができる。5b is fixed to the substrate 1b by solder 6. In addition, the length of the external lead pin 5b is set to the usual 4 to 5 steps, and the length of the external lead pin 5a is set to, for example, 7.5 steps.
When the length is set to 8.5 mm, the tips of the external lead pins 5a and 5b can be aligned.
このように構成されるピングリッドアレイパッケージ型
半導体装置においては、基板１ａ＋１ｂに夫々ＩＣチッ
プ２ａ、２ｂを搭載した後に、即ち基板！ａ、ｌｂを組
み立てる前に各ＩＣチップ２ａ、２ｂについて個別的に
良否を判定することができる。このため、複数のＩＣチ
ップを１つの基板上に搭載する場合とは異なって、ピン
グ’Ｊ −／ドアレイパッケージ型半導体装置の製造歩
留りの低下を防止できる。また、ＩＣチップが搭載され
た基板１ａ、１ｂを検査する場合には、従来と同様にし
て、ピッチが２．５４■嘗の検査用ソケットを使用する
ことができる。一方、製品としては、第１図に示すよう
に、ピッチが２．５４ｍｍの外部リードピン５ ａ ＋
５ ｂを有する基板１ａ、ｌｂを重ねあわせること
により使用されるので、第３図に示す基板１ｂの部分拡
大底面図に示すように、外部り−Ｆピア５ａと外部リー
ドピン５ｂとの間のピッチが約１．８酊であって千鳥格
子状の実装密度が高いピングリッドアレイパッケージ型
半導体装置を得ることができる。In the pin grid array package type semiconductor device configured in this way, after the IC chips 2a and 2b are mounted on the substrates 1a and 1b, respectively, that is, the substrates! Before assembling IC chips 2a and 2b, it is possible to individually determine the quality of each IC chip 2a and 2b. Therefore, unlike the case where a plurality of IC chips are mounted on one substrate, it is possible to prevent a decrease in the manufacturing yield of the pin'J-/door array package type semiconductor device. Further, when inspecting the substrates 1a and 1b on which IC chips are mounted, an inspection socket with a pitch of 2.54 cm can be used as in the conventional case. On the other hand, as shown in Fig. 1, the product is an external lead pin 5 a + with a pitch of 2.54 mm.
Since it is used by overlapping the boards 1a and 1b having 5b, as shown in the partially enlarged bottom view of the board 1b shown in FIG. It is possible to obtain a pin grid array package type semiconductor device with a high packing density in a houndstooth pattern, in which the voltage is about 1.8 mm.
なお、本実施例においては、外部リードピン５ａ、５ｂ
の直径は、機械的強度、スルーホールの開孔技術及び微
小基板の配線技術等を勘案して約０．３ｍ＋ｉにするこ
とが好ましい。Note that in this embodiment, the external lead pins 5a, 5b
It is preferable to set the diameter to approximately 0.3 m+i in consideration of mechanical strength, through hole drilling technology, micro board wiring technology, etc.
第２図は本発明の第２の実施例に係るピングリッドアレ
イパッケージ型半導体装置を示す部分拡大断面図である
。本実施例はＩＣチップの搭載構造が異なる実施例であ
るため、第２図において第１図と同一物には同一符号を
付してその部分の詳細な説明は省略する。FIG. 2 is a partially enlarged sectional view showing a pin grid array package type semiconductor device according to a second embodiment of the present invention. Since this embodiment is an embodiment in which the IC chip mounting structure is different, in FIG. 2, the same parts as those in FIG.
本実施例においては、基板１ｂは下面の略中央に凹状の
キャビティが形成されていて、このキャビティの底面に
ＩＣチップ２ｂが搭載されている。In this embodiment, a concave cavity is formed approximately in the center of the lower surface of the substrate 1b, and an IC chip 2b is mounted on the bottom surface of this cavity.
そして、基板１ａと基板１ｂとは密着するようにして固
定されている。The substrate 1a and the substrate 1b are fixed in close contact with each other.
本実施例においては、スルーホール７ａ、７ｃが連結さ
れるので、半田デイツプ工程において、毛細管現象によ
り半田８がスルーホール７ａに注入される。このため、
第１の実施例に比して強度を高めることができ、信頼性
をより一層向上させることができる。In this embodiment, since the through holes 7a and 7c are connected, the solder 8 is injected into the through hole 7a by capillary action in the solder dipping step. For this reason,
The strength can be increased compared to the first embodiment, and the reliability can be further improved.
［発明の効果コ
以上説明したように本発明によれば、第１のＩＣチップ
が搭載され複数の第１の外部リードピンが設けられた第
１の基板と、第２のＩＣチップが搭載され複数の第２の
外部リードピンが設けられていると共に前記第１の外部
リードピンが挿通されるスルーホールが形成された第２
の基板とを有し、前記第１及び前記第２の基板は前記第
１の外部リードピンを前記スルーホールに挿通させて前
記第２の基板から突出させた状態で相互に固定されるか
ら、前記第１及び前記第２の基板を夫々個′別的に検査
して各ＩＣチップ毎に良品及び不良品を選別することが
できる。このため、ピングリッドアレイパッケージ型半
導体装置の製造歩留りを向上させることができる。また
、製品としては、各基板を組み立てて、前記第１及び前
記第２の外部リードピンの全てのビンを使用することに
より、実装密度を従来に比してより一層高めることがで
きる。[Effects of the Invention] As explained above, according to the present invention, there is a first substrate on which a first IC chip is mounted and a plurality of first external lead pins, and a first substrate on which a second IC chip is mounted and a plurality of first external lead pins. A second external lead pin is provided, and a through hole into which the first external lead pin is inserted is formed.
and the first and second substrates are fixed to each other with the first external lead pin inserted through the through hole and protruding from the second substrate. The first and second substrates can be individually inspected to select good products and defective products for each IC chip. Therefore, the manufacturing yield of the pin grid array package type semiconductor device can be improved. Further, as a product, by assembling each board and using all the bins of the first and second external lead pins, the packaging density can be further increased compared to the conventional product.
第１図は本発明の第１の実施例に係るピングリッドアレ
イパッケージ型半導体装置を示す部分拡大断面図、第２
図は本発明の第２の実施例に係るピングリッドアレイパ
ッケージ型半導体装置を示す部分拡大断面図、第３図は
第１図の部分拡大底面図、第４図は従来のピングリッド
アレイパッケ−ジ型半導体装置を示す断面図である。
ｌａ、ｌｂ、１１；基板、２ａ、２ｂ、１２：ＩＣチッ
プ、３ａ＋ ３ｂ、１３；ボンディングワイヤ、４ａ
、４ｂ：封止樹脂層、５ａ、５ｂ、１４：外部リードピ
ン、６；半田、７ａ、７ｂ、７Ｃ；スルーホール、１５
；パッケージ1 is a partially enlarged sectional view showing a pin grid array package type semiconductor device according to a first embodiment of the present invention; FIG.
The figure is a partially enlarged sectional view showing a pin grid array package type semiconductor device according to a second embodiment of the present invention, FIG. 3 is a partially enlarged bottom view of FIG. 1, and FIG. 4 is a conventional pin grid array package type semiconductor device. FIG. 2 is a cross-sectional view showing a di-type semiconductor device. la, lb, 11; substrate, 2a, 2b, 12: IC chip, 3a+ 3b, 13; bonding wire, 4a
, 4b: Sealing resin layer, 5a, 5b, 14: External lead pin, 6: Solder, 7a, 7b, 7C: Through hole, 15
;package
Claims (2)
ードピンが設けられた第１の基板と、第２のＩＣチップ
が搭載され複数の第２の外部リードピンが設けられてい
ると共に前記第１の外部リードピンが挿通されるスルー
ホールが形成された第２の基板とを有し、前記第１及び
前記第２の基板は前記第１の外部リードピンを前記スル
ーホールに挿通させて前記第２の基板から突出させた状
態で相互に固定されることを特徴とするピングリッドア
レイパッケージ型半導体装置。(1) A first substrate on which a first IC chip is mounted and a plurality of first external lead pins are mounted; a second board on which a second IC chip is mounted and a plurality of second external lead pins are mounted; a second substrate having a through hole formed therein through which the first external lead pin is inserted; A pin grid array package type semiconductor device, characterized in that the semiconductor device is fixed to each other while protruding from two substrates.
々２．５４ｍｍであることを特徴とする請求項１に記載
のピングリッドアレイパッケージ型半導体装置。(2) The pin grid array package type semiconductor device according to claim 1, wherein pitches of the first and second external lead pins are each 2.54 mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10838390A JP2870115B2 (en) | 1990-04-24 | 1990-04-24 | Pin grid array package type semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10838390A JP2870115B2 (en) | 1990-04-24 | 1990-04-24 | Pin grid array package type semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH046858A true JPH046858A (en) | 1992-01-10 |
| JP2870115B2 JP2870115B2 (en) | 1999-03-10 |
Family
ID=14483381
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10838390A Expired - Lifetime JP2870115B2 (en) | 1990-04-24 | 1990-04-24 | Pin grid array package type semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2870115B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05206378A (en) * | 1992-01-30 | 1993-08-13 | Nec Kyushu Ltd | Semiconductor device |
| US5567984A (en) * | 1994-12-08 | 1996-10-22 | International Business Machines Corporation | Process for fabricating an electronic circuit package |
-
1990
- 1990-04-24 JP JP10838390A patent/JP2870115B2/en not_active Expired - Lifetime
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05206378A (en) * | 1992-01-30 | 1993-08-13 | Nec Kyushu Ltd | Semiconductor device |
| US5567984A (en) * | 1994-12-08 | 1996-10-22 | International Business Machines Corporation | Process for fabricating an electronic circuit package |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2870115B2 (en) | 1999-03-10 |
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