JPH09330993A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPH09330993A JPH09330993A JP17185296A JP17185296A JPH09330993A JP H09330993 A JPH09330993 A JP H09330993A JP 17185296 A JP17185296 A JP 17185296A JP 17185296 A JP17185296 A JP 17185296A JP H09330993 A JPH09330993 A JP H09330993A
- Authority
- JP
- Japan
- Prior art keywords
- lands
- semiconductor
- solder bump
- solder
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0266—Marks, test patterns or identification means
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/3457—Solder materials or compositions; Methods of application thereof
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、半導体装置に関し、特
に半導体チップが複数個搭載されて形成される半導体装
置に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device, and more particularly to a semiconductor device formed by mounting a plurality of semiconductor chips.
【０００２】[0002]
【従来の技術】従来、この種の半導体チップが複数個搭
載されて形成される半導体装置は、テスティングを容易
にする為に、たとえば、特開昭６１−２３３３２号公報
には、フリップチップ型半導体装置において、半導体チ
ップを搭載する配線用基板にプローブテスト用配線を配
設し、バンプ電極を半田蒸着により短絡、その後ウェッ
トバックすることによりオープンすることで、前記配線
用基板のテスティングを容易にすることができる技術に
ついて記載されている。2. Description of the Related Art Conventionally, a semiconductor device formed by mounting a plurality of semiconductor chips of this kind is disclosed in, for example, Japanese Patent Application Laid-Open No. 61-232332, which discloses a flip chip type. In a semiconductor device, a wiring for a probe test is arranged on a wiring substrate on which a semiconductor chip is mounted, and the bump electrodes are short-circuited by solder vapor deposition and then opened by wet back to facilitate testing of the wiring substrate. It describes techniques that can be used.
【０００３】また、特開昭５８−１２８７５４号公報に
は、能動素子チップ搭載基板と受動素子搭載基板が組み
合わされて形成される混成集積回路において、能動素子
チップ搭載基板には、能動素子チップよりそれぞれ外部
取り出し電極が独立して引き出されており、受動素子基
板には、前記能動素子チップ搭載基板の外部取り出し電
極間を接続するための接続金属層があり、半田で接続す
ることにより、電気的に接続され回路が構成される。能
動素子チップ搭載基板には、各能動素子チップより独立
して外部取り出し電極がでているため、各能動素子チッ
プを単独で検査でき、良否判定が容易にできる。Japanese Patent Application Laid-Open No. 58-128754 discloses a hybrid integrated circuit formed by combining an active element chip mounting substrate and a passive element mounting substrate. The external extraction electrodes are independently drawn out, and the passive element substrate has a connection metal layer for connecting between the external extraction electrodes of the active element chip mounting substrate. To form a circuit. Since the active element chip mounting substrate is provided with an external extraction electrode independently of each active element chip, each active element chip can be inspected independently, and quality can be easily determined.
【０００４】[0004]
【発明が解決しようとする課題】従来の技術である特開
昭６１−２３３３２では、テスティングを容易にするた
めに、プローブテスト用の配線を引き出す必要があると
いう問題がある。その理由はテスティングのために、半
田バンプ電極間をショートさせるのに配線を使用してい
るためである。また、従来の技術である特開昭５８−１
２８７５４では、半導体チップ間を結線するのに、別の
基板が必要になるという問題がある。その理由は個々の
半導体チップより独立して外部取り出し電極がでている
ためである。本発明の目的は、複数個の半導体チップが
搭載される半導体装置において、テスティングを容易に
する技術を提供することにある。The conventional technique disclosed in Japanese Patent Application Laid-Open No. Sho 61-23332 has a problem that it is necessary to draw out a wiring for a probe test in order to facilitate testing. The reason for this is that wiring is used for short-circuiting between the solder bump electrodes for testing. In addition, Japanese Patent Application Laid-Open No. 58-1
In 28754, there is a problem that another substrate is required to connect the semiconductor chips. The reason for this is that external extraction electrodes are provided independently of the individual semiconductor chips. An object of the present invention is to provide a technique for facilitating testing in a semiconductor device on which a plurality of semiconductor chips are mounted.
【０００５】[0005]
【課題を解決するための手段】本発明は、半導体チップ
が複数個搭載されて形成されるボールグリッドアレイ構
造の半導体装置において、半導体チップ間で結線される
配線を分離して別々に半田バンプ形成ランドの分割され
たランドに接続されて形成された基板と、前記基板上に
前記半導体チップが搭載され、基板上のパターンと半導
体チップ間を接続する金属ワイヤと前記半導体チップを
覆うエポキシ樹脂を有し、前記分割された半田バンプ形
成ランドをテスティングに使用し、前記分割ランドを半
田バンプで接続することを特徴とする半導体装置であ
る。また、本発明は、上記の半導体装置の複数個搭載さ
れる半導体チップが、ｎ個の半導体チップ間が結線され
る場合、半田バンプ形成ランドはｎ等分した形状である
ことを特徴とするものである。SUMMARY OF THE INVENTION The present invention relates to a semiconductor device having a ball grid array structure formed by mounting a plurality of semiconductor chips, and separately forming solder bumps by separating wirings connected between the semiconductor chips. A substrate formed by being connected to the divided lands of the land; a semiconductor chip mounted on the substrate; metal wires connecting the pattern on the substrate to the semiconductor chip; and an epoxy resin covering the semiconductor chip. The divided solder bump forming lands are used for testing, and the divided lands are connected by solder bumps. Further, the present invention is characterized in that, when a plurality of semiconductor chips of the above-mentioned semiconductor device are connected between n semiconductor chips, the solder bump forming lands are shaped equally into n. It is.
【０００６】[0006]
【作用】本発明においては、半導体バンプが形成される
ランドを分割して形成し、半導体チップ間で結線される
配線を分離して、別々に前記分割ランドに引き出すこと
により、半導体チップを単独でテスティングすることが
できる。また、半田ボール等により前記分割ランドに半
田バンプを形成することで電気的に接続することができ
ることにより、ユーザー不要な半田バンプを少なくする
ことができ、また、ユーザーでの配線が不要となるもの
である。In the present invention, the lands on which the semiconductor bumps are formed are formed separately, the wirings connected between the semiconductor chips are separated, and the wirings are separately drawn out to the divided lands, so that the semiconductor chips are singly separated. Can be tested. Further, by forming solder bumps on the divided lands with solder balls or the like, electrical connection can be made, so that solder bumps unnecessary for the user can be reduced, and wiring for the user is unnecessary. It is.
【０００７】[0007]
【発明の実施の形態】本発明の半導体装置は、ＢＧＭ
（ボールグリッドアレイ）構造において、半田バンプが
形成されるランドを分割して形成し、半導体チップ間で
結線される配線を分離して、別々に前記分割ランドに引
き出すものであり、その後、半導体チップを搭載し、前
記分割ランドを使用してテスティングを行い、半田ボー
ル等で半田バンプを形成する。その時半田バンプにより
前記分割ランドが電気的に接続されるものであり、その
実施の形態について図面を参照して詳細に説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device according to the present invention has a BGM
In the (ball grid array) structure, lands on which solder bumps are formed are divided and formed, and wirings connected between semiconductor chips are separated and separately drawn to the divided lands. , And testing is performed using the divided lands, and solder bumps are formed with solder balls or the like. At that time, the divided lands are electrically connected by solder bumps, and an embodiment thereof will be described in detail with reference to the drawings.
【０００８】[0008]
【実施例１】本発明の第１の実施例を図１、図２で説明
する。図１（Ａ）は、本発明の第１の実施例を示すブロ
ック図の一部分である。図１（Ｂ）は、本発明の第１の
実施例の裏面からの平面図、（Ｃ）は、（Ｂ）をＸ−
Ｘ’線で切断したときの断面図、（Ｄ）は、（Ｂ）の分
割ランドの拡大図である。また、図２（Ａ），（Ｂ）
は、本発明の第１の実施例の半田バンプ形成を示す断面
図である。Embodiment 1 A first embodiment of the present invention will be described with reference to FIGS. FIG. 1A is a part of a block diagram showing a first embodiment of the present invention. FIG. 1B is a plan view from the back surface of the first embodiment of the present invention, and FIG.
FIG. 4D is a cross-sectional view taken along the line X ′, and FIG. 4D is an enlarged view of the divided land shown in FIG. FIGS. 2A and 2B
FIG. 2 is a cross-sectional view showing the formation of a solder bump according to the first embodiment of the present invention.
【０００９】まず図１について、図１（Ａ）に示すよう
に、回路上、半導体チップ１間で結線される配線ａ、ｂ
を図１（Ｂ）に示す基板（セラミック基板又はガラスエ
ポキキシ基板）２上で結線しないで、別々に基板２の半
田バンプ形成ランド３ａ、３ｂに引き出す。半田バンプ
形成ランド３ａ、３ｂの形状は、分割ランドの拡大図を
示す図１（Ｄ）のように、同一サイズの半円であり、サ
イズは分割されていない半田バンプ形成ランド３と同一
サイズである。半田バンプ形成ランド３ａ、３ｂの間の
スリット４のサイズは、０．１〜０．１５ｍｍの範囲で
ある。First, referring to FIG. 1, as shown in FIG. 1A, wirings a and b connected between the semiconductor chips 1 are formed on the circuit.
Are separately drawn out to the solder bump formation lands 3a and 3b of the substrate 2 without being connected on the substrate (ceramic substrate or glass epoxy substrate) 2 shown in FIG. The shape of the solder bump formation lands 3a and 3b is a semicircle of the same size as shown in FIG. 1D showing an enlarged view of the divided land, and the size is the same as that of the undivided solder bump formation land 3. is there. The size of the slit 4 between the solder bump formation lands 3a and 3b is in the range of 0.1 to 0.15 mm.
【００１０】また、図１（Ｃ）の断面図に示すように、
半導体チップ１を基板２上に搭載し、金属ワイヤ５で前
記半導体チップ１と基板２の配線パターン間を電気的に
接続して、エポキシ樹脂６で充填する。その後、図１
（Ｂ）に示す半田バンプ形成ランド３ａ、３ｂ及び他の
分割されていない半田バンプ形成ランド３にテスティン
グ用のプローバを立てて、半導体チップ１のテスティン
グを実施する。Further, as shown in the sectional view of FIG.
The semiconductor chip 1 is mounted on the substrate 2, the wiring between the semiconductor chip 1 and the wiring pattern of the substrate 2 is electrically connected with the metal wires 5, and the semiconductor chip 1 is filled with the epoxy resin 6. Then, FIG.
A testing prober is set up on the solder bump formation lands 3a and 3b and the other undivided solder bump formation lands 3 shown in FIG. 3B, and the semiconductor chip 1 is tested.
【００１１】次に、本発明の半導体装置の製造工程につ
いて、図１、図２を参照して説明する。上述した図１
（Ｂ）に示す半田バンプ形成ランド３ａ、３ｂにテステ
ィング用のプローバを立てて、半導体チップ１のテステ
ィングを実施した後、図２（Ａ）に示すように、半田ボ
ール７を前記半田バンプ形成ランド３ａ、３ｂ上に搭載
して、リフロー装置に通すことで半田ボール７を溶融さ
せて、図２（Ｂ）に示す半田バンプ８を形成する。この
時、半田バンプ形成ランド３ａ、３ｂが半田バンプ８に
より、電気的に接続され、半導体装置が形成される。ま
た、前記半田ボール７の替わりに半田ペーストを使用し
ても同じ効果が得られる。Next, a manufacturing process of the semiconductor device of the present invention will be described with reference to FIGS. FIG. 1 described above
After testing the semiconductor chip 1 by setting up a prober for testing on the solder bump formation lands 3a and 3b shown in FIG. 2B, as shown in FIG. The solder balls 7 are mounted on the formation lands 3a and 3b and passed through a reflow device to melt the solder balls 7, thereby forming the solder bumps 8 shown in FIG. 2B. At this time, the solder bump formation lands 3a and 3b are electrically connected by the solder bumps 8, and a semiconductor device is formed. The same effect can be obtained by using a solder paste instead of the solder ball 7.
【００１２】[0012]
【実施例２】本発明の第２の実施例を図３で説明する。
図３（Ａ）は、本発明の第２の実施例を示すブロック図
の一部分であり、（Ｂ）は分割ランドの拡大図である。
上述した第１の実施例を示した図１では、２個の半導体
チップ間で結線される配線について説明したが、図３で
は、３個の半導体チップ１間が結線される場合について
説明する。３個の半導体チップ間で結線される配線ａ、
ｂ、ｃを半田バンプ形成ランド３ａ、３ｂ、３ｃに引き
出す。半田バンプ形成ランド３ａ、３ｂ、３ｃの形状
は、分割されていない半田バンプ形成ランド３を３等分
した形状である。また、４個の半導体チップ１間が結線
される場合は、半田バンプ形成ランド３は４等分した形
状であり、ｎ個の半導体チップ１間が結線される場合
は、ｎ等分した形状である。Second Embodiment A second embodiment of the present invention will be described with reference to FIG.
FIG. 3A is a part of a block diagram showing a second embodiment of the present invention, and FIG. 3B is an enlarged view of a divided land.
Although FIG. 1 showing the first embodiment described above describes the wiring connected between two semiconductor chips, FIG. 3 describes the case where three semiconductor chips 1 are connected. A wiring a connected between the three semiconductor chips,
b and c are drawn out to the solder bump formation lands 3a, 3b and 3c. The shape of the solder bump formation lands 3a, 3b, 3c is a shape obtained by dividing the undivided solder bump formation lands 3 into three equal parts. When the four semiconductor chips 1 are connected, the solder bump formation land 3 has a shape equally divided into four, and when the n semiconductor chips 1 are connected, the solder bump formation land 3 has the shape equally divided into n. is there.
【００１３】[0013]
【発明の効果】本発明によれば、復数個の半導体チップ
が搭載されて形成される半導体装置のテスティングが容
易にできるという効果を有する。これは半導体チップ間
で結線される配線を分離して、別々に半田バンプの分割
ランドに引き出していることより、各半導体チップが独
立しており、単独でテスティングができるためである。
また、半導体装置のテスティングを容易にするために、
ユーザーに不要な半田バンプを少なくできることと、ユ
ーザー側で半導体チップ間を接続するための配線をする
必要がなくなるという効果を有する。これは半田ボール
等により半田バンプを形成することにより、分割ランド
を電気的に接続することができるためである。According to the present invention, it is possible to easily test a semiconductor device formed by mounting several semiconductor chips. This is because the wiring connected between the semiconductor chips is separated and is separately drawn out to the divided lands of the solder bumps, so that each semiconductor chip is independent and testing can be performed independently.
In addition, to facilitate testing of semiconductor devices,
This has the effect of reducing the number of solder bumps unnecessary for the user and eliminating the need for the user to perform wiring for connecting the semiconductor chips. This is because the divided lands can be electrically connected by forming solder bumps with solder balls or the like.
【図１】 本発明の第１の実施を示す図FIG. 1 shows a first embodiment of the present invention.
【図２】 本発明の第１の実施を示す図FIG. 2 is a diagram showing a first embodiment of the present invention.
【図３】 本発明の第１の実施を示す図FIG. 3 shows a first embodiment of the present invention.
１ 半導体チップ ２ 基板 ３ 半田バンプ形成ランド ４ スリット ５ 金属ワイヤ ６ エポキシ樹脂 ７ 半田ボール ８ 半田バンプ DESCRIPTION OF SYMBOLS 1 Semiconductor chip 2 Substrate 3 Land for forming solder bumps 4 Slit 5 Metal wire 6 Epoxy resin 7 Solder ball 8 Solder bump
Claims (2)
れるボールグリッドアレイ構造の半導体装置において、
半導体チップ間で結線される配線を分離して別々に半田
バンプ形成ランドの分割されたランドに接続されて形成
された基板と、前記基板上に前記半導体チップが搭載さ
れ、基板上のパターンと半導体チップ間を接続する金属
ワイヤと前記半導体チップを覆うエポキシ樹脂を有し、
前記分割された半田バンプ形成ランドをテスティングに
使用し前記分割ランドを半田バンプで接続したことを特
徴とする半導体装置。In a semiconductor device having a ball grid array structure formed by mounting a plurality of semiconductor chips,
A substrate formed by separately connecting wires connected between semiconductor chips and separately connected to the divided lands of the solder bump formation lands; and the semiconductor chip mounted on the substrate, and a pattern on the substrate and a semiconductor. Having a metal wire connecting the chips and an epoxy resin covering the semiconductor chip,
A semiconductor device, wherein the divided solder bump forming lands are used for testing, and the divided lands are connected by solder bumps.
の半導体チップ間が結線される場合、半田バンプ形成ラ
ンドはｎ等分した形状であることを特徴とする請求項１
に記載の半導体装置。2. The semiconductor device according to claim 1, wherein when a plurality of semiconductor chips are connected between n semiconductor chips, the solder bump forming lands have a shape equally divided into n.
3. The semiconductor device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17185296A JP2765567B2 (en) | 1996-06-11 | 1996-06-11 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17185296A JP2765567B2 (en) | 1996-06-11 | 1996-06-11 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH09330993A true JPH09330993A (en) | 1997-12-22 |
| JP2765567B2 JP2765567B2 (en) | 1998-06-18 |
Family
ID=15930979
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17185296A Expired - Fee Related JP2765567B2 (en) | 1996-06-11 | 1996-06-11 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2765567B2 (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6018462A (en) * | 1997-06-30 | 2000-01-25 | Nec Corporation | Multi-tip module |
| EP1030365A1 (en) * | 1997-10-17 | 2000-08-23 | Ibiden Co., Ltd. | Package substrate |
| US6798078B2 (en) * | 2000-12-14 | 2004-09-28 | Yamaha Hatsudoki Kabushiki Kaisha | Power control device with semiconductor chips mounted on a substrate |
| US6927491B1 (en) | 1998-12-04 | 2005-08-09 | Nec Corporation | Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board |
| WO2005076319A3 (en) * | 2004-02-04 | 2005-11-10 | Infineon Technologies Ag | Semiconductor component comprising a semiconductor chip stack on a wiring frame and method for producing the same |
| JP2012074635A (en) * | 2010-09-29 | 2012-04-12 | Toppan Printing Co Ltd | Method of inspecting semiconductor package substrate, method of manufacturing semiconductor package substrate, and semiconductor package substrate |
-
1996
- 1996-06-11 JP JP17185296A patent/JP2765567B2/en not_active Expired - Fee Related
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6018462A (en) * | 1997-06-30 | 2000-01-25 | Nec Corporation | Multi-tip module |
| EP1030365A1 (en) * | 1997-10-17 | 2000-08-23 | Ibiden Co., Ltd. | Package substrate |
| USRE41051E1 (en) | 1997-10-17 | 2009-12-22 | Ibiden Co., Ltd. | Package substrate |
| USRE41242E1 (en) | 1997-10-17 | 2010-04-20 | Ibiden Co., Ltd. | Package substrate |
| US6927491B1 (en) | 1998-12-04 | 2005-08-09 | Nec Corporation | Back electrode type electronic part and electronic assembly with the same mounted on printed circuit board |
| US6798078B2 (en) * | 2000-12-14 | 2004-09-28 | Yamaha Hatsudoki Kabushiki Kaisha | Power control device with semiconductor chips mounted on a substrate |
| WO2005076319A3 (en) * | 2004-02-04 | 2005-11-10 | Infineon Technologies Ag | Semiconductor component comprising a semiconductor chip stack on a wiring frame and method for producing the same |
| US7521809B2 (en) | 2004-02-04 | 2009-04-21 | Infineon Technologies Ag | Semiconductor device having a chip stack on a rewiring plate |
| JP2012074635A (en) * | 2010-09-29 | 2012-04-12 | Toppan Printing Co Ltd | Method of inspecting semiconductor package substrate, method of manufacturing semiconductor package substrate, and semiconductor package substrate |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2765567B2 (en) | 1998-06-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6765228B2 (en) | Bonding pad with separate bonding and probing areas | |
| US5942795A (en) | Leaded substrate carrier for integrated circuit device and leaded substrate carrier device assembly | |
| JP2825085B2 (en) | Semiconductor device mounting structure, mounting board, and mounting state inspection method | |
| JP2988075B2 (en) | Semiconductor device | |
| US20050082657A1 (en) | Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same | |
| US5744383A (en) | Integrated circuit package fabrication method | |
| JP2006128597A (en) | Structure of chip-size package and method of forming thereof | |
| JP3063687B2 (en) | Multi-chip module | |
| JP3566957B2 (en) | Semiconductor device and manufacturing method thereof | |
| JP2002118205A (en) | Ball grid array package and circuit board used therefor | |
| JP3927783B2 (en) | Semiconductor parts | |
| JP2765567B2 (en) | Semiconductor device | |
| KR100548554B1 (en) | Test vehicle ball grid array package | |
| JP2006278374A (en) | Semiconductor device and packaging structure thereof | |
| JP2003017495A (en) | Semiconductor device and method for manufacturing the same | |
| JPH07226418A (en) | Chip carrier semiconductor device and its manufacture | |
| JP3949077B2 (en) | Semiconductor device, substrate, semiconductor device manufacturing method, and semiconductor device mounting method | |
| US20010040297A1 (en) | Multiple line grid for use in a packaging of a testing application | |
| JP2571023B2 (en) | BGA type semiconductor device | |
| JPH0744243B2 (en) | Semiconductor integrated circuit module | |
| JP2001135795A (en) | Semiconductor device | |
| JPS59117252A (en) | Semiconductor device | |
| JPH08250620A (en) | Semiconductor device | |
| JP3485424B2 (en) | IC package | |
| JPH11224915A (en) | Substrate for semiconductor connection |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |