JPH09246426A - Surface mounted type electronic component, wiring board, mounting board and mounting method - Google Patents

Surface mounted type electronic component, wiring board, mounting board and mounting method

Info

Publication number
JPH09246426A
JPH09246426A JP7329096A JP7329096A JPH09246426A JP H09246426 A JPH09246426 A JP H09246426A JP 7329096 A JP7329096 A JP 7329096A JP 7329096 A JP7329096 A JP 7329096A JP H09246426 A JPH09246426 A JP H09246426A
Authority
JP
Japan
Prior art keywords
mounting
bumps
electronic component
electrodes
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP7329096A
Other languages
Japanese (ja)
Inventor
Sumiko Shimizu
須美子 清水
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP7329096A priority Critical patent/JPH09246426A/en
Publication of JPH09246426A publication Critical patent/JPH09246426A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/0266Marks, test patterns or identification means
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/11Printed elements for providing electric connections to or between printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components

Abstract

PROBLEM TO BE SOLVED: To facilitate breakage check between a surface mounted type electronic component and a wiring board, by providing a single or a plurality of bump conduction connection means for conducting and connecting different dummy bumps. SOLUTION: In an IC package with bump 32, for example, an IC chip 41 is mounted on one surface 40A of a circuit board 40 by a wire bonding method and is sealed by a sealing resin 42, such as, epoxy, and bumps 43 are provided in two columns on the other surface 40B of the circuit board 40 along peripheral edge portions of the other surface 40B. The bumps 43, except for four dummy testing bumps 43A to 43D arranged at the corners of the circuit board 40, are electrically connected via through-holes to corresponding electrodes formed on the side of the one surface 40A of the circuit board 40. (The electrodes are conducted and connected to corresponding electrodes of the IC chip 41 via metal wires 44 made of a gold material).

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【目次】以下の順序で本発明を説明する。 発明の属する技術分野 従来の技術(図5〜図8) 発明が解決しようとする課題(図5〜図8) 課題を解決するための手段(図1〜図4) 発明の実施の形態(図1〜図4) 発明の効果[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional technology (FIGS. 5 to 8) Problems to be solved by the invention (FIGS. 5 to 8) Means for solving the problems (FIGS. 1 to 4) Embodiments of the invention (FIGS. 1 to 4) Effect of the invention

【0002】[0002]

【発明の属する技術分野】本発明は表面実装型電子部
品、配線基板、実装基板及び実装方法に関し、例えばB
GA(Ball Grid Array )及びCSP(Chip Size Pack
age )などのような、一面に信号入出力用の複数のバン
プを有し、フエースダウンで実装するICパツケージ、
当該ICパツケージに対応するプリント配線板、このI
Cパツケージがプリント配線板に実装されてなる実装基
板及びこのICパツケージの実装方法に適用して好適な
ものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a surface mount type electronic component, a wiring board, a mounting board and a mounting method.
GA (Ball Grid Array) and CSP (Chip Size Pack)
age) etc., IC package that has multiple bumps for signal input / output on one surface and is mounted by face-down,
A printed wiring board corresponding to the IC package, I
It is suitable to be applied to a mounting board in which a C package is mounted on a printed wiring board and a mounting method of this IC package.

【0003】[0003]

【従来の技術】従来、ICチツプをプリント配線板に実
装するためのICパツケージの1つとして、プラスチツ
クQSP(Quad Flat Package )がある。通常、この種
のICパツケージにおいては、図5に示すように、パツ
ケージ本体部2の各周側面にガルウイング状にフオーミ
ングされた複数のリード3が所定ピツチで突出形成され
ることにより構成されており、現在ではこのQFP1が
ICパツケージの主流を占めている。
2. Description of the Related Art Conventionally, as one of IC packages for mounting an IC chip on a printed wiring board, there is a plastic QSP (Quad Flat Package). Normally, in this type of IC package, as shown in FIG. 5, a plurality of leads 3 formed in a gull wing shape are formed on a peripheral side surface of the package main body 2 by a predetermined pitch so as to project therefrom. At present, this QFP1 is the mainstream of IC packages.

【0004】ところがQFP1においては、近年の半導
体素子の高集積化及び多ピン化に伴いつてリード2の狭
ピツチ化が進んでおり、高度な実装技術が必要となつて
きている。このため近年では、既存の実装技術で容易に
実装できるICパツケージとして、例えばBGAやCS
Pが注目されている。
However, in the QFP 1, the lead 2 is becoming narrower with the recent trend toward higher integration and higher pin count of semiconductor elements, which requires advanced packaging technology. Therefore, in recent years, as an IC package that can be easily mounted by the existing mounting technology, for example, BGA or CS.
P is receiving attention.

【0005】実際上図6に示すように、BGA10にお
いては、回路基板11の一面11A上にワイヤボンデイ
ング法によりICチツプ12が実装されると共に、当該
ICチツプ12がエポキシ等の封止樹脂13により封止
され(又はICチツプ12に金属等のキヤツプが被せら
れ)、かつ回路基板11の他面側に金属ボールでなる突
起電極(以下、これをバンプと呼ぶ)14が例えば1.5
〔mm〕程度のピツチでマトリクス状に形成されることに
より構成されている。
Actually, as shown in FIG. 6, in the BGA 10, the IC chip 12 is mounted on the one surface 11A of the circuit board 11 by the wire bonding method, and the IC chip 12 is sealed by the sealing resin 13 such as epoxy. A protrusion electrode (hereinafter referred to as a bump) 14 formed of a metal ball is sealed (or the IC chip 12 is covered with a cap such as a metal), and the other surface of the circuit board 11 is, for example, 1.5.
It is formed by forming a matrix with pitches of about [mm].

【0006】この場合各バンプ14は、それぞれ回路基
板11の一面11A側に形成された対応する電極(それ
ぞれ金材からなる金属線15を介してICチツプ12の
対応する電極と導通接続されている)と内層やスルーホ
ール等を介して電気的に接続されている。
In this case, each bump 14 is electrically connected to a corresponding electrode formed on one surface 11A of the circuit board 11 (a corresponding electrode of the IC chip 12 via a metal wire 15 made of a gold material). ) Is electrically connected to the inner layer and through holes.

【0007】かくしてBGA10においては、プリント
配線板の所定位置にフエースダウンで位置決めマウント
した後、プリント配線板の対応する電極上に予め供給さ
れたはんだ(及び又は各バンプ14)を加熱溶融し、こ
れらバンプ14をそれぞれプリント配線板の対応する電
極と接合することにより実装することができるため、従
来の実装技術の範囲内で容易に実装し得る利点がある。
Thus, in the BGA 10, after positioning and mounting the printed wiring board at a predetermined position by face-down, the solder (and / or each bump 14) previously supplied on the corresponding electrode of the printed wiring board is melted by heating. Since the bumps 14 can be mounted by being joined to the corresponding electrodes of the printed wiring board, there is an advantage that they can be easily mounted within the range of the conventional mounting technology.

【0008】一方SCPは、BGA10と同様の回路基
板や金属箔を積層したポリイミド等の絶縁フイルムを用
い、当該回路基板又は絶縁フイルムの一面側に実装面積
が大きくならないようにフリツプチツプ法によりICチ
ツプを実装すると共に、回路基板又は絶縁フイルムの他
面側に金属ボールでなるバンプを例えば0.5 〔mm〕ピツ
チでマトリクス状に形成することにより構成されてお
り、全体としてほぼICチツプとほぼ同等の大きさに形
成されている。
On the other hand, the SCP uses an insulating film made of polyimide or the like in which a circuit board similar to the BGA 10 or a metal foil is laminated, and an IC chip is formed by a flip chip method so that the mounting area does not become large on one side of the circuit board or the insulating film. It is mounted and mounted on the other side of the circuit board or insulating film by forming bumps made of metal balls in a matrix shape with, for example, 0.5 [mm] pitches, and is approximately the same size as an IC chip as a whole. Is formed in.

【0009】従つてこのSCPにおいても、BGA10
と同様にしてプリント配線板上に実装でき、従来の実装
技術で容易に実装することができる。なお図7にBGA
10(図6)やCSPのようなパツケージ本体部16の
裏面16A側に信号入出力用のバンプ17が複数設けら
れたICパツケージ(以下、これをバンプ付ICパツケ
ージと呼ぶ)18の裏面構成例を示し、図8にプリント
配線板19にこのようなバンプ付ICパツケージ18が
複数実装されてなる従来の実装基板20の構成例を示
す。
Therefore, even in this SCP, the BGA10
It can be mounted on a printed wiring board in the same manner as, and can be easily mounted by a conventional mounting technique. Note that the BGA is shown in FIG.
10 (FIG. 6) and an example of the back surface configuration of an IC package (hereinafter, referred to as an IC package with bumps) 18 in which a plurality of signal input / output bumps 17 are provided on the back surface 16A side of the package body 16 such as CSP. FIG. 8 shows a configuration example of a conventional mounting substrate 20 in which a plurality of such IC packages with bumps 18 are mounted on a printed wiring board 19.

【0010】[0010]

【発明が解決しようとする課題】ところで、例えばQF
P1(図5)のようにリード3がガルウイングタイプの
ICパツケージでは、各リード3とプリント配線板の対
応する電極との接合部がICパツケージの周囲に露出し
た状態にあるため、当該接合部の接合状態(破断の有無
等)を目視により確認することができる。
By the way, for example, QF
In an IC package in which the leads 3 are gull-wing type as shown in P1 (FIG. 5), the joint between each lead 3 and the corresponding electrode of the printed wiring board is exposed in the periphery of the IC package. It is possible to visually confirm the joining state (presence or absence of breakage, etc.).

【0011】ところがBGA10(図6)やCSPのよ
うなバンプ付ICパツケージ18(図7)においては、
上述のようにパツケージ本体部16の裏面16A側にバ
ンプ17が形成され、フエイスダウンで実装するため、
実装後、各ハンプ17とプリント配線板19(図8)の
対応する電極との接合部がパツケージ本体部16により
覆われてしまい目視し難い問題があつた。
However, in the IC package 18 with bumps (FIG. 7) such as the BGA 10 (FIG. 6) or the CSP,
As described above, since the bumps 17 are formed on the back surface 16A side of the package body 16 and mounted by face-down,
After mounting, the joint between each hump 17 and the corresponding electrode of the printed wiring board 19 (FIG. 8) was covered by the package body 16 and was difficult to see.

【0012】従つて従来では、このようなバンプ付IC
パツケージ18(図7)に対するプリント配線板19
(図8)との接合部の破断状態の検査を、回路に信号を
送り、1つ1つICの動作確認をすることにより行われ
おり、このためこのような破断状態の検査作業が煩雑か
つ多くの時間を要する問題があつた。またパンプ付IC
パツケージ18(図7)に対するプリント配線板19
(図8)との破断状態の確認作業は、ICテスタ等の専
用の治具や検査装置を必要とするため、コストがかかる
問題もあつた。
Therefore, conventionally, such an IC with bumps is used.
Printed wiring board 19 for package 18 (FIG. 7)
The broken state of the joint with (Fig. 8) is inspected by sending a signal to the circuit to check the operation of each IC one by one. Therefore, the inspection work of such a broken state is complicated. There was a problem that took a lot of time. IC with pump
Printed wiring board 19 for package 18 (FIG. 7)
The work of confirming the broken state with (FIG. 8) requires a dedicated jig such as an IC tester or an inspection device, which causes a problem that the cost is high.

【0013】本発明は以上の点を考慮してなされたもの
で、破断検査を簡易化させ得る表面実装型電子部品、配
線基板、実装基板及び実装方法を提案しようとするもの
である。
The present invention has been made in view of the above points, and an object thereof is to propose a surface mounting type electronic component, a wiring board, a mounting board, and a mounting method capable of simplifying a fracture inspection.

【0014】[0014]

【課題を解決するための手段】かかる課題を解決するた
め第1の発明においては、一面側に信号入出力用の複数
のバンプが形成された表面実装型電子部品において、複
数のダミーバンプを一面側に設けると共に、これらダミ
ーバンプのうち、それぞれ異なる一対のダミーバンプを
単数又は複数のバンプ導通接続手段により導通接続する
ようにした。
In order to solve such a problem, in a first aspect of the invention, a plurality of dummy bumps are provided on one surface side in a surface mount type electronic component having a plurality of signal input / output bumps formed on one surface side. Of the dummy bumps, a pair of different dummy bumps are conductively connected by a single or a plurality of bump conductive connecting means.

【0015】また第2の発明においては、第1の発明の
表面実装型電子部品に対応する配線基板として、各ダミ
ーバンプにそれぞれ対応する複数の第2の電極と、それ
ぞれ異なる所定の第1の電極と導電接続された第3及び
第4の電極とを実装面に形成すると共に、表面実装電子
部品が実装されたときに、第2の電極、ダミーバンプ及
びバンプ導通接続手段と共に第3及び第4の電極を導通
接続する一繋ぎの導電路を形成するように、それぞれ異
なる一対の第2の電極を導通接続する単数又は複数の電
極導電接続手段を設けるようにした。
In the second invention, as the wiring board corresponding to the surface mount type electronic component of the first invention, a plurality of second electrodes respectively corresponding to the dummy bumps and predetermined first electrodes different from each other are provided. A third electrode and a fourth electrode conductively connected to the mounting surface, and when the surface-mounted electronic component is mounted, the third electrode and the dummy bump and the bump conductive connecting means together with the third and fourth electrodes are formed. A single or a plurality of electrode conductive connection means for conductively connecting a pair of different second electrodes are provided so as to form a continuous conductive path for conductively connecting the electrodes.

【0016】さらに第3の発明においては、第1の発明
の表面実装型電子部品を第2の発明の配線基板に実装す
るようにして実装基板を形成するようにした。
Further, in the third invention, the mounting board is formed by mounting the surface mount type electronic component of the first invention on the wiring board of the second invention.

【0017】さらに第4の発明においては、一面側に信
号入出力用の複数のバンプが形成された表面実装型電子
部品を配線基板の実装面に実装する実装方法において、
表面実装型電子部品の一面側に複数のダミーバンプを設
けると共に、異なる一対のダミーバンプを単数又は複数
のバンプ導通接続手段により導通接続する一方、配線基
板の実装面にこれら各ダミーバンプにそれぞれ対応する
複数の第2の電極と、それぞれ異なる所定の第1の電極
と導電接続された第3及び第4の電極とを形成し、かつ
表面実装電子部品が実装されたときに、第2の電極、ダ
ミーバンプ及びバンプ導通接続手段と共に第3及び第4
の電極を導通接続する一繋ぎの導電路を形成するよう
に、異なる一対の第2の電極を単数又は複数の電極導電
接続手段により導通接続する第1のステツプと、これを
配線基板上に実装する第2のステツプとを設けるように
した。
Further, in a fourth aspect of the present invention, there is provided a mounting method for mounting a surface mounting type electronic component having a plurality of bumps for signal input / output formed on one surface thereof on a mounting surface of a wiring board.
A plurality of dummy bumps are provided on one surface side of the surface-mounted electronic component, and a pair of different dummy bumps are electrically connected by a single or a plurality of bump conduction connection means, while a plurality of dummy bumps corresponding to the dummy bumps are provided on the mounting surface of the wiring board. A second electrode, a third electrode and a fourth electrode which are conductively connected to different first electrodes, respectively, are formed, and when the surface mount electronic component is mounted, the second electrode, the dummy bump, and Third and fourth together with bump conduction connecting means
And a first step for conductively connecting a pair of different second electrodes by one or a plurality of electrode conductive connecting means so as to form a continuous conductive path for conductively connecting the electrodes of FIG. The second step is provided.

【0018】この場合第1及び第2の発明においては、
第1の発明の表面実装型電子部品を第2の発明の配線基
板に実装したときに、表面実装型電子部品の各ダミーバ
ンプ及びバンプ導通接続手段と、配線基板の第2の電極
及び電極導通接続手段とによつて配線基板の第3及び第
4の電極間を導通接続する導通路が形成される。
In this case, in the first and second inventions,
When the surface-mounted electronic component of the first invention is mounted on the wiring board of the second invention, each dummy bump and bump conduction connection means of the surface-mounted electronic component, and the second electrode and electrode conduction connection of the wiring board. By means of the means, a conduction path for electrically connecting the third and fourth electrodes of the wiring board is formed.

【0019】従つて例えばダミーバンプのいずれか1つ
でも破断している場合には第3及び第4の電極間の抵抗
値が破断していない場合に比べて大きい値を示すため、
第3及び第4の電極間の抵抗値を測定するだけで各ダミ
ーバンプに破断が生じているか否かを検査することがで
き、かくしてこのダミーバンプをサンプルとして、表面
実装型電子部品及び配線基板間の破断検査を行うことが
できる。
Therefore, for example, when any one of the dummy bumps is broken, the resistance value between the third and fourth electrodes is larger than that when it is not broken.
It is possible to inspect whether or not each dummy bump is broken by simply measuring the resistance value between the third and fourth electrodes, and thus, using this dummy bump as a sample, between the surface mount electronic component and the wiring board. Breakage inspection can be performed.

【0020】また第3及び第4の発明においても、第3
及び第4の電極間の抵抗値を測定するだけで各ダミーバ
ンプに破断が生じているか否かを検査することができ、
かくしてこのダミーバンプをサンプルとして、実装基板
の破断検査を行うことができる。
Also in the third and fourth inventions, the third
And, it is possible to inspect whether or not each dummy bump is broken only by measuring the resistance value between the fourth electrode,
In this way, it is possible to perform a breakage inspection of the mounting substrate using this dummy bump as a sample.

【0021】[0021]

【発明の実施の形態】以下図面について、本発明の一実
施例を詳述する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

【0022】図1において、30は全体として実施例に
よる実装基板を示し、所定の配線パターンが形成された
プリント配線板31の実装面31A上に複数のバンプ付
ICパツケージ32が実装されることにより形成されて
いる。バンプ付ICパツケージ32においては、それぞ
れ図2及び図3に示すように、回路基板40の一面40
A上にワイヤボンデイング法によりICチツプ41が実
装されると共に、このICチツプ41がエポキシ等の封
止樹脂42により封止され、かつ回路基板40の他面4
0B側にバンプ43が当該他面40Bの周端部に沿つて
2列に並べて設けられることにより形成されている。
In FIG. 1, reference numeral 30 generally indicates a mounting board according to the embodiment, and a plurality of IC packages 32 with bumps are mounted on a mounting surface 31A of a printed wiring board 31 on which a predetermined wiring pattern is formed. Has been formed. In the bumped IC package 32, as shown in FIGS. 2 and 3, respectively, one surface 40 of the circuit board 40
An IC chip 41 is mounted on A by a wire bonding method, the IC chip 41 is sealed with a sealing resin 42 such as epoxy, and the other surface 4 of the circuit board 40 is sealed.
The bumps 43 are formed on the 0B side by being arranged in two rows along the peripheral edge portion of the other surface 40B.

【0023】この各バンプ43は、回路基板40の他面
40Bの各隅部にそれぞれ配置された4つのダミーバン
プ(以下、これらそれぞれ第1〜第4の検査用バンプと
呼ぶ)43A〜43D(図3)を除いて、それぞれ回路
基板40の一面40A側に形成された対応する電極(そ
れぞれ金材からなる金属線44を介してICチツプ41
の対応する電極と導通接続されている)とスルーホール
(図示せず)を介して電気的に接続されている。
Each of the bumps 43 is composed of four dummy bumps (hereinafter, referred to as first to fourth inspection bumps) 43A to 43D respectively arranged at the corners of the other surface 40B of the circuit board 40. 3) except for the corresponding electrodes formed on the one surface 40A side of the circuit board 40 (the IC chip 41 via the metal wires 44 each made of a gold material).
Are electrically connected to the corresponding electrodes of the above) and are electrically connected through through holes (not shown).

【0024】また特に図3において明らかなように、第
1及び2の検査用バンプ43A、43Bは回路基板40
の他面40Bに形成された配線ライン45Aを介して導
通接続されると共に、これと同様に、第3及び第4の検
査用バンプ43C、43Dも配線ライン45Bを介して
導通接続されている。
Further, as is particularly apparent in FIG. 3, the first and second inspection bumps 43A and 43B are formed on the circuit board 40.
While being conductively connected via the wiring line 45A formed on the other surface 40B, similarly, the third and fourth inspection bumps 43C and 43D are also conductively connected via the wiring line 45B.

【0025】一方プリント配線板31においては、実装
面31Aに各バンプ付ICパツケージ32の各バンプ4
3にそれぞれ対応させてランド50が形成されている。
この場合これら各ランド50のうち、バンプ付ICパツ
ケージ32の第1の検査用ピン43Aが接合されるラン
ド(以下、これを第1の検査用ランドと呼ぶ)50A
と、バンプ付ICパツケージ32の第3の検査用ピン4
3Cが接合されるランド(以下、これを第3の検査用ラ
ンドと呼ぶ)50Cは配線ライン51により導通接続さ
れている。
On the other hand, in the printed wiring board 31, the bumps 4 of the IC package 32 with bumps are mounted on the mounting surface 31A.
Lands 50 are formed so as to correspond to the respective Nos. 3 and 3.
In this case, of these lands 50, a land to which the first inspection pin 43A of the IC package 32 with bumps is bonded (hereinafter, referred to as a first inspection land) 50A.
And the third inspection pin 4 of the IC package 32 with bumps
A land (hereinafter, referred to as a third inspection land) 50C to which 3C is joined is electrically connected by a wiring line 51.

【0026】またこのプリント配線板31の実装面31
Aには、バンプ付ICパツケージ32との対向領域を避
けて第1及び第2のチエツク用ランド53A、53Bが
投げられると共に、これら第1及び第2のチエツク用ラ
ンド53A、53Bはそれぞれ配線ライン52A、52
Bを介して対応する第4の検査用バンプ43Bが接合さ
れるランド(以下、これを第4の検査用ランドと呼ぶ)
50D又は第2の検査用バンプ43Bが接合されるラン
ド(以下、これを第2の検査用ランドと呼ぶ)50Bと
導通接続されている。
The mounting surface 31 of the printed wiring board 31
At A, the first and second check lands 53A and 53B are thrown away from the area facing the IC package 32 with bumps, and these first and second check lands 53A and 53B are respectively connected to the wiring line. 52A, 52
Land to which the corresponding fourth inspection bump 43B is joined via B (hereinafter, referred to as a fourth inspection land)
50D or a land (hereinafter, referred to as a second inspection land) 50B to which the second inspection bump 43B is joined is electrically connected.

【0027】これによりこのプリント配線板31におい
ては、上述のバンプ付ICパツケージ32を実装したと
きに、第1及び第2のチエツク用ランド53A、53B
が配線ライン52A、第4の検査用ランド50D、第4
の検査用バンプ43D(図3)、配線ライン45B(図
3)、第3の検査用バンプ43C(図3)、第3の検査
用ランド50C、配線ライン51、第1の検査用ランド
50A、第1の検査用バンプ43A(図3)、配線ライ
ン45A(図3)、第2の検査用バンプ43B(図
3)、第2の検査用ランド50B及び配線ライン52A
を順次介して導電接続されるようになされている。
As a result, in this printed wiring board 31, when the above-mentioned bumped IC package 32 is mounted, the first and second check lands 53A and 53B are provided.
Is the wiring line 52A, the fourth inspection land 50D, and the fourth
Inspection bump 43D (FIG. 3), wiring line 45B (FIG. 3), third inspection bump 43C (FIG. 3), third inspection land 50C, wiring line 51, first inspection land 50A, First inspection bump 43A (FIG. 3), wiring line 45A (FIG. 3), second inspection bump 43B (FIG. 3), second inspection land 50B and wiring line 52A.
Are electrically connected via the.

【0028】以上の構成において、バンプ付ICパツケ
ージ32の第1〜第4の検査用バンプ43A〜43Dが
いずれも破断していない状態で当該バンプ付ICパツケ
ージ32がプリント配線板31上に実装されている場
合、第1及び第2のチエツク用ランド53A、53B
は、上述のように配線ライン52A、第4の検査用ラン
ド50D、第4の検査用バンプ43D(図3)、配線ラ
イン45B(図3)、第3の検査用バンプ43C(図
3)、第3の検査用ランド50C、配線ライン51、第
1の検査用ランド50A、第1の検査用バンプ43A
(図3)、配線ライン45A(図3)、第2の検査用バ
ンプ43B(図3)、第2の検査用ランド50B及び配
線ライン52Aからなる一繋ぎの導電路によつて導電接
続されるため、これら第1及び第2のチエツク用ランド
53A、53Bにそれぞれテスタの第1又は第2の端子
を接触させたときに、測定値として所定の抵抗値(以
下、これを第1の抵抗値と呼ぶ)が得られる。
In the above structure, the bumped IC package 32 is mounted on the printed wiring board 31 in a state where none of the first to fourth inspection bumps 43A to 43D of the bumped IC package 32 is broken. The first and second check lands 53A, 53B
Is the wiring line 52A, the fourth inspection land 50D, the fourth inspection bump 43D (FIG. 3), the wiring line 45B (FIG. 3), the third inspection bump 43C (FIG. 3), as described above. Third inspection land 50C, wiring line 51, first inspection land 50A, first inspection bump 43A
(FIG. 3), the wiring line 45A (FIG. 3), the second inspection bump 43B (FIG. 3), the second inspection land 50B, and the wiring line 52A are electrically conductively connected by a continuous conductive path. Therefore, when the first or second terminal of the tester is brought into contact with each of the first and second check lands 53A and 53B, a predetermined resistance value (hereinafter, referred to as the first resistance value) is measured as a measurement value. Called) is obtained.

【0029】これに対してこのバンプ付ICパツケージ
32の第1〜第4の検査用バンプ43A〜43Dのいず
れかが破断した状態で当該バンプ付ICパツケージ32
がプリント配線板31上に実装されている場合には、第
1及び第2のチエツク用ランド53A、53Bの導通が
この破断した第1〜第4の検査用バンプ43A〜43D
において切断されため、第1及び第2のチエツク用ラン
ド53A、53Bにそれぞれテスタの第1又は第2の端
子を接触させたときに、測定値として第1の抵抗値より
も大きな抵抗値が得られる。
On the other hand, the bumped IC package 32 is in a state where any of the first to fourth inspection bumps 43A to 43D of the bumped IC package 32 is broken.
Is mounted on the printed wiring board 31, the conduction of the first and second check lands 53A and 53B is the broken first to fourth inspection bumps 43A to 43D.
When the first or second terminals of the tester are brought into contact with the first and second check lands 53A and 53B, respectively, a resistance value larger than the first resistance value is obtained as a measurement value. To be

【0030】ここで、このバンプ付ICパツケージ32
のように裏面側に信号入出力用の複数のバンプが形成さ
れたバンプ付ICパツケージでは、バンプとプリント配
線板の対応するランド間が破断する一番の原因として、
プリント配線板及びバンプ付ICパツケージ間の熱膨張
係数差から、ICチツプの動作時に発生する熱によつて
バンプ付ICパツケージとプリント配線板との間で伸縮
に不整合が生じ、その応力(歪み)がバンプ付ICパツ
ケージ及びプリント配線板間の接合部であるバンプにか
かることがあげらる。
Here, this IC package with bumps 32
In the IC package with bumps in which a plurality of bumps for signal input / output are formed on the back surface as described above, the main cause of the break between the bumps and the corresponding lands of the printed wiring board is
Due to the difference in coefficient of thermal expansion between the printed wiring board and the IC package with bumps, the heat generated during the operation of the IC chip causes a mismatch in expansion and contraction between the IC package with bumps and the printed wiring board, resulting in stress (strain). ) Is applied to the bump which is the joint between the IC package with bumps and the printed wiring board.

【0031】この場合バンプ付ICパツケージ及びプリ
ント配線板間において最も伸縮差が大きな箇所はバンプ
付ICパツケージの周端部近傍であり、従つてバンプ付
ICパツケージの裏面側に設けられた各バンプのうち、
隅部に配置された各バンプに最も応力が集中するため、
当該隅部の各バンプに破断が生じ易いことが本願出願人
によつて確認されている。
In this case, the largest expansion / contraction difference between the IC package with bumps and the printed wiring board is in the vicinity of the peripheral edge of the IC package with bumps, and accordingly, the bumps provided on the back side of the IC package with bumps are the same. home,
Since the stress concentrates most on each bump placed in the corner,
It has been confirmed by the applicant of the present invention that the bumps at the corners are likely to break.

【0032】従つてこの実施例のように、バンプ付IC
パツケージ32及びプリント配線板31を構成すること
によつて、プリント配線板31の第1及び第2のチエツ
ク用ランド53A、53B間の抵抗値を測定するだけ
で、第1〜第4の検査用バンプ43A〜43Dをサンプ
ルとして、バンプ付ICパツケージ32及びプリント配
線板31間の接合部の破断検査をほぼ精度良く、かつ容
易に行うことができる。
Therefore, as in this embodiment, an IC with bumps is provided.
By configuring the package 32 and the printed wiring board 31, it is only necessary to measure the resistance value between the first and second check lands 53A and 53B of the printed wiring board 31, and Using the bumps 43A to 43D as a sample, the fracture inspection of the joint between the bumped IC package 32 and the printed wiring board 31 can be performed with high accuracy and easily.

【0033】以上の構成によれば、バンプICパツケー
ジ31の各バンプ43が設けられた裏面(回路基板40
の他面40B)の隅部にダミーバンプでなる第1〜第4
の検査用バンプ43A〜43Dを配置すると共に、これ
ら第1〜第4の検査用バンプ43A〜43Dのうち、第
1及び第2の検査用バンプ43A、43B間と、第3及
び第4の検査用バンプ43C、43D間とをそれぞれ配
線ライン45A、45Bで導通接続する一方、プリント
配線板31の実装面31Aに、バンプ付ICパツケージ
31の各第1〜第4の検査用バンプ43A〜43Dとそ
れぞれ対応する第1〜第4の検査用ランド50A〜50
Dと、第4又は第2の検査用ランド50D、50Bと導
通接続された第1及び第2のチエツク用ランド53A、
53Bと、第1及び第3の検査用ランド50A、50C
を導通接続する配線ライン51とを設けるようにしたこ
とにより、バンプ付ICパツケージ32及びプリント配
線板31間の接合部の破断状態をほぼ精度良くかつ容易
に検査することができ、かくして実装基板の破断検査を
簡易化させ得るバンプ付ICパツケージ、プリント配線
板、実装基板及び検査方法を実現できる。
According to the above construction, the back surface (circuit board 40) of the bump IC package 31 on which each bump 43 is provided.
First to fourth dummy bumps formed on the corners of the other surface 40B)
Of the inspection bumps 43A to 43D, and among the first to fourth inspection bumps 43A to 43D, between the first and second inspection bumps 43A and 43B and between the third and fourth inspection bumps 43A to 43D. The wiring bumps 43C and 43D are electrically connected to each other by wiring lines 45A and 45B, respectively, while the mounting surface 31A of the printed wiring board 31 is connected to the first to fourth inspection bumps 43A to 43D of the IC package 31 with bumps. Corresponding first to fourth inspection lands 50A to 50, respectively
D and the first and second check lands 53A that are conductively connected to the fourth or second inspection lands 50D and 50B,
53B and first and third inspection lands 50A and 50C
By providing the wiring line 51 for conductively connecting the ICs with each other, the broken state of the joint between the bumped IC package 32 and the printed wiring board 31 can be inspected almost accurately and easily. It is possible to realize an IC package with bumps, a printed wiring board, a mounting board, and an inspection method that can simplify the fracture inspection.

【0034】なお上述の実施例においては、本発明を図
2及び図3のように構成されたバンプ付ICパツケージ
32、当該バンプ付ICパツケージ32を実装するプリ
ント配線板31及び当該バンプ付ICパツケージ32が
当該プリント配線板31に実装されてなる実装基板30
に適用するようにした場合について述べたが、本発明は
これに限らず、一面側に信号入出力用の複数のバンプ
(突起電極)が設けられたこの他種々の表面実装型電子
部品、当該表面実装型電子部品を実装する配線基板及び
実装基板に適用することができる。
In the embodiment described above, the present invention is applied to the IC package 32 with bumps configured as shown in FIGS. 2 and 3, the printed wiring board 31 on which the IC package 32 with bumps is mounted, and the IC package with bumps. A mounting board 30 in which 32 is mounted on the printed wiring board 31.
However, the present invention is not limited to this, and various other surface mount type electronic components in which a plurality of bumps (projection electrodes) for signal input / output are provided on one surface side, It can be applied to a wiring board and a mounting board on which surface-mounted electronic components are mounted.

【0035】また上述の実施例においては、バンプ付I
Cパツケージ32の裏面(回路基板40の他面)に形成
する第1〜第4の検査用バンプ43A〜43Dを当該バ
ンプ付ICパツケージ32の裏面の各隅部にそれぞれ形
成するようにした場合について述べたが、本発明はこれ
に限らず、第1〜第4の検査用バンプ43A〜43Dの
形成位置としてはバンプ付ICパツケージ32の裏面の
各隅部以外の場所であつても良く、また検査用バンプ4
3A〜43Dの数としては4個以上であつても良い。
In the above embodiment, the bumped I
Regarding the case where the first to fourth inspection bumps 43A to 43D formed on the back surface of the C package 32 (the other surface of the circuit board 40) are formed on the respective corners of the back surface of the IC package 32 with bumps. However, the present invention is not limited to this, and the formation positions of the first to fourth inspection bumps 43A to 43D may be positions other than the corners of the back surface of the bumped IC package 32. Inspection bump 4
The number of 3A to 43D may be four or more.

【0036】さらに上述の実施例においては、バンプ付
ICパツケージ32側において第1及び第2の検査用バ
ンプ43A、43Bと、第3及び第4の検査用バンプ4
3C、43Dとをそれぞれ配線ライン45A、45Bで
導通接続すると共に、プリント配線板31側において第
1及び第3の検査用ランド50A、50Cを配線ライン
51により導通接続するようにした場合について述べた
が、本発明はこれに限らず、要は、バンプ付ICパツケ
ージ32をプリント配線板31上に実装したときに、第
1〜第4の検査用ランド50A〜50Dと、これら第1
〜第4の検査用ランド50A〜50Dのうちの所定の一
対の第1〜第4の検査用ランド50A〜50Dを導通接
続する単数又は複数の第1の配線ラインと、第1〜第4
の検査用バンプ43A〜43Dと、これら第1〜第4の
検査用バンプ43A〜43Dのうちの所定の一対の第1
〜第4の検査用バンプ43A〜43Dを導通接続する単
数又は複数の第2の配線ラインとによつて第1及び第2
のチエツク用ランド53A、53Bを導通接続する一繋
ぎの導電路を形成することができるのであれば、第1及
び第2の配線ラインの形成位置の組み合わせとしては、
この他種々の組み合わせを適用できる。
Further, in the above embodiment, the first and second inspection bumps 43A and 43B and the third and fourth inspection bumps 4 are provided on the side of the IC package 32 with bumps.
3C and 43D are electrically connected by the wiring lines 45A and 45B, respectively, and the first and third inspection lands 50A and 50C are electrically connected by the wiring line 51 on the printed wiring board 31 side. However, the present invention is not limited to this, and the point is that when the IC package 32 with bumps is mounted on the printed wiring board 31, the first to fourth inspection lands 50A to 50D and the first to fourth inspection lands 50A to 50D.
~ One or a plurality of first wiring lines that electrically connect a predetermined pair of first to fourth inspection lands 50A to 50D among the fourth inspection lands 50A to 50D, and first to fourth
Inspection bumps 43A to 43D and a predetermined pair of first bumps 43A to 43D among the first to fourth inspection bumps 43A to 43D.
-The first and second wiring lines for electrically connecting the fourth inspection bumps 43A to 43D are connected to the first and second wiring lines.
If it is possible to form a continuous conductive path that electrically connects the check lands 53A and 53B, the combination of the formation positions of the first and second wiring lines is:
Various other combinations can be applied.

【0037】さらに上述の実施例においては、バンプ付
ICパツケージ32の第1及び第2の検査用バンプ43
A、43B、第3及び第4の検査用バンプ43C、43
Dをそれぞれ導通接続するバンプ導通接続手段として、
配線ライン45A、45Bを適用するようにした場合に
ついて述べたが、本発明はこれに限らず、例えばリード
線等を用いるようにしても良く、バンプ付ICパツケー
ジ32の第1及び第2の検査用バンプ43A、43B、
第3及び第4の検査用バンプ43C、43Dをそれぞれ
導通接続するバンプ導通接続手段としては、この他種々
のバンプ導通接続手段を適用できる。
Furthermore, in the above-described embodiment, the first and second inspection bumps 43 of the IC package 32 with bumps are provided.
A, 43B, third and fourth inspection bumps 43C, 43
As a bump conduction connecting means for electrically connecting D respectively,
Although the case where the wiring lines 45A and 45B are applied has been described, the present invention is not limited to this, and for example, a lead wire may be used, and the first and second inspections of the bumped IC package 32 may be performed. Bumps 43A, 43B,
Various other bump conduction connecting means can be applied as the bump conduction connecting means for conducting and connecting the third and fourth inspection bumps 43C and 43D, respectively.

【0038】同様にして上述の実施例においては、プリ
ント配線板31の第1及び第3の検査用ランド50A、
50Cを導通接続する電極導通接続手段として配線ライ
ン51を適用するようにした場合について述べたが、本
発明はこれに限らず、要は、プリント配線板31の第1
〜第4の検査用ランド50A〜50D、バンプ付ICパ
ツケージ32の第1〜第4の検査用バンプ43A〜43
D及び配線ライン45A、45Bと共に第1及び第2の
チエツク用ランド53A、53B間を導通接線する一繋
ぎの導電路を形成することができるのであれば、例えば
リード線等を用いるようにしても良く、プリント配線板
31の第1及び第3の検査用ランド50A、50Cを導
通接続する電極導通接続手段としては、この他種々の電
極導通接続手段を適用できる。
Similarly, in the above-described embodiment, the first and third inspection lands 50A of the printed wiring board 31,
The case where the wiring line 51 is applied as the electrode conduction connecting means for conducting conduction connection of 50C has been described, but the present invention is not limited to this, and the point is that the first of the printed wiring board 31 is used.
-Fourth inspection lands 50A-50D, first-fourth inspection bumps 43A-43 of the IC package 32 with bumps
If it is possible to form a continuous conductive path that makes a conductive tangent line between the first and second check lands 53A and 53B together with the D and the wiring lines 45A and 45B, for example, a lead wire or the like may be used. Of course, various other electrode conductive connection means can be applied as the electrode conductive connection means for conductively connecting the first and third inspection lands 50A and 50C of the printed wiring board 31.

【0039】[0039]

【発明の効果】上述のように本発明によれば、表面実装
型電子部品の一面側にに複数のダミーバンプを設けると
共に、異なる一対のダミーバンプを単数又は複数のバン
プ導通接続手段により導通接続する一方、配線基板の実
装面に、表面実装型電子部品の各ダミーバンプにそれぞ
れ対応する複数の第2の電極と、それぞれ異なる所定の
第1の電極と導電接続された第3及び第4の電極とを形
成し、かつ表面実装電子部品が実装されたときに、第2
の電極、ダミーバンプ及びバンプ導通接続手段と共に第
3及び第4の電極を導通接続する一繋ぎの導電路を形成
するように、異なる一対の第2の電極を単数又は複数の
電極導電接続手段により導通接続するようにしたことに
より、第3及び第4の電極間の抵抗値を測定するだけで
表面実装型電子部品及び配線基板間の破断検査を行うこ
とができ、かくして実装基板の破断検査を簡易化させ得
る表面実装型電子部品、配線基板、実装基板及び実装方
法を実現できる。
As described above, according to the present invention, a plurality of dummy bumps are provided on one surface side of a surface mount type electronic component, and a pair of different dummy bumps are electrically connected by a single or a plurality of bump conduction connecting means. , A plurality of second electrodes respectively corresponding to the dummy bumps of the surface-mounted electronic component, and third and fourth electrodes conductively connected to different predetermined first electrodes on the mounting surface of the wiring board. When formed and surface-mounted electronic components are mounted, the second
Of electrodes, dummy bumps, and bump conduction connection means so that a pair of different second electrodes are electrically connected by a single or a plurality of electrode conduction connection means so as to form a continuous conduction path for electrically connecting the third and fourth electrodes. By making the connection, the breakage inspection between the surface mount type electronic component and the wiring board can be performed only by measuring the resistance value between the third and fourth electrodes, thus simplifying the breakage inspection of the mount board. It is possible to realize a surface mount electronic component, a wiring board, a mounting board and a mounting method that can be realized.

【図面の簡単な説明】[Brief description of drawings]

【図1】実施例による実装基板の構成を示す平面図であ
る。
FIG. 1 is a plan view showing a configuration of a mounting board according to an embodiment.

【図2】実施例によるバンプ付ICパツケージの構成を
示す断面図である。
FIG. 2 is a cross-sectional view showing a configuration of an IC package with bumps according to an embodiment.

【図3】実施例によるバンプ付ICパツケージの構成を
示す平面面である。
FIG. 3 is a plan view showing a configuration of an IC package with bumps according to an embodiment.

【図4】実施例によるプリント配線板の構成を示す略線
的な平面図である。
FIG. 4 is a schematic plan view showing a configuration of a printed wiring board according to an example.

【図5】QFPの構成を示す斜視図である。FIG. 5 is a perspective view showing a configuration of a QFP.

【図6】BGAの構成を示す断面図である。FIG. 6 is a cross-sectional view showing the structure of a BGA.

【図7】従来のバンプ付ICパツケージの一構成例を示
す平面図である。
FIG. 7 is a plan view showing a configuration example of a conventional IC package with bumps.

【図8】従来の実装基板の構成を示す平面図である。FIG. 8 is a plan view showing a configuration of a conventional mounting board.

【符号の説明】[Explanation of symbols]

30……実装基板、31……プリント配線板、31A…
…実装面、32……バンプ付ICパツケージ、41……
ICチツプ、43……バンプ、43A〜43D……検査
用バンプ、45A、45B、51、52A、52B……
配線ライン、50……ランド、50A〜50D……検査
用ランド、53A、53B……チエツク用ランド。
30 ... Mounting board, 31 ... Printed wiring board, 31A ...
… Mounting surface, 32 …… Bumped IC package, 41 ……
IC chip, 43 ... Bump, 43A to 43D ... Inspection bump, 45A, 45B, 51, 52A, 52B ...
Wiring line, 50 ... Land, 50A to 50D ... Inspection land, 53A, 53B ... Check land.

Claims (8)

【特許請求の範囲】[Claims] 【請求項1】一面側に信号入出力用の複数のバンプが形
成された表面実装型電子部品において、 上記一面側に設けられた複数のダミーバンプと、 それぞれ異なる一対の上記ダミーバンプを導通接続する
単数又は複数のバンプ導通接続手段とを具えることを特
徴とする表面実装型電子部品。
1. A surface-mounted electronic component having a plurality of bumps for signal input / output formed on one surface side, wherein a plurality of dummy bumps provided on the one surface side and a pair of dummy bumps respectively different from each other are electrically connected. Alternatively, a surface mount type electronic component comprising a plurality of bump conductive connecting means.
【請求項2】各上記ダミーバンプは、それぞれ上記一面
側の隅部に設けられたことを特徴とする請求項1に記載
の表面実装型電子部品。
2. The surface mount electronic component according to claim 1, wherein each of the dummy bumps is provided in a corner portion on the one surface side.
【請求項3】一面側に信号入出力用のバンプを複数有す
る表面実装型電子部品を実装する配線基板において、 上記バンプにそれぞれ対応させて、上記表面実装部品を
実装する実装面に形成された複数の第1の電極と、 上記表面実装型電子部品の上記一面側に設けられた複数
のダミーバンプにそれぞれ対応させて上記実装面に形成
された複数の第2の電極と、 上記実装面のうち、上記表面実装型電子部品との対向領
域を避けて形成され、それぞれ異なる所定の上記第1の
電極と導電接続された第3及び第4の電極と、 上記表面実装電子部品が実装されたときに、上記第2の
電極、上記ダミーバンプ及びそれぞれ異なる一対の上記
ダミーバンプを導通接続する単数又は複数のバンプ導通
接続手段と共に上記第3及び第4の電極を導通接続する
一繋ぎの導電路を形成するように、それぞれ異なる一対
の上記第2の電極を導電接続する単数又は複数の電極導
通接続手段とを具えることを特徴とする配線基板。
3. A wiring board for mounting a surface mount type electronic component having a plurality of signal input / output bumps on one surface side, the wiring board being formed on the mounting surface for mounting the surface mount component in correspondence with each of the bumps. A plurality of first electrodes, a plurality of second electrodes formed on the mounting surface corresponding to a plurality of dummy bumps provided on the one surface side of the surface mount electronic component, and among the mounting surface When the surface mounting electronic component is mounted, third and fourth electrodes which are formed so as to avoid the area facing the surface mounting electronic component and are conductively connected to the predetermined different first electrodes, respectively. And one or more bump conductive connecting means for conductively connecting the second electrode, the dummy bump, and a pair of different dummy bumps, respectively, and a conductive connection for the third and fourth electrodes. A wiring board comprising a single or a plurality of electrode conductive connecting means for conductively connecting a pair of different second electrodes so as to form a continuous conductive path.
【請求項4】各上記第2の電極は、 上記表面実装型電子部品の上記一面側の隅部にそれぞれ
設けられた各上記ダミーバンプにそれぞれ対応させて、
上記実装面のうち、上記表面実装型電子部品のとの上記
対向領域の隅部にそれぞれ形成されたことを特徴とする
請求項3に記載の配線基板。
4. The second electrodes correspond to the dummy bumps respectively provided at the corners on the one surface side of the surface mount electronic component,
The wiring board according to claim 3, wherein each of the mounting surfaces is formed at a corner of the facing area of the surface-mounted electronic component.
【請求項5】配線基板の実装面に表面実装型電子部品が
実装されてなる実装基板において、 上記表面実装型電子部品は、 上記配線基板との対向面でなる一面側に設けられた信号
出入力用の複数のバンプと上記一面側に設けられた複数
のダミーバンプと、 それぞれ異なる一対の上記ダミーバンプを導通接続する
単数又は複数のバンプ導通接続手段とを具え、 上記配線基板は、 上記表面実装型電子部品の各上記バンプにそれぞれ対応
させて上記実装面に形成された複数の第1の電極と、 上記表面実装型電子部品の各上記ダミーバンプにそれぞ
れ対応させて上記実装面に形成された複数の第2の電極
と、 上記実装面の上記第2の電極の周囲に形成され、それぞ
れ異なる所定の上記第1の電極と導電接続された第3及
び第4の電極と、 上記表面実装電子部品が実装されたときに、上記第2の
電極、上記ダミーバンプ及び上記バンプ導通接続手段と
共に上記第3及び第4の電極を導通接続する一繋ぎの導
電路を形成するように、それぞれ異なる一対の上記第2
の電極を導電接続する単数又は複数の電極導通接続手段
とを具えることを特徴とする実装基板。
5. A mounting board in which a surface mounting type electronic component is mounted on a mounting surface of a wiring board, wherein the surface mounting type electronic component has a signal output provided on one surface side which is a surface facing the wiring board. The wiring board includes a plurality of bumps for input, a plurality of dummy bumps provided on the one surface side, and a single or a plurality of bump conductive connecting means for conductively connecting a pair of different dummy bumps, respectively, A plurality of first electrodes formed on the mounting surface corresponding to the bumps of the electronic component, and a plurality of first electrodes formed on the mounting surface corresponding to the dummy bumps of the surface mount electronic component. A second electrode, third and fourth electrodes formed around the second electrode on the mounting surface and electrically conductively connected to different first electrodes, respectively, and the surface Different from each other so that when the electronic component is mounted, the second electrode, the dummy bump, and the bump conductive connection means form a continuous conductive path for conductively connecting the third and fourth electrodes. A pair of the second
And a plurality of electrode conductive connecting means for conductively connecting the electrodes of 1.
【請求項6】上記表面実装型電子部品の各上記ダミーバ
ンプは、 それぞれ上記表面実装型電子部品の上記一面側の隅部に
設けられ各上記第2の電極は、 各上記ダミーバンプにそれぞれ対応させて、上記実装面
のうち、上記表面実装型電子部品との対向領域の隅部に
それぞれ形成されたことを特徴とする請求項5に記載の
実装基板。
6. The dummy bumps of the surface-mounted electronic component are respectively provided at the corners on the one surface side of the surface-mounted electronic component, and the second electrodes correspond to the dummy bumps, respectively. The mounting board according to claim 5, wherein the mounting board is formed at a corner portion of a region facing the surface-mounted electronic component, of the mounting surface.
【請求項7】一面側に信号入出力用の複数のバンプが形
成された表面実装型電子部品を配線基板の実装面に実装
する実装方法において、 上記表面実装型電子部品の上記一面側に複数のダミーバ
ンプを設けると共に、異なる一対の上記ダミーバンプを
単数又は複数のバンプ導通接続手段により導通接続する
一方、上記配線基板の上記実装面に、上記表面実装型電
子部品の各上記バンプ又は各上記ダミーバンプにそれぞ
れ対応する複数の第1及び第2の電極と、それぞれ異な
る所定の上記第1の電極と導電接続された第3及び第4
の電極とを形成し、かつ上記表面実装電子部品が実装さ
れたときに、上記第2の電極、上記ダミーバンプ及び上
記バンプ導通接続手段と共に上記第3及び第4の電極を
導通接続する一繋ぎの導電路を形成するように、異なる
一対の上記第2の電極を単数又は複数の電極導電接続手
段により導通接続する第1のステツプと、 上記表面実装型電子部品を上記配線基板上に位置決めし
てマウントした後、上記表面実装型電子部品の上記バン
プ及び上記ダミーバンプをそれぞれ上記配線基板の対応
する第1又は第2の電極と接合する第2のステツプとを
具えることを特徴とする実装方法。
7. A mounting method for mounting a surface mounting type electronic component having a plurality of bumps for signal input / output formed on one side thereof on a mounting surface of a wiring board, wherein a plurality of surface mounting type electronic components are provided on the one side. While providing the dummy bumps, the pair of different dummy bumps are conductively connected by a single or a plurality of bump conductive connecting means, on the mounting surface of the wiring board, to the bumps or the dummy bumps of the surface mount electronic component. A plurality of corresponding first and second electrodes, and third and fourth conductively connected to the respective different predetermined first electrodes.
Of the second electrode, the dummy bump, and the bump conductive connection means, and when the surface-mounted electronic component is mounted, the third electrode and the fourth electrode are electrically connected. A first step for conductively connecting a pair of different second electrodes by one or more electrode conductive connecting means so as to form a conductive path; and positioning the surface mount electronic component on the wiring board. And a second step of joining the bump and the dummy bump of the surface-mounted electronic component to the corresponding first or second electrode of the wiring board after mounting.
【請求項8】上記第1のステツプでは、 各上記ダミーバンプを、それぞれ上記表面実装型電子部
品の上記一面側の隅部に設けると共に、 各上記第2の電極を、各上記ダミーバンプにそれぞれ対
応させて、実装面のうち、上記表面実装型電子部品との
対向領域の隅部にそれぞれ形成することを特徴とする実
装方法。
8. In the first step, each of the dummy bumps is provided at a corner of the one surface side of the surface mount electronic component, and each of the second electrodes is associated with each of the dummy bumps. Then, the mounting method is characterized in that it is formed at a corner of a region facing the surface-mounted electronic component on the mounting surface.
JP7329096A 1996-03-04 1996-03-04 Surface mounted type electronic component, wiring board, mounting board and mounting method Pending JPH09246426A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP7329096A JPH09246426A (en) 1996-03-04 1996-03-04 Surface mounted type electronic component, wiring board, mounting board and mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7329096A JPH09246426A (en) 1996-03-04 1996-03-04 Surface mounted type electronic component, wiring board, mounting board and mounting method

Publications (1)

Publication Number Publication Date
JPH09246426A true JPH09246426A (en) 1997-09-19

Family

ID=13513882

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7329096A Pending JPH09246426A (en) 1996-03-04 1996-03-04 Surface mounted type electronic component, wiring board, mounting board and mounting method

Country Status (1)

Country Link
JP (1) JPH09246426A (en)

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333386B1 (en) * 1999-06-29 2002-04-18 박종섭 chip scale package
US6960830B2 (en) * 2002-10-31 2005-11-01 Rohm Co., Ltd. Semiconductor integrated circuit device with dummy bumps
JP2008205975A (en) * 2007-02-21 2008-09-04 Fujitsu Ltd Semiconductor integrated circuit
US7449907B2 (en) 2004-12-28 2008-11-11 Samsung Electronics Co., Ltd Test unit to test a board having an area array package mounted thereon
WO2010064341A1 (en) * 2008-12-01 2010-06-10 パナソニック株式会社 Semiconductor device having chip
JP2010251519A (en) * 2009-04-15 2010-11-04 Denso Corp Electronic device
JP2011254053A (en) * 2010-06-04 2011-12-15 Nec Corp Semiconductor package, wiring board and reflow furnace
JP2016510877A (en) * 2013-03-07 2016-04-11 ザイリンクス インコーポレイテッドXilinx Incorporated Package integrity monitor with sacrificial bumps
CN106298709A (en) * 2016-11-11 2017-01-04 三星半导体(中国)研究开发有限公司 Low cost fan-out formula encapsulating structure
JP2020141223A (en) * 2019-02-27 2020-09-03 ローム株式会社 Semiconductor device

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100333386B1 (en) * 1999-06-29 2002-04-18 박종섭 chip scale package
US6960830B2 (en) * 2002-10-31 2005-11-01 Rohm Co., Ltd. Semiconductor integrated circuit device with dummy bumps
US7449907B2 (en) 2004-12-28 2008-11-11 Samsung Electronics Co., Ltd Test unit to test a board having an area array package mounted thereon
JP2008205975A (en) * 2007-02-21 2008-09-04 Fujitsu Ltd Semiconductor integrated circuit
US8067950B2 (en) 2008-12-01 2011-11-29 Panasonic Corporation Semiconductor device including chip
WO2010064341A1 (en) * 2008-12-01 2010-06-10 パナソニック株式会社 Semiconductor device having chip
JP2010251519A (en) * 2009-04-15 2010-11-04 Denso Corp Electronic device
US8395404B2 (en) 2009-04-15 2013-03-12 Denso Corporation Electronic device including electronic part and wiring substrate
JP2011254053A (en) * 2010-06-04 2011-12-15 Nec Corp Semiconductor package, wiring board and reflow furnace
JP2016510877A (en) * 2013-03-07 2016-04-11 ザイリンクス インコーポレイテッドXilinx Incorporated Package integrity monitor with sacrificial bumps
CN106298709A (en) * 2016-11-11 2017-01-04 三星半导体(中国)研究开发有限公司 Low cost fan-out formula encapsulating structure
CN106298709B (en) * 2016-11-11 2019-08-13 三星半导体(中国)研究开发有限公司 Low cost is fanned out to formula encapsulating structure
JP2020141223A (en) * 2019-02-27 2020-09-03 ローム株式会社 Semiconductor device

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