KR100333386B1 - chip scale package - Google Patents

chip scale package Download PDF

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Publication number
KR100333386B1
KR100333386B1 KR1019990025216A KR19990025216A KR100333386B1 KR 100333386 B1 KR100333386 B1 KR 100333386B1 KR 1019990025216 A KR1019990025216 A KR 1019990025216A KR 19990025216 A KR19990025216 A KR 19990025216A KR 100333386 B1 KR100333386 B1 KR 100333386B1
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South Korea
Prior art keywords
dummy
lead
protrusion
encapsulant
solder balls
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KR1019990025216A
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Korean (ko)
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KR20010004527A (en
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홍성학
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박종섭
주식회사 하이닉스반도체
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Priority to KR1019990025216A priority Critical patent/KR100333386B1/en
Publication of KR20010004527A publication Critical patent/KR20010004527A/en
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Publication of KR100333386B1 publication Critical patent/KR100333386B1/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/05111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05164—Palladium [Pd] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Abstract

본 발명은 칩 스캐일 패키지를 개시한다. 개시된 본 발명은, 반도체 칩의 본딩 패드 형성면에 리드 프레임이 부착된다. 리드 프레임은 본딩 패드와 대응하는 수로 이루어진 복수개의 리드들을 포함한다. 각 리드들 밑면에는 단자용 돌출부들이 형성된다. 각 리드들 사이로 더미 리드들이 배치된다. 더미 리드에도 최소한 하나 이상의 돌출부가 형성되는데, 이 더미용 돌출부는 단자용 돌출부의 외곽에 배치된다. 각 리드들의 내측단 밑면이 금속 와이어에 의해 본딩 패드에 전기적으로 연결된다. 각 돌출부들 밑면이 노출되도록 전체가 봉지제로 몰딩된다. 리드의 내측단 하부의 봉지제 부분에는 하향으로 돌출된 볼록부를 갖는다. 최외곽에 배치된 더미용 돌출부 외측으로도 측면 볼록부가 형성되고, 또한 단자용 및 더미용 돌출부의 전후에도 전후면 볼록부들이 형성된다. 봉지제에서 노출된 각 돌출부에 단자용 솔더 볼과 더미용 솔더 볼이 마운트된다.The present invention discloses a chip scale package. In the disclosed invention, a lead frame is attached to a bonding pad forming surface of a semiconductor chip. The lead frame includes a plurality of leads made of a bonding pad and a corresponding number. Protrusions for terminals are formed on the bottom of each lead. Dummy leads are disposed between the leads. At least one protrusion is also formed in the dummy lead, and the dummy protrusion is disposed outside the terminal protrusion. The inner bottom surface of each lead is electrically connected to the bonding pad by a metal wire. The whole is molded with encapsulant so that the bottom of each protrusion is exposed. The encapsulant portion below the inner end of the lid has a convex portion projecting downward. Side convex portions are also formed outside the dummy protrusions arranged at the outermost side, and front and rear convex portions are formed also before and after the terminals and the dummy protrusions. Each exposed protrusion from the encapsulant is mounted with a terminal solder ball and a dummy solder ball.

Description

칩 스캐일 패키지{chip scale package}Chip scale package

본 발명은 칩 스캐일 패키지에 관한 것으로서, 보다 구체적으로는 기판에 실장되는 복수개의 솔더 볼을 갖는 칩 스캐일 패키지에 관한 것이다.The present invention relates to a chip scale package, and more particularly, to a chip scale package having a plurality of solder balls mounted on a substrate.

패키지의 한 예로서, 가장 범용으로 사용되고 있는 에스오제이(SOJ:Small Outline J-lead) 타입이 있고, 특수한 경우에 사용하는 지프(ZIP: Zigzag Inline Package) 타입이 있으며, 또 규격화되고 있는 메모리 카드(memory card)에 적합하도록 구성된 티에스오피(TSOP: Thin Small Outline Package) 타입 등이 있다.An example of a package is a small outline J-lead (SOJ) type that is most commonly used, and a Zigzag Inline Package (ZIP) type that is used in a special case. There is a Thin Small Outline Package (TSOP) type that is configured to be suitable for a memory card.

이러한 패키지 제조 방법을 개략적으로 설명하면 다음과 같다.The manufacturing method of such a package is briefly described as follows.

먼저, 웨이퍼를 스크라이빙 라인을 따라 절단하는 소잉(sawing) 공정을 진행하여 개개의 반도체 칩으로 분리한 다음, 리드 프레임의 인너 리드를 각 반도체 칩에 부착하는 다이 어태치 공정을 진행한다.First, a sawing process of cutting a wafer along a scribing line is performed to separate the semiconductor chips into individual semiconductor chips, and then a die attach process of attaching the inner lead of the lead frame to each semiconductor chip is performed.

이후 일정 온도에서 일정시간 동안 큐어링(curing)을 실시한 후, 반도체 칩의 패드와 리드 프레임의 인너 리드를 금속 와이어로 상호 연결시켜 전기적으로 연결시키는 와이어 본딩 공정을 수행한다.After curing at a predetermined temperature for a predetermined time, a wire bonding process is performed in which the pads of the semiconductor chip and the inner lead of the lead frame are interconnected with metal wires to be electrically connected to each other.

와이어 본딩이 끝나면, 봉지제를 사용하여 반도체 칩을 몰딩하는 몰딩 공정을 수행한다. 이와 같이 반도체 칩을 몰딩해야만, 외부의 열적, 기계적 충격으로 부터 반도체 칩을 보호할 수가 있는 것이다.After the wire bonding is finished, a molding process of molding a semiconductor chip using an encapsulant is performed. Only by molding the semiconductor chip in this way, can the semiconductor chip be protected from external thermal and mechanical shocks.

상기와 같은 몰딩 공정이 완료된 후에는 아우터 리드을 도금하는 플래팅 공정, 아우터 리드를 지지하고 있는 댐바를 절단하는 트림 공정 및 기판에 실장이 용이하도록 아우터 리드를 소정 형태로 절곡 형성하는 포밍 공정을 진행하여, 패키지를 제조한다.After the above molding process is completed, a plating process for plating the outer lead, a trimming process for cutting the dam bar supporting the outer lead, and a forming process for bending the outer lead into a predetermined shape to facilitate mounting on the substrate are performed. Manufacture the package.

이러한 공정으로 제작되는 일반적인 패키지에 대해, 패키지의 경박화를 위해 제시된 칩 스캐일 패키지는 기판에 실장되는 수 개의 솔더 볼이 어레이식으로 배열된 구조로 이루어진다.For a typical package fabricated by this process, the chip scale package presented for the thinning of the package has a structure in which several solder balls mounted on a substrate are arranged in an array form.

보다 구체적으로 설명하면, 반도체 칩의 밑면에 리드 프레임이 접착제로 부착되어 있다. 리드 프레임의 인너 리드가 금속 와이어로 반도체 칩의 패드에 연결되어 있다. 리드 프레임의 밑면이 부분 식각되어 아우터 리드가 형성되어 있다. 각 아우터 리드가 노출되도록 전체가 봉지제로 몰딩되어 있다. 봉지제에서 노출된 아우터 리드에 솔더 볼이 마운팅되어 있다.More specifically, the lead frame is attached to the bottom of the semiconductor chip with an adhesive. The inner lead of the lead frame is connected to the pad of the semiconductor chip with a metal wire. The bottom surface of the lead frame is partially etched to form an outer lead. The whole is molded with an encapsulant so that each outer lead is exposed. Solder balls are mounted on the outer leads exposed from the encapsulant.

상기와 같은 구성으로 이루어진 칩 스캐일 패키지는 기판(PCB)에 실장되어 사용된다. 그런데, 기판의 열팽창계수는 14.9E-6/℃인데 반해서 패키지의 열팽창계수는 8E-6/℃ 정도이다. 특히, 패키지의 열팽창계수는 봉지제가 차지하는 면적에 비례하고 반도체 칩의 크기에는 반비례한다.The chip scale package having the above configuration is mounted on a substrate (PCB) and used. By the way, the thermal expansion coefficient of a board | substrate is 14.9E-6 / degreeC, whereas the thermal expansion coefficient of a package is about 8E-6 / degreeC. In particular, the coefficient of thermal expansion of the package is proportional to the area occupied by the encapsulant and inversely proportional to the size of the semiconductor chip.

여기서, 패키지 전체에 대해서 반도체 칩이 차지하는 용적비가 80% 정도 이상일 경우에, 이러한 패키지를 칩 스캐일 패키지라 한다. 최근의 연구 추세에 비추어보면 반도체 칩이 차지하는 용적비는 계속 증가할 것이 명백한 사실이다. 패키지에서 반도체 칩이 차지하는 용적비가 증가한다는 것은 역으로 봉지제가 차지하는 용적비가 상대적으로 줄어든다는 것을 의미한다. 따라서, 기판과 패키지간의 열팽창계수 차이는 칩 스캐일 패키지가 구현되면 될 수록 점점 더 커질 수밖에 없다.Here, when the volume ratio of the semiconductor chip to the whole package is about 80% or more, such a package is called a chip scale package. In light of recent research trends, it is clear that the volume ratio of semiconductor chips will continue to increase. Increasing the volume fraction of semiconductor chips in packages means that the volume fraction of encapsulants is relatively reduced. Therefore, the difference in coefficient of thermal expansion between the substrate and the package will become larger as the chip scale package is implemented.

이와 같이 점차 심화되는 기판과 패키지간의 열팽창계수 차이는 솔더 볼의 접속 불량, 즉 솔더 볼에 균열이 발생되는 심각한 문제점을 일으킨다. 도 1은 패키지에서 각 구성요소의 변화에 따른 솔더 볼의 접속 불량율을 나타낸 그래프이다. 도 1에서 횡축은 온도 사이클이고, 종축이 접속 불량율이다. 도시된 바와 같이, 접속 불량율을 낮추기 위해서는, 반도체 칩의 크기는 작게, 솔더 볼간의 피치는 넓게, 솔더 볼의 수는 증가시켜야 한다.This deepening difference in thermal expansion coefficient between the substrate and the package causes a serious problem that the solder ball connection failure, that is, cracks in the solder ball. 1 is a graph showing the connection failure rate of the solder ball according to the change of each component in the package. In Figure 1, the axis of abscissas is the temperature cycle, and the axis of ordinates is the connection failure rate. As shown in the figure, in order to reduce the connection failure rate, the size of the semiconductor chip should be small, the pitch between solder balls should be wide, and the number of solder balls should be increased.

그런데, 패키지 수준에서는 반도체 칩의 크기는 미리 정해져 있고, 솔더 볼간의 피치 역시 기판과 대응되도록 표준화되어 있으므로, 반도체 칩의 크기나 솔더 볼간의 피치를 임의로 조정할 수는 없다. 그러므로, 남아 있는 변수인 솔더 볼의 수를 늘이거나 또는 전술된 바와 같이 패키지의 두께나 면적이 증가되지 않도록 하면서 봉지제가 차지하는 용적비를 늘이는 방법밖에 없다. 여기서, 솔더 볼의 수도 기판과 대응되도록 표준화되어 있음은 물론이다. 그러므로, 솔더 볼의 수를 늘이기 위해서는, 전기 신호가 흐르지 않는 솔더 볼을 고려할 수가 있다.However, at the package level, the size of the semiconductor chip is predetermined and the pitch between the solder balls is also standardized to correspond to the substrate. Therefore, the size of the semiconductor chip and the pitch between the solder balls cannot be arbitrarily adjusted. Therefore, the only method is to increase the number of solder balls remaining, or increase the volume ratio of the encapsulant while preventing the thickness or area of the package from increasing as described above. Here, of course, the solder ball is also standardized to correspond to the substrate. Therefore, in order to increase the number of solder balls, it is possible to consider solder balls in which electric signals do not flow.

본 발명은 상기된 전제 조건을 근거로 하여 안출된 것으로서, 패키지 전체에 대해서 봉지제가 차지하는 용적비를 늘임으로써, 기판과 패키지간의 열팽창계수 차이를 최대한 줄여서 솔더 볼의 접속 신뢰성을 향상시킬 수 있는 칩 스캐일 패키지를 제공하는데 목적이 있다.The present invention has been made based on the above-described preconditions, and by increasing the volume ratio of the encapsulant over the entire package, the chip scale package can improve the connection reliability of the solder ball by minimizing the difference in thermal expansion coefficient between the substrate and the package. The purpose is to provide.

본 발명의 다른 목적은, 전기 신호가 흐르지 않는 솔더 볼을 이용해서 솔더 볼의 수를 증가시키므로써, 솔더 볼의 접속 불량율을 낮출 수 있는 칩 스캐일 패키지를 제공하는데 있다.Another object of the present invention is to provide a chip scale package which can lower the connection failure rate of solder balls by increasing the number of solder balls using solder balls through which no electrical signal flows.

도 1은 본 발명의 실시예 1에 따른 칩 스캐일 패키지를 나타낸 단면도.1 is a cross-sectional view showing a chip scale package according to Embodiment 1 of the present invention.

도 2는 본 실시예 1의 주요부인 리드 프레임을 나타낸 평면도.Fig. 2 is a plan view showing a lead frame as a main part of the first embodiment.

도 3은 패키지의 배면 사시도.3 is a rear perspective view of the package;

도 4는 본 발명의 실시예 2에 따른 칩 스캐일 패키지의 배면 사시도.4 is a rear perspective view of the chip scale package according to Embodiment 2 of the present invention;

도 5는 본 발명의 실시예 3에 따른 칩 스캐일 패키지의 배면 사시도.5 is a rear perspective view of the chip scale package according to Embodiment 3 of the present invention;

도 6은 본 발명의 실시예 4에 따른 칩 스캐일 패키지를 나타낸 단면도.6 is a sectional view showing a chip scale package according to a fourth embodiment of the present invention.

- 도면의 주요 부분에 대한 부호의 설명 --Explanation of symbols for the main parts of the drawing-

10 ; 반도체 칩 11 ; 본딩 패드10; Semiconductor chip 11; Bonding pads

20 ; 리드 프레임 21 ; 리드20; Lead frame 21; lead

22 ; 더미 리드 23 ; 단자용 돌출부22; Dummy lead 23; Protrusion for terminal

24 ; 더미용 돌출부 30 ; 접착제24; Dummy protrusions 30; glue

40 ; 금속 와이어 50 ; 봉지제40; Metal wire 50; Encapsulant

51,52,53 ; 볼록부 60 ; 단자용 솔더 볼51,52,53; Convex part 60; Solder Balls for Terminal

61 ; 더미용 솔더 볼 70 ; 접합 보조용 금속막61; Dummy solder balls 70; Bonding metal film

상기와 같은 목적을 달성하기 위하여, 본 발명에 따른 칩 스캐일 패키지는 본딩 패드가 하부를 향하도록 배치된 반도체 칩; 반도체 칩의 밑면에 부착되고, 본딩 패드와 대응되는 수로 이루어진 리드들을 포함하며, 각 리드들 사이에 더미 리드들이 배치되고, 리드와 더미 리드 각각에 단자용 및 더미용 돌출부가 형성되며, 더미용 돌출부는 단자용 돌출부 외곽에 배치된 리드 프레임; 리드 프레임의 리드 내측단과 반도체 칩의 본딩 패드를 전기적으로 연결하는 금속 와이어; 상기 구조물 전체를 몰딩시키되, 단자용 및 더미용 돌출부를 노출시키는 봉지제; 봉지제로부터 노출된 단자용 및 더미용 돌출부에 각각 마운트된 단자용 및 더미용 솔더 볼; 및 더미용 솔더 볼의 외곽에 위치하는 봉지제 부분과 단자용 및 더미용 솔더 볼의 전후에 위치하는 봉지제 부분에 적어도 어느 한부분에 형성되어 인너 리드의 하부에 위치하는 부분에 금속 와이어의 노출을 방지하고 전체 용적비를 증가시키는 볼록부를 포함하는 것을 특징으로 한다.In order to achieve the above object, the chip scale package according to the present invention comprises a semiconductor chip disposed so that the bonding pad facing downward; Attached to the bottom surface of the semiconductor chip, comprising a lead corresponding to the number of bonding pads, dummy leads are disposed between each lead, and each of the lead and the dummy lead is formed for the terminal and dummy protrusions, the dummy protrusion The lead frame is disposed outside the terminal projection; A metal wire electrically connecting the lead inner end of the lead frame to the bonding pad of the semiconductor chip; An encapsulant for molding the entire structure and exposing the terminal and dummy protrusions; Solder balls for terminals and dummy mounted on the terminals and dummy protrusions exposed from the encapsulant, respectively; And exposing the metal wire to at least one portion of the encapsulant portion located at the outer side of the dummy solder ball and the encapsulant portion positioned at the front and rear of the terminal and dummy solder ball and positioned at the lower portion of the inner lead. It characterized in that it comprises a convex portion to prevent and increase the total volume ratio.

이하, 본 발명의 바람직한 실시예를 첨부도면에 의거하여 설명한다.Best Mode for Carrying Out the Invention Preferred embodiments of the present invention will now be described based on the accompanying drawings.

[실시예 1]Example 1

도 1은 본 발명의 실시예 1에 따른 칩 스캐일 패키지를 나타낸 단면도이고, 도 2는 본 실시예 1의 주요부인 리드 프레임을 나타낸 평면도이며, 도 3은 패키지의 배면 사시도이다.1 is a cross-sectional view showing a chip scale package according to a first embodiment of the present invention, FIG. 2 is a plan view showing a lead frame as a main part of the first embodiment, and FIG. 3 is a rear perspective view of the package.

도 1에 도시된 바와 같이, 반도체 칩(10)은 중앙을 따라 배치된 본딩 패드(11)가 하부를 향하게 배치된다. 리드 프레임(20)이 반도체 칩(10)의 밑면에 부착되는데, 리드 프레임(20)의 상세한 구조가 도 2에 평면으로 도시되어 있다.As illustrated in FIG. 1, in the semiconductor chip 10, the bonding pads 11 disposed along the center thereof face downward. The lead frame 20 is attached to the underside of the semiconductor chip 10, the detailed structure of the lead frame 20 is shown in plan in FIG.

도 2에 도시된 바와 같이, 리드 프레임(20)은 본딩 패드와 대응되는 수로 이루어진 복수개의 리드(21)를 포함한다. 본딩 패드와 연결되는 각 리드(21)의 내측단은 중앙에 위치되고, 외측단은 외곽으로 연장된다. 각 리드(21)의 외측단은 댐바(미도시)에 연결되어 일체로 된 상태로 지지된다. 한편, 본 발명에서는 각 리드(21)들 사이로 더미 리드(22)를 배치한다. 즉, 각 더미 리드(22)의 외측단은 댐바에 연결되고, 내측단은 중앙을 향해 연장된다. 특히, 각 더미 리드(22)의 길이는 도 2를 보면 리드(21) 길이의 1/3 정도인데, 그 이유는 더미 리드(22)의 내측단이 후술되는 솔더 볼이 마운트되는 위치보다 외곽에 위치되어야 하기 때문이다. 이와 같이 더미 리드(22)의 길이를 제한하는 이유는 이후에 상세히 설명하기로 한다.As shown in FIG. 2, the lead frame 20 includes a plurality of leads 21 formed of a number corresponding to the bonding pads. The inner end of each lead 21 connected to the bonding pad is located at the center, and the outer end extends outward. The outer end of each lead 21 is connected to a dam bar (not shown) and supported in an integrated state. Meanwhile, in the present invention, the dummy lead 22 is disposed between the leads 21. That is, the outer end of each dummy lead 22 is connected to the dam bar, and the inner end extends toward the center. In particular, the length of each dummy lead 22 is about one third of the length of the lead 21 as shown in FIG. 2, because the inner end of the dummy lead 22 is located outside the position where the solder ball to be described later is mounted. Because it must be located. The reason for limiting the length of the dummy lead 22 as described above will be described later.

다시, 도 1을 참조로 하여, 리드(21)의 밑면에 2개의 돌출부(23), 보다 구체적으로는 단자용 돌출부들이 형성된다. 실제로, 단자용 돌출부(23)는 리드(21)에 하나씩 형성되는데, 도 3에 도시된 바와 같이 솔더 볼(60)들이 2열로 배열되므로, 이를 나타내기 위해서 도 1에서는 편의상 하나의 리드(21)에 2개의 단자용 돌출부(23)들이 형성된 상태로 도시하였다. 또한, 더미 리드(22)의 내측단 밑면에도 돌출부(24), 보다 구체적으로는 더미용 돌출부들이 형성된다. 특히, 전술된 바와 같이, 더미 리드(22)의 길이가 제한되어 있으므로, 더미용 돌출부(24)는 단자용 돌출부(23)의 외곽에 배치된다.Again, referring to FIG. 1, two protrusions 23, more specifically terminal protrusions, are formed on the underside of the lid 21. In fact, the terminal protrusions 23 are formed on the leads 21 one by one. Since the solder balls 60 are arranged in two rows as shown in FIG. 3, one lead 21 is shown in FIG. 1 for convenience. It is shown with two terminal protrusions 23 formed in the. In addition, a protrusion 24, more specifically, a dummy protrusion is formed on the bottom surface of the inner end of the dummy lead 22. In particular, as described above, since the length of the dummy lead 22 is limited, the dummy protrusion 24 is disposed outside the terminal protrusion 23.

단자용 및 더미용 돌출부(23,24)들이 배치된 구조는 도 2에 보다 상세히 도시되어 있다. 도 2에서 각 돌출부(23,24)는 솔더 볼을 마운트하기 용이하도록 원형으로 형성된다. 여기서, 각 돌출부(23,24)가 리드(21)와 더미 리드(22)에서 돌출되는 식으로 형성된다고 설명하였지만, 실제로는 리드(21)와 더미 리드(22)를 식각하는 것에 의해 형성된다. 즉, 리드(21)와 더미 리드(22)의 원래 두께는 도 1에서 리드(21)의 내측단 두께가 된다. 각 돌출부(23,24)는 이러한 두께를 갖는 리드(21)와 더미 리드(22)를 부분 식각하는 것에 의해 형성된다.The structure in which the terminal and dummy protrusions 23 and 24 are arranged is shown in more detail in FIG. 2. In FIG. 2, the protrusions 23 and 24 are formed in a circular shape to facilitate mounting the solder balls. Here, although each protrusion 23 and 24 was formed in the way which protrudes from the lead 21 and the dummy lead 22, it is formed by etching the lead 21 and the dummy lead 22 actually. That is, the original thicknesses of the leads 21 and the dummy leads 22 are the inner end thicknesses of the leads 21 in FIG. 1. Each of the protrusions 23 and 24 is formed by partially etching the lead 21 and the dummy lead 22 having such a thickness.

상기된 구성으로 이루어진 리드 프레임(20)이 도 1에 도시된 바와 같이, 접착제(30)를 매개로 반도체 칩(10)의 밑면에 부착된다. 각 리드(21)의 내측단 밑면이 금속 와이어(40)에 의해 본딩 패드(11)에 전기적으로 연결된다.As shown in FIG. 1, the lead frame 20 having the above-described configuration is attached to the bottom surface of the semiconductor chip 10 through the adhesive 30. The inner bottom surface of each lead 21 is electrically connected to the bonding pad 11 by the metal wire 40.

전체가 봉지제(50)로 몰딩되는데, 이때 각 돌출부(23,24)의 밑면과 전술된 댐바만이 봉지제(50)에서 노출된다. 봉지제(50)에서 노출된 댐바를 절단하므로써, 도 2에 도시된 리드 프레임(20)이 완성되고, 도 1과 같이 반도체 칩(10)에 연결되지 않은 더미 리드(22)가 리드(21)와 동일 평면에 위치할 수가 있게 된다.The whole is molded with encapsulant 50, wherein only the underside of each protrusion 23, 24 and the aforementioned dambar are exposed at encapsulant 50. By cutting the dam bar exposed by the encapsulant 50, the lead frame 20 shown in FIG. 2 is completed, and the dummy lead 22 not connected to the semiconductor chip 10 as shown in FIG. It can be located on the same plane as.

또한, 리드(21)의 내측단 하부에 있는 봉지제(50) 부분에 하향으로 볼록부(51)가 형성된다. 패키지 전체를 기준으로 중앙에 배치된 중앙 볼록부(51)는 와이어 본딩시, 리드(21)의 내측단 밑면보다 아래로 약간 처지게 되는 금속 와이어(40)가 봉지제(50)에서 노출되지 않도록 하는 역할을 한다. 이러한 역할에 부가하여, 중앙 돌출부(51)는 패키지에 대한 봉지제(50)의 용적비를 증가시키는 역할도 하게 된다. 더미용 돌출부(24) 외곽에 있는 봉지제(50) 부분에도 측면 볼록부(52)가 형성된다. 측면 볼록부(52)가 하는 역할은 중앙 볼록부(51)의 후자 역할과 동일하다.Further, the convex portion 51 is formed downward in the portion of the encapsulant 50 under the inner end of the lid 21. The central convex part 51 disposed at the center of the package as a whole may not expose the metal wire 40 from the encapsulant 50, which is slightly sag below the bottom surface of the inner end of the lead 21 during wire bonding. It plays a role. In addition to this role, the central protrusion 51 also serves to increase the volume ratio of the encapsulant 50 to the package. Side convex portions 52 are also formed at portions of the encapsulant 50 outside the dummy protrusions 24. The role of the side convex part 52 is the same as the latter role of the center convex part 51. FIG.

한편, 도 3에 도시된 바와 같이, 각 볼록부(51,52)는 패키지의 장축 방향을 따라 전체적으로 형성된다. 패키지의 장축 방향이란 더미용 돌출부(24)들이 배열된 방향이다. 봉지제(50)에서 노출된 단자용 및 더미용 돌출부(23,24)에 단자용 솔더 볼(60)과 더미용 솔더 볼(61)이 마운트된다. 여기서, 각 솔더 볼(60,61)의 높이가 패키지에 추가되므로, 전술된 볼록부(51,52)들이 패키지의 두께를 증가시키지는 않는다. 또한, 각 볼록부(51,52)가 솔더 볼(60,61)보다 하부로 더 돌출되지 않아야 함은 물론이다.Meanwhile, as shown in FIG. 3, each of the convex portions 51 and 52 is formed entirely along the long axis direction of the package. The long axis direction of the package is a direction in which the dummy protrusions 24 are arranged. The terminal solder balls 60 and the dummy solder balls 61 are mounted on the terminal and dummy protrusions 23 and 24 exposed by the encapsulant 50. Here, since the height of each solder ball 60, 61 is added to the package, the above-mentioned convex portions 51, 52 do not increase the thickness of the package. In addition, each of the convex portions 51 and 52 should not protrude further below the solder balls 60 and 61, of course.

패키지가 상기와 같은 구성으로 이루어지면, 우선 봉지제(50)의 용적비가 패키지의 두께는 증가되지 않으면서 각 볼록부(51,52)들에 의해 늘어나게 되므로, 기판과 패키지간의 열팽창계수 차이가 줄어들게 된다. 또한, 단자용 솔더 볼(60) 외곽으로 더미용 솔더 볼(61)이 배치되므로써, 열팽창계수 차이로 인해 발생되어 외곽으로부터 진행되는 크랙이 우선적으로 더미용 솔더 볼(61)부터 일어나게 되므로써, 실질적으로 전기 신호를 전달하는 단자용 솔더 볼(60)에 크랙 현상이 발생되는 것이 억제된다.When the package is configured as described above, the volume ratio of the encapsulant 50 is first increased by the convex portions 51 and 52 without increasing the thickness of the package, thereby reducing the difference in thermal expansion coefficient between the substrate and the package. do. In addition, since the dummy solder ball 61 is disposed outside the terminal solder ball 60, a crack generated due to a difference in thermal expansion coefficient and proceeding from the outside occurs preferentially from the dummy solder ball 61. It is suppressed that a crack phenomenon arises in the solder ball 60 for terminals which transmit an electric signal.

[실시예 2]Example 2

도 4는 본 발명의 실시예 2에 따른 칩 스캐일 패키지의 배면 사시도이다. 실시예 1의 도 3과 비교해보면, 각 솔더 볼(60,61)의 전후에도 볼록부(53)들이 형성되어 있다는 점에서 차이가 있다. 따라서, 봉지제(50)의 용적비가 더욱 증가되어, 기판과 패키지간의 열팽창계수 차이를 더욱 줄어든다.4 is a rear perspective view of the chip scale package according to Embodiment 2 of the present invention. Compared with FIG. 3 of the first embodiment, there is a difference in that the convex portions 53 are formed before and after each solder ball 60 and 61. Therefore, the volume ratio of the encapsulant 50 is further increased to further reduce the difference in thermal expansion coefficient between the substrate and the package.

한편, 각 볼록부(52,53) 사이 공간이 다른 봉지제(미도시)로 몰딩될 수도 있다. 즉, 단자용 및 더미용 솔더 볼(60,61)이 마운트된 후, 각 솔더 볼(60,62) 높이의 2/3 높이 정도로 볼록부(52,53)와 동일 평면을 갖는 다른 봉지제로 몰딩할 수도 있다. 이와 같이, 각 볼록부(52,53) 사이 공간을 다른 봉지제로 몰딩하게 되면, 각 솔더 볼(60,61)을 측부에서 지지하는 강도가 대폭 강화되는 잇점이 있다.Meanwhile, the space between the convex portions 52 and 53 may be molded with another encapsulant (not shown). That is, after the terminal and dummy solder balls 60 and 61 are mounted, they are molded with another encapsulant having the same plane as the convex portions 52 and 53 about 2/3 of the height of each solder ball 60 and 62. You may. Thus, when the space between each convex part 52 and 53 is molded by another sealing agent, the strength which supports each solder ball 60 and 61 by the side part is strengthened significantly.

[실시예 3]Example 3

도 5는 본 발명의 실시예 3에 따른 칩 스캐일 패키지의 배면 사시도이다. 실시예 1의 도 3과 비교해보면, 각 솔더 볼(60,61)의 전후에 실시예 2와 같이 볼록부가 형성된 것이 아니라 더미용 솔더 볼(62)들이 배치된다. 특히, 이 더미용 솔더 볼(62)은 다른 솔더 볼(60,61)들보다 크기가 상대적으로 크다. 그 이유는, 전술된 솔더 볼(60,61)은 돌출부상에 마운트되지만, 실시예 3에 따른 더미용 솔더 볼(62)은 식각된 리드의 밑면에 마운트되므로, 다른 솔더 볼(60,61)들과 마찬가지로 기판에 실장되기 위해서 더 큰 크기를 가져야 하는 것에 기인한다.5 is a rear perspective view of the chip scale package according to Embodiment 3 of the present invention. Compared with FIG. 3 of the first embodiment, the dummy solder balls 62 are disposed before and after each of the solder balls 60 and 61, rather than having convex portions as in the second embodiment. In particular, this dummy solder ball 62 is relatively larger in size than the other solder balls 60 and 61. The reason is that the above-described solder balls 60 and 61 are mounted on the protrusions, but the dummy solder balls 62 according to Embodiment 3 are mounted on the underside of the etched lead, so that the other solder balls 60 and 61 are mounted. Like these, it is due to having a larger size to be mounted on a substrate.

이러한 구조의 패키지에서는, 실시예 2에 따른 패키지보다는 봉지제의 용적비가 비록 줄어들지만, 패키지의 전후 방향에서 진행되는 크랙을 완충시킬 수 있는 다른 효과가 있다.In the package having such a structure, although the volume ratio of the encapsulant is smaller than that of the package according to the second embodiment, there is another effect that can cushion the cracks that proceed in the front-rear direction of the package.

[실시예 4]Example 4

도 6은 본 발명의 실시예 4에 따른 칩 스캐일 패키지를 나타낸 단면도이다. 실시예 1의 도 1과 비교해보면, 더미용 솔더 볼(61)이 하나가 아니라 2개이다. 즉, 더미 리드(22)의 밑면을 식각하면서, 더미용 돌출부(22)를 2개로 형성하는 것이다. 대신에, 추가로 형성되는 더미용 돌출부(22)가 봉지제(50)에서 노출되는 최외곽에 배치되므로, 실시예 1과 같이 봉지제(50)에 측면 볼록부(52)가 형성되지 않는다.6 is a cross-sectional view illustrating a chip scale package according to Embodiment 4 of the present invention. As compared with FIG. 1 of the first embodiment, the dummy solder balls 61 are not one but two. In other words, the bottom surface of the dummy lead 22 is etched to form two dummy protrusions 22. Instead, since the additionally formed dummy protrusion 22 is disposed at the outermost portion exposed by the encapsulant 50, the side convex portion 52 is not formed in the encapsulant 50 as in the first embodiment.

이러한 구조의 패키지에서는, 봉지제(50)의 용적비는 줄지만, 더미용 솔더 볼(61)이 패키지 측면에 2열로 배치되므로, 측면에서 진행되는 크랙을 보다 효과적으로 저지시킬 수 있는 상대적인 효과가 있다.In the package having such a structure, the volume ratio of the encapsulant 50 is reduced, but since the dummy solder balls 61 are arranged in two rows on the side surface of the package, there is a relative effect that can effectively prevent cracks that progress from the side surface.

한편, 각 실시예에서 솔더 볼(60,61)을 돌출부(23,24)에 마운트할 때, 먼저돌출부(23,24)의 전면 또는 가장자리에 접합 보조용 금속막(70)을 증착한 후, 이 접합 보조용 금속막(70)에 솔더 볼(60,61)을 마운트하는 것이, 접합 강도 측면에서 유리하다. 접합 보조용 금속막(70)의 재질로는 니켈, 은, 구리, 금, 팔라듐, 주석, 납, 코발트 또는 크롬 중의 하나인 것이 바람직하다.On the other hand, when mounting the solder balls (60, 61) to the protrusions (23, 24) in each embodiment, first after depositing the bonding auxiliary metal film 70 on the front or edge of the protrusions (23, 24), It is advantageous to mount the solder balls 60, 61 on the bonding auxiliary metal film 70 in terms of bonding strength. The material of the joining auxiliary metal film 70 is preferably one of nickel, silver, copper, gold, palladium, tin, lead, cobalt or chromium.

이상에서 설명한 바와 같이 본 발명에 의하면, 단자용 솔더 볼 외곽으로 전기 신호가 흐르지 않는 더미용 솔더 볼이 배치되므로써, 기판과 패키지간의 열팽창계수 차이로 인해 패키지 외곽으로부터 발생된 크랙이 더미용 솔더 볼에 먼저 진행된다. 따라서, 전기 신호를 전달하는 단자용 솔더 볼에 크랙이 진행되는 것이 억제된다.As described above, according to the present invention, since a dummy solder ball in which no electrical signal flows is disposed outside the terminal solder ball, cracks generated from the outside of the package due to the difference in thermal expansion coefficient between the substrate and the package are transferred to the dummy solder ball. First proceed. Therefore, the progress of a crack in the solder ball for terminals which transmit an electric signal is suppressed.

또한, 봉지제에 볼록부들이 형성되어, 패키지에 대한 봉지제의 용적비가 증가된다. 따라서, 기판과 패키지간의 열팽창계수 차이가 최대한 줄어들게 되므로, 크랙 현상 자체가 억제된다.In addition, convex portions are formed in the encapsulant, thereby increasing the volume ratio of the encapsulant to the package. Therefore, the difference in thermal expansion coefficient between the substrate and the package is reduced as much as possible, so that the crack phenomenon itself is suppressed.

이상에서는 본 발명에 의한 칩 스캐일 패키지를 실시하기 위한 바람직한 실시예에 대하여 도시하고 또한 설명하였으나, 본 발명은 상기한 실시예에 한정되지 않고, 이하 청구범위에서 청구하는 본 발명의 요지를 벗어남이 없이 당해 발명이 속하는 분야에서 통상의 지식을 가진자라면 누구든지 다양한 변경 실시가 가능할 것이다.In the above, a preferred embodiment for implementing a chip scale package according to the present invention has been illustrated and described, but the present invention is not limited to the above-described embodiment, without departing from the gist of the present invention as claimed in the following claims. Various modifications can be made by those skilled in the art to which the present invention pertains.

Claims (8)

본딩 패드가 하부를 향하도록 배치된 반도체 칩;A semiconductor chip disposed such that a bonding pad faces downward; 상기 반도체 칩의 밑면에 부착되고, 상기 본딩 패드와 대응되는 수로 이루어진 리드들을 포함하며, 각 리드들 사이에 더미 리드들이 배치되고, 상기 리드와 더미 리드 각각에 단자용 및 더미용 돌출부가 형성되며, 상기 더미용 돌출부는 단자용 돌출부 외곽에 배치된 리드 프레임;A lead attached to the bottom surface of the semiconductor chip, the lead including a number corresponding to the bonding pad, dummy leads disposed between the leads, and terminal and dummy protrusions formed on the leads and the dummy leads, respectively. The dummy protrusion may include a lead frame disposed outside the terminal protrusion; 상기 리드 프레임의 리드 내측단과 반도체 칩의 본딩 패드를 전기적으로 연결하는 금속 와이어;A metal wire electrically connecting a lead inner end of the lead frame to a bonding pad of a semiconductor chip; 상기 구조물 전체를 몰딩시키되, 상기 단자용 돌출부 및 상기 더미용 돌출부를 노출시키는 봉지제;An encapsulant for molding the entire structure and exposing the terminal protrusion and the dummy protrusion; 상기 봉지제로부터 노출된 상기 단자용 돌출부 및 상기 더미용 돌출부에 각각 마운트된 단자용 솔더 볼 및 더미용 솔더 볼; 및A terminal solder ball and a dummy solder ball respectively mounted on the terminal protrusion and the dummy protrusion exposed from the encapsulant; And 성가 더미용 솔더 볼의 외곽에 위치하는 봉지제 부분과 상기 단자용 솔더 볼 및 상기 더미용 솔더 볼의 전후에 위치하는 봉지제 부분 중 적어도 어느 한부분에 형성되어 상기 인너 리드의 하부에 위치하는 부분에 상기 금속 와이어의 노출을 방지하고 전체 용적비를 증가시키는 볼록부를 포함하는 것을 특징으로 하는 칩 스캐일 패키지.A portion formed on at least one of an encapsulant portion located at an outer side of the annoying dummy solder ball and an encapsulant portion positioned before and after the terminal solder ball and the dummy solder ball and positioned below the inner lead. And a convex portion for preventing exposure of the metal wire and increasing the total volume ratio. 청구항2는 삭제 되었습니다.Claim 2 has been deleted. 청구항3는 삭제 되었습니다.Claim 3 has been deleted. 제 1항에 있어서, 상기 볼록부 사이 부분이, 볼록부와 동일 평면을 이루는 다른 봉지제로 몰딩된 것을 특징으로 하는 칩 스캐일 패키지.The chip scale package according to claim 1, wherein the portions between the convex portions are molded with another encapsulant which is coplanar with the convex portions. 제 1 항에 있어서, 상기 각 솔더 볼의 전후에 위치하는 리드 밑면에 더미용 솔더 볼들이 마운트되고, 상기 더미용 솔더 볼은 기판 실장이 가능하도록 측면을 따라 배치된 상기 단자용 및 더미용 솔더 볼들보다 크기가 큰 것을 특징으로 하는 칩 스캐일 패키지.The dummy solder balls of claim 1, wherein the dummy solder balls are mounted on a bottom surface of the lead positioned before and after each of the solder balls, and the dummy solder balls are disposed along side surfaces to allow board mounting. Chip scale package, characterized in that the larger size. 제 1 항에 있어서, 상기 더미용 돌출부는 하나의 더미 리드에 2개로 형성되어, 각 더미용 돌출부에 2개의 더미용 솔더 볼이 마운트된 것을 특징으로 하는 칩 스캐일 패키지.The chip scale package of claim 1, wherein two dummy protrusions are formed in one dummy lead, and two dummy solder balls are mounted on each dummy protrusion. 제 1 항에 있어서, 상기 각 솔더 볼과 돌출부 사이에 접합 보조 금속막이 증착된 것을 특징으로 하는 칩 스캐일 패키지.The chip scale package of claim 1, wherein a bonding auxiliary metal film is deposited between the solder balls and the protrusions. 제 7 항에 있어서, 상기 접합 보조 금속막의 재질은 니켈, 은, 구리, 금, 팔라듐, 주석, 납, 코발트 또는 크롬 중의 하나인 것을 특징으로 하는 칩 스캐일 패키지.The chip scale package of claim 7, wherein the bonding auxiliary metal layer is made of nickel, silver, copper, gold, palladium, tin, lead, cobalt, or chromium.
KR1019990025216A 1999-06-29 1999-06-29 chip scale package KR100333386B1 (en)

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