JPS6242441A - Integrated circuit device - Google Patents

Integrated circuit device

Info

Publication number
JPS6242441A
JPS6242441A JP60182348A JP18234885A JPS6242441A JP S6242441 A JPS6242441 A JP S6242441A JP 60182348 A JP60182348 A JP 60182348A JP 18234885 A JP18234885 A JP 18234885A JP S6242441 A JPS6242441 A JP S6242441A
Authority
JP
Japan
Prior art keywords
integrated circuit
bonding
circuit chip
circular
configuration
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP60182348A
Other languages
Japanese (ja)
Inventor
Kenji Iwata
健二 岩田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP60182348A priority Critical patent/JPS6242441A/en
Publication of JPS6242441A publication Critical patent/JPS6242441A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/023—Redistribution layers [RDL] for bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

PURPOSE:To make larger an allowance for the protrusion of a thermocompression bonding part, to maintain connection strength and to suppress the generation of defective appearances by a method wherein the configuration of bonding pads is formed into an oblong form, a polygonal form, a circular form, an elliptic form, a configuration combining these forms, or a configuration combining a circular form and a square form. CONSTITUTION:Bonding pads 2 in a configuration combined a circular form and a square form are arranged on the periphery of the upper surface of an integrated circuit chip 1 plural pieces and each bonding pad 2 has lead-out wirings 2a and is exposed to the outside from a window 3 of an insulative protective film formed for protection of the integrated circuit chip 1 to be able to be electrically connected.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は乗積回路チップ上に形底されるボンディングパ
ッドに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to bonding pads formed on multiplicative circuit chips.

〔従来の技術〕[Conventional technology]

従来、この種の集積回路装置は、集積回路チップの周辺
に正方形のボンディングパッドを複数個有していた。Conventionally, this type of integrated circuit device has had a plurality of square bonding pads around the periphery of the integrated circuit chip.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述しｔ従来の集積回路装置は、正方形のボンディング
バットヲ有しているので、ボンディング線をボンディン
グする際、ボンディング位置がずれると、熱田着部分が
ボンディングパッドよりはみ出し、ボンディングの接続
強度が低下すると共に、外観上の不良となり、歩留りが
低下するという欠点がある。特に近年ボンディング装置
は著しく高速化、自動化が進められており、上述の欠点
を是正する為に、ボンディング装置の調整に時間を費す
と生産性が著しく低下する欠点もある。又。As mentioned above, the conventional integrated circuit device has a square bonding butt, so if the bonding position shifts when bonding the bonding wire, the hot soldering part protrudes from the bonding pad, reducing the bonding connection strength. At the same time, there are disadvantages in that the appearance is defective and the yield is reduced. Particularly in recent years, bonding equipment has become much faster and more automated, and if time is spent adjusting the bonding equipment in order to correct the above-mentioned drawbacks, productivity will drop significantly. or.

上述の不具合を是正する為にボンディングパッドを大き
くすることも可能であるが、そうするとペレットの大き
さが大きくなり、ＬＳＩ装置の大きささが大きくなって
しまうという欠点がある。Although it is possible to increase the size of the bonding pad in order to correct the above-mentioned problems, this has the drawback that the size of the pellet increases and the size of the LSI device increases.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の集積回路装置は、長方形又は円を含む５角形以
上の多角形、又は埼円形、又はこれら全組み合わせた形
状、又は円形と正方形を組み合わせた形状のボンディン
グパッドを有している。The integrated circuit device of the present invention has a bonding pad having a rectangular shape, a pentagonal or more polygonal shape including a circle, a cylindrical shape, a combination of all of these shapes, or a combination of a circular shape and a square shape.

［実施例］ 次に、本発明について図面を参照して説明する。[Example] Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例に係る集積回路チ・ノブの上
面図である。集積回路チップ１の上面周辺に、円形およ
び正方形を組み合わせた形状のボンディングパッド（点
線で示す）２が複数個配置され、それぞれのボンディン
グパッド２は引出し配置ｚａを暮し集積回路チップ１の
保護の為に形取された絶縁性保護膜の窓３から外面に露
出し電気、的接続が可能となっている。FIG. 1 is a top view of an integrated circuit chip according to an embodiment of the present invention. A plurality of bonding pads 2 having a combination of circular and square shapes (indicated by dotted lines) are arranged around the top surface of the integrated circuit chip 1, and each bonding pad 2 is placed in a drawer arrangement za to protect the integrated circuit chip 1. It is exposed to the outside through the window 3 of the insulating protective film cut into a shape, and electrical connection is possible.

ｌｃ２図ないし第５図は、本発明の変形例をそれぞれ示
すための表面保護膜を取除いた状態の部分平面図である
。Figures lc2 to 5 are partial plan views with the surface protective film removed to show modified examples of the present invention.

第２図は円形の一部を直線で切シ落した形状のボンディ
ングパッド４を複数個有する集積回路チップの上面図を
示す、第３図は円形のボンディングパッド５を複数個有
する集積回路チップの上面図を示す、第４図は長円形ま
九は！１円形のボンディングパッド６を複数個有する集
積回路チップの上面図を示す。第５内は六角形のボンデ
ィングパッド７を複数個有する＄積回路チップの上面図
を示す。FIG. 2 shows a top view of an integrated circuit chip having a plurality of bonding pads 4 in the shape of a circular part cut off with a straight line, and FIG. 3 shows a top view of an integrated circuit chip having a plurality of circular bonding pads 5. Figure 4, which shows the top view, is an oval shape! A top view of an integrated circuit chip having a plurality of circular bonding pads 6 is shown. The fifth figure shows a top view of a $ product circuit chip having a plurality of hexagonal bonding pads 7.

これらは集積回路装置のチップの大きさ制限や集積回路
装置のチップ上Ｖｃ＃Ｉ！成される回路素子の配置によ
り最も適切なボンディングパッドを選択できる。また、
集積回路装置の回路素子形状および回路素子配置などに
応じて、上記の変形例に示さレル複数のボンディングパ
ッド形状を同−集積回路装置上に配置してもよいことは
言うまでもない。These include the size limitations of the chip of the integrated circuit device and the Vc#I on the chip of the integrated circuit device! The most appropriate bonding pad can be selected depending on the layout of the circuit elements to be created. Also,
It goes without saying that a plurality of bonding pad shapes shown in the above modification may be arranged on the same integrated circuit device depending on the circuit element shape and circuit element arrangement of the integrated circuit device.

〔発明の効果〕〔Effect of the invention〕

以上説明したように２本発明は、ボンディングパッドの
形状を長方形又は５角形以上の多角形。As explained above, in the second aspect of the present invention, the shape of the bonding pad is rectangular or polygonal with more than 5 sides.

又は円形、又は酷円形、又はこれらを組み合せ定形状、
又は円形と正方形をくみ合わせた形状として適宜集積回
路装置上に配置することＶＣよシ、集積回路装置の大き
さを変えずに、ボンディング位置のずれによる熱圧着部
分のはみ出しに対する余裕を大きくすることができ、接
続強度の維持と、外観不良の発生を押えることができる
効果がある。Or a circular shape, a very circular shape, or a combination of these,
Or, to arrange it on the integrated circuit device as appropriate in a shape that combines a circle and a square.For VC, to increase the margin for the protrusion of the thermocompression bonded part due to deviation of the bonding position without changing the size of the integrated circuit device. This has the effect of maintaining connection strength and preventing appearance defects.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は本発明の一実施例に係る集積回路チップの上面
図、第２図ないし第５図はそれぞれ本発明の他の実施例
に係る集積回路チップの表面保護膜を除いて示し九変形
例の部分平面図である。 １・・・・・・集積回路チップ、２１００８８．長円形
のボンディングパッド、２ａ・・・・・・ボンディング
パッド引出し配置、３・・・・・・保護膜の窓、４・・
・・・・部分円形パッド、５・・・・・・円形パッド、
６・・・・・嶋円形パット、７・・・・・・６角形パツ
ド。FIG. 1 is a top view of an integrated circuit chip according to one embodiment of the present invention, and FIGS. 2 to 5 respectively show integrated circuit chips according to other embodiments of the present invention without the surface protective film. FIG. 3 is a partial plan view of an example. 1...Integrated circuit chip, 210088. Oval bonding pad, 2a...Bonding pad drawer arrangement, 3...Protective film window, 4...
...Partial circular pad, 5...Circular pad,
6... Shima circular pad, 7... Hexagonal pad.

Claims (1)

【特許請求の範囲】[Claims] 長方形、長円形、円を含む５角形以上の多角形、円弧の
一部を直線とした部分円形などの、正方形を除いた形状
のボンディングパッド領域群から、任意に選んだ複数の
ボンディングパッドを有する集積回路チップを備えたこ
とを特徴とする集積回路装置。It has a plurality of bonding pads arbitrarily selected from a group of bonding pad regions with shapes other than squares, such as rectangles, ellipses, polygons of pentagons or more including circles, and partial circles where part of the arc is a straight line. An integrated circuit device comprising an integrated circuit chip.
JP60182348A 1985-08-19 1985-08-19 Integrated circuit device Pending JPS6242441A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60182348A JPS6242441A (en) 1985-08-19 1985-08-19 Integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60182348A JPS6242441A (en) 1985-08-19 1985-08-19 Integrated circuit device

Publications (1)

Publication Number Publication Date
JPS6242441A true JPS6242441A (en) 1987-02-24

Family

ID=16116736

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60182348A Pending JPS6242441A (en) 1985-08-19 1985-08-19 Integrated circuit device

Country Status (1)

Country Link
JP (1) JPS6242441A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63157935U (en) * 1987-04-03 1988-10-17
JPH0260435U (en) * 1988-10-25 1990-05-02
US5834849A (en) * 1996-02-13 1998-11-10 Altera Corporation High density integrated circuit pad structures

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63157935U (en) * 1987-04-03 1988-10-17
JPH0260435U (en) * 1988-10-25 1990-05-02
US5834849A (en) * 1996-02-13 1998-11-10 Altera Corporation High density integrated circuit pad structures

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