JPS63296289A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPS63296289A JPS63296289A JP13215687A JP13215687A JPS63296289A JP S63296289 A JPS63296289 A JP S63296289A JP 13215687 A JP13215687 A JP 13215687A JP 13215687 A JP13215687 A JP 13215687A JP S63296289 A JPS63296289 A JP S63296289A
- Authority
- JP
- Japan
- Prior art keywords
- conductor
- substrate
- active element
- integrated circuit
- bonding wire
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004020 conductor Substances 0.000 claims abstract description 46
- 239000000758 substrate Substances 0.000 claims abstract description 16
- 239000003990 capacitor Substances 0.000 abstract description 5
- 239000000919 ceramic Substances 0.000 abstract description 5
- 238000004519 manufacturing process Methods 0.000 abstract description 4
- 239000010409 thin film Substances 0.000 abstract description 3
- 238000000034 method Methods 0.000 abstract description 2
- 238000005516 engineering process Methods 0.000 description 3
- 230000009467 reduction Effects 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000002860 competitive effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000010408 film Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は混成集積回路装置に関し、特に開発費の低減、
コスト低減、短納期全可能にする混成集積回路装置に関
する。[Detailed Description of the Invention] [Industrial Field of Application] The present invention relates to a hybrid integrated circuit device, and particularly to a reduction in development costs,
This invention relates to a hybrid integrated circuit device that enables cost reduction and short delivery times.
近年、混成集積回路装置（以下、）・イブリッドＩＣと
称す）は、トランジスタ、コンデンサ、抵抗器及びコイ
ルだけではなく、メモリ装置のＣＰＵ等のＩＣやＬＳＩ
も多数搭載されるよう罠なってきた。それにもかかわら
ず、開発費とコストの低減および短納期の要求は強くな
る一方である。In recent years, hybrid integrated circuit devices (hereinafter referred to as ``hybrid IC'') have not only been developed to include transistors, capacitors, resistors, and coils, but also ICs and LSIs such as CPUs in memory devices.
It has become a trap as many of them are installed. Nevertheless, the demand for lower development costs, lower costs, and shorter delivery times continues to grow stronger.
第９図は従来のかかるハイブリッドＩＣ基板の平面図で
ある。FIG. 9 is a plan view of such a conventional hybrid IC board.
第ろ図に示すように、かかる従来の／ＳイブリッドＩＣ
の組立にあたっては、品種毎にパターン図しかる後エツ
チング等により導体２を形成する。As shown in FIG.
When assembling, the conductor 2 is formed by drawing a pattern for each type and then etching or the like.
次に、ＩＣチップ３を基板１上に搭載しボンディングワ
イヤ７によシ導体２の先端に形成されているパッドと前
記ＩＣチップ３のリードとをボンディング接続する。ま
たセラミックチップコンデンサ４等は導体２間に接続さ
れる。尚、１０は基板１上の導体２間に印刷された印刷
抵抗である。Next, the IC chip 3 is mounted on the substrate 1, and the pads formed at the ends of the conductors 2 are bonded to the leads of the IC chip 3 using the bonding wires 7. Further, a ceramic chip capacitor 4 or the like is connected between the conductors 2. Note that 10 is a printed resistor printed between the conductors 2 on the substrate 1.
従来はこのように、基板１に搭載される電子部品に合わ
せて導体２が形成されるため、設計変更などにより電子
部品の配置を変えるためには、再度パターンや引回しな
どを開発する必要がある。Conventionally, the conductor 2 is formed in accordance with the electronic components mounted on the board 1 in this way, so if the arrangement of the electronic components is changed due to a design change, it is necessary to develop the pattern and routing again. be.
上述した従来のハイプリ、ドＩＣは、品種毎にパターン
図およびマスク設計を行い、しかる後印刷、スパッタ、
エツチング等を行った上で基板を製造している。従って
、従来のハイブリッドＩＣの製造にあたっては開発費と
コストの低減及び納期の短縮が困難となる問題がある。In the conventional high-precision and de-IC described above, pattern drawings and mask designs are made for each product type, and then printing, sputtering,
The substrate is manufactured after etching, etc. Therefore, in manufacturing conventional hybrid ICs, there is a problem in that it is difficult to reduce development costs and costs and shorten delivery time.
これらを大幅に改善することは競争の激しい半導体技術
分野において、強力な武器となる所以である。Significant improvements in these aspects will become a powerful weapon in the highly competitive field of semiconductor technology.
本発明の目的は、上述のように開発費およびコストの低
減、並びに製造納期を短縮し得るハイプリ、ドＩＣを提
供することにある。As described above, an object of the present invention is to provide a high-performance IC that can reduce development costs and costs, and shorten manufacturing delivery time.
本発明のハイブリッドＩＣは、基板上に網目状に形成さ
れた導体と、前記導体上に搭載された能動素子および受
動素子と、前記導体をステッチ側となるように前記能動
素子および受動素子と接続されるボンディングワイヤと
、前記導体のうち不要人導体部分を切断し所定の配線等
を形成するだめの導体切断部とを含んで構成される。The hybrid IC of the present invention includes a conductor formed in a mesh shape on a substrate, an active element and a passive element mounted on the conductor, and the conductor is connected to the active element and the passive element so as to be on the stitch side. The conductor cutting section is configured to include a bonding wire that is connected to the conductor, and a spare conductor cutting section that cuts off an unnecessary conductor portion of the conductor to form a predetermined wiring or the like.
特に、本発明は電子部品を形成する搭載部品の形状とポ
ンディングパッドの位置、ビン配置、導体引回し等を考
慮して導体を多数切断するようにしている。In particular, in the present invention, a large number of conductors are cut in consideration of the shape of the mounted components forming the electronic component, the position of the bonding pad, the arrangement of the bins, the routing of the conductors, etc.
次に、本発明の実施例について図面を参照して説明する
。Next, embodiments of the present invention will be described with reference to the drawings.
第１図（ａ） 、 （ｂ）はそれぞれ本発明の一実施例
を説明するための工程順に示した混成集積回路部品搭載
基板の平面図である。FIGS. 1(a) and 1(b) are plan views of a hybrid integrated circuit component mounting board shown in the order of steps for explaining an embodiment of the present invention.
第１図（ａ）に示すように、セラミック基板ｌの全体に
わたシ網目状の薄膜導体２が形成される。この薄膜導体
２０幅は５０μｍ程度である。As shown in FIG. 1(a), a mesh-like thin film conductor 2 is formed over the entire ceramic substrate 1. As shown in FIG. The width of this thin film conductor 20 is about 50 μm.
次に、第１図（ｂ）に示すように、基板１の導体ｚ上に
種々の部品を搭載する状態を示し、３は能動素子を、４
はセラミックチップコンデンサを、また５はチップ抵抗
である。尚、この場合、ボンディングワイヤ及び導体の
切断部分は細いので省略している。Next, as shown in FIG. 1(b), a state in which various components are mounted on the conductor z of the substrate 1 is shown, 3 is an active element, 4 is an active element,
5 is a ceramic chip capacitor, and 5 is a chip resistor. Note that in this case, the cut portions of the bonding wire and conductor are thin, so they are omitted.
このように１基板上が網目状になっているのでほとんど
の引回しに対応が可能であシ、複数の能動および受動素
子が大きさく関係なく容易に搭載することができる。ま
た、大きさだけでなく簡単な構造のものから複雑表構造
のものまで同一基板で対応することが出来る。Since one substrate has a mesh shape in this way, it is possible to accommodate almost any wiring arrangement, and a plurality of active and passive elements can be easily mounted regardless of their size. Furthermore, in addition to size, it is possible to use the same board to handle everything from simple structures to complex table structures.
第２図は第１図における基板の一部拡大図である。FIG. 2 is a partially enlarged view of the substrate in FIG. 1.
第２図に示すように１基板１上に網目状の導体２が形成
され、能動素子３の電極部と導体２のクロス部９とをボ
ンディングワイヤ７によシワイヤポンディング接続して
いる。かかる導体２の導体クロス部９はボンディング接
続ができるように多少太く形成されている。また、導体
２の不要導体切断部６は縦、横両方向にＣＡＤ装置等に
より切断を行うことが出来る。更に１基板ｌ上の導体ク
ロス部９からは外部接続用のリード部８にボンディング
ワイヤ７によシボンディング接続されている。As shown in FIG. 2, a mesh conductor 2 is formed on one substrate 1, and the electrode portion of the active element 3 and the cross portion 9 of the conductor 2 are connected by bonding wire 7 by wire bonding. The conductor cross section 9 of the conductor 2 is formed to be somewhat thick so as to enable bonding connection. Further, the unnecessary conductor cutting portion 6 of the conductor 2 can be cut both vertically and horizontally using a CAD device or the like. Further, a conductor cross section 9 on one substrate l is connected to a lead section 8 for external connection by bonding wire 7.
このようなハイブリッドＩＣを構成することにより、あ
らゆる回路パターンの設計に対応でき、開発工数や短納
期化等を実現することができる。By configuring such a hybrid IC, it is possible to respond to the design of any circuit pattern, and it is possible to realize reductions in development man-hours and delivery times.
以上説明したように、本発明の混成集積回路装置は基板
全体に網目状の導体を形成したものを準備しておき回路
に応じてＣＡＤ等を利用し部品配置及び導体引回しの作
業を行うことによシ、回路毎にパターンを設計しマスク
を作らｋくてもよいという効果がある。すなわち、従来
の開発工数と比べ開発工数は半分以下となり、短納期対
応に非常に有効となる。従って、開発費は当然安価とカ
シ、量産品においても基板の統一化がなされるので安価
となる。As explained above, in the hybrid integrated circuit device of the present invention, a circuit board with a mesh conductor formed over the entire board is prepared, and parts placement and conductor routing work is performed using CAD etc. according to the circuit. Another advantage is that it is not necessary to design a pattern and create a mask for each circuit. In other words, the development man-hours are less than half of the conventional development man-hours, making it extremely effective for short delivery times. Therefore, development costs are naturally low, and mass-produced products are also inexpensive because the substrates are standardized.
尚、本発明においてもレーザー等を用いて１枚づつ導体
をカットしなければならないが、厚膜印刷抵抗を用いて
いるハイブリッドＩＣはほとんど抵抗値の調整のために
トリミングをしているので、本発明における導体切断工
数が特別な工数アップになるということもない。In the present invention, the conductors must be cut one by one using a laser, etc., but since most hybrid ICs using thick-film printed resistors are trimmed to adjust the resistance value, this method is not suitable for this invention. There is no particular increase in the number of man-hours required for cutting the conductor in the invention.
第１図（ａ） 、 （ｂ）はそれぞれ本発明の一実施例
を説明するだめの工程順に示した混成集積回路部品搭載
基板の平面図、第２図は第１図における基板の一部拡大
図、第３図は従来の一例を説明するための混成集積回路
装置基板の平面図である。
１・・・・・・基板、２・・・・・・導体、３・・・・
・・能動素子、４・・・・・・チップコンデンサ、５・
・・・・・チップ抵抗、６・・・・・・導体切断部、７
・・・・・・ボンディングワイヤ、８・・・・・・リー
ド部、９・・・・・・導体クロス部。
代理人 弁理士 内 原 晋（゛′：第１（２）
第２図1(a) and 1(b) are plan views of a board on which a hybrid integrated circuit component is mounted, respectively, shown in the order of steps to explain an embodiment of the present invention, and FIG. 2 is a partially enlarged view of the board in FIG. 1. 3 are plan views of a hybrid integrated circuit device board for explaining an example of the conventional technology. 1...Substrate, 2...Conductor, 3...
...Active element, 4...Chip capacitor, 5.
...Chip resistor, 6...Conductor cutting section, 7
. . . Bonding wire, 8 . . . Lead section, 9 . . . Conductor cross section. Agent: Susumu Uchihara, Patent Attorney (゛': No. 1 (2) Figure 2
Claims (1)
載された能動素子および受動素子と、前記導体をステッ
チ側となるように前記能動素子および受動素子と接続さ
れるボンディングワイヤと、前記導体のうち不要な導体
部分を切断し所定の配線等を形成するための導体切断部
とを含むことを特徴とする混成集積回路装置。a conductor formed in a mesh shape on a substrate; an active element and a passive element mounted on the conductor; a bonding wire connected to the active element and the passive element so that the conductor is on the stitching side; A hybrid integrated circuit device comprising a conductor cutting section for cutting unnecessary conductor portions of the conductors to form predetermined wiring or the like.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13215687A JPS63296289A (en) | 1987-05-27 | 1987-05-27 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP13215687A JPS63296289A (en) | 1987-05-27 | 1987-05-27 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63296289A true JPS63296289A (en) | 1988-12-02 |
Family
ID=15074672
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP13215687A Pending JPS63296289A (en) | 1987-05-27 | 1987-05-27 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63296289A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006134919A (en) * | 2004-11-02 | 2006-05-25 | Jtekt Corp | Electric wiring board and its manufacturing method |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4843162A (en) * | 1971-10-02 | 1973-06-22 | ||
| JPS54113863A (en) * | 1978-02-24 | 1979-09-05 | Univ Tokai | Printed circuit board |
-
1987
- 1987-05-27 JP JP13215687A patent/JPS63296289A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4843162A (en) * | 1971-10-02 | 1973-06-22 | ||
| JPS54113863A (en) * | 1978-02-24 | 1979-09-05 | Univ Tokai | Printed circuit board |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006134919A (en) * | 2004-11-02 | 2006-05-25 | Jtekt Corp | Electric wiring board and its manufacturing method |
| JP4496922B2 (en) * | 2004-11-02 | 2010-07-07 | 株式会社ジェイテクト | Electrical wiring board and method of manufacturing the same |
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