KR0175024B1 - Delay Control Circuit Using Register File - Google Patents

Abstract

A delay control circuit using a register file is included. The present invention relates to a delay control circuit using a register file having n delay stages connected in series, wherein the number of unit delay circuits of each of the n delay stages, i.e., the number of resistors and capacitors, is varied. By varying the stage delay values, the delay values can be arbitrarily adjusted by a combination of register values assigned to the respective delay stages.

In addition, when the required delay value is large, the number of delay stages (Number) and the number of registers can be significantly reduced compared to the prior art, thereby reducing the chip area.

Description

Delay Control Circuit Using Register File

1 is a diagram illustrating a unit delay circuit composed of a resistor and a capacitor.

2 is a diagram illustrating a delay control circuit using a conventional register file.

3 is a diagram illustrating a delay adjustment circuit using a register file according to an embodiment of the present invention.

The present invention relates to a delay control circuit in a semiconductor device, and more particularly, to a delay control circuit using a register file.

In the case where a delay between elements is to be formed in a circuit of a semiconductor device, the most commonly used conventional method is to connect a delay chain by serially connecting a unit delay circuit composed of a resistor and a capacitor as shown in FIG. Configure. The number of unit delay circuits of the delay chain is determined to suit the desired delay value in consideration of process variables in design.

However, in a delay chain constructed by connecting the unit delay circuits in series, a delay value measured in the actual manufacturing state due to a process variable in a manufacturing process may be significantly different from a delay value intended for design.

In addition, if such a case occurs and the chip malfunctions, redesign is inevitable and there is a drawback that the burden of having to go through the reprocessing is required.

As another method for solving the shortcomings of the delay chain, a delay control circuit using a register file is used. FIG. 2 is a diagram illustrating a delay control circuit using a conventional register file.

Referring to FIG. 2, n control data allocated by one bit to each of n delay stages (1, 2, 3, ..., n) connected in series with each other in the delay control circuit (Centrol Data) Are stored in a register file 21 having n bits of registers according to the desired delay value.

Then, when an input signal is input through the data input line 23 connected to the input terminal of the first delay stage 1, the control data of the register of the register file 21 allocated to the first delay stage 1 is When low, the first transmission gate TM1 and the second transmission gate TM2 are turned on so that the input signal is composed of one resistor R and one capacitor C. Delayed by a predetermined value through (27) and then output to the output terminal of the first delay stage (1).

In addition, when the control data of the register of the register file 21 allocated to the first delay stage 1 is high, the control data is inverted by the inverter I so that the third transmission gate ( TM3) is turned on so that the input signal is output to the output terminal of the first delay stage 1 without delay.

The input signals passing through the first delay stage 1 are serially connected to each other in the same operation as in the first delay stage 1 according to the control data of the registers of the register file 21 assigned to each stage. A data output line connected to the output terminal of the nth delay stage, which is the last stage, after passing sequentially through the second delay stage 2, the third delay stage 3, ..., and the nth delay stage n. 25, the input signal having a desired delay value is output.

However, the delay control circuit using the conventional register file,

Since the delay circuits 27 of each of the n delay stages (1, 2, 3, ..., n) are composed of only one resistor and one capacitor, the delay stage required when the required delay value is large There is a problem that the number (Number) and the number of registers is increased, thereby occupying a large area of the chip.

Accordingly, an object of the present invention is to solve the problems of the prior art, by varying the delay value of each delay stage by varying the number of unit delay circuits of each delay stage, that is, the number of resistors and capacitors. The purpose of the present invention is to provide a delay control circuit using a register file that can arbitrarily adjust the delay value by using a combination of register values allocated to each delay stage and reduce the area of the chip.

Delay adjustment circuit using the register file of the present invention for achieving the above object,

According to the state of the control data of the register allocated one bit to each delay stage, each of the n delay stages for outputting the input signal through the delay circuit or without the delay circuit is output. The number of unit delay circuits which are serially connected from the nth stage to the nth stage and formed in the delay circuits of the n delay stages is one in the first stage, two in the second stage, and the nth stage. n individual delay control circuits;

And a register file having n registers for storing n control data allocated one bit to each of the n delay stages of the delay control circuit.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

3 is a circuit diagram of a delay control circuit using register files according to an exemplary embodiment of the present invention. Referring to FIG.

Inverter (I) receiving and receiving control data, a first transmission gate (TM1) which is turned on when the control data is low and passes the input signal received at an input terminal, and the first transmission gate (TM1). A delay circuit 37 connected to the delay circuit 37 for delaying the input signal, a second transmission gate TM2 connected to the delay circuit and passing on the delayed input signal when the control data is low, and the control An output terminal connected to the third transmission gate TM3, the second transmission gate TM2, and the third transmission gate TM3 that are turned on when the data is high to pass the input signal received by the input without delay. Each of the n delay stages 11, 12, 13, ..., 1n having a plurality of delay stages is sequentially connected from the first stage to the nth stage, thereby forming a delay control circuit.

In the delay circuit 37 formed at each of the n delay stages 11, 12, 13, ..., 1n, the number of unit delay circuits formed of a resistor R and a capacitor C is numbered. The first stage is connected one by one, the second stage is two, ... and the nth stage is connected in series.

In addition, n control data allocated by one bit are stored in each of the n delay stages 11, 12, 13, ..., 1n, and the n delay stages 11, 12 are stored. A register file 31 having n-bit registers connected to the input terminal of each inverter I of 13, ..., ..., 1n is constructed.

A data input line 33 for receiving an input signal is connected to an input terminal of the first delay stage 11 among the n delay stages 11, 12, 13, ..., 1n, and an nth delay stage 1n. The data output line 35 is connected to the output terminal of the "

Looking at the operation of the delay control circuit using the register file of the present invention with reference to FIG.

In order to obtain a desired delay value in a delay control circuit in which each of the n delay stages 11, 12, 13, ..., 1 n having different delay values are connected in series,

First, n control data allocated by one bit to each of the n delay stages 11, 12, 13, ..., 1n are set to n bits according to the desired delay value. It is stored in the register file 31 which has a register.

Then, when the input signal is input through the data input line 33 connected to the input terminal of the first delay stage 11,

When the control data of the register of the register file 31 allocated to the first delay stage 11 is low, the first transmission gate TM1 and the second transmission gate TM2 are turned on. The input signal is delayed by a predetermined value through the delay circuit 37 and then output to the output terminal of the first delay stage 11.

In addition, when the control data of the register of the register file 31 allocated to the first delay stage 11 is high, the control data is inverted by the inverter I so that the third transmission gate ( TM3) is turned on so that the input signal is output to the output terminal of the first delay stage 11 without delay.

The input signal output through the first delay stage 11 and output to the output stage is the same as that of the first delay stage 11 according to the control data of the register of the register file 31 assigned to each stage. After passing through the second delay stage 12, the third delay stage 13, ..., and the nth delay stage 1n sequentially connected to each other,

The input signal having a desired delay value is output through the data output line 35 connected to the output terminal of the last n-th delay stage 1n.

In the delay control circuit using the register file according to the present invention described above, the delay value of each delay stage is changed by varying the number of unit delay circuits of each delay stage, that is, the number of resistors and capacitors. Delay values can be adjusted arbitrarily by a combination of register values assigned to.

In addition, when the required delay value is large, the number of delay stages (Number) and the number of registers can be significantly reduced compared to the prior art, thereby reducing the chip area.

In addition, the present invention is not limited to the above embodiments, and it is apparent that various modifications may be made by those skilled in the art within the technical spirit of the present invention.

Claims (5)

In a delay control circuit of a semiconductor device, an input signal is output through a delay circuit or the delay circuit is output according to a control data state of a register allocated by one bit to each delay stage. Each of the n delay stages to be output without passing through is sequentially connected from the first stage to the nth stage, and the number of unit delay circuits formed in the delay circuits of the n delay stages is one in the first stage. A delay adjusting circuit having two second stages, ..., n-th stages; And a register file having n registers for storing n control data allocated one bit to each of n delay stages of the delay control circuit. The delay control circuit according to claim 1, wherein the unit delay circuit comprises a resistor and a capacitor having a predetermined value. The method of claim 1, wherein when the state of the control data is low, the input signal is output through a delay circuit, and when the state of the control data is high, the output is not transmitted through the delay circuit. And a delay control circuit using a register file. A delay control circuit of a semiconductor device, comprising: an inverter (I) for receiving control data and inverting the same, and passing the input signal received at an input terminal when the control data is low (On). A delay circuit 37 connected to the first transmission gate TM1, the first transmission gate TM1 and delaying the input signal, and an input that is connected to the delay circuit and turned on when the control data is low A second transmission gate TM2 for passing a signal, a third transmission gate TM3 that is turned on when the control data is high, and passes the input signal received at an input terminal without delay, and the second transmission gate TM2. ) And n delay stages (11, 12, 13, ..., 1n) each having an output terminal connected to the third transmission gate (TM3) sequentially from the first stage to the nth stage. In the delay circuit 37 which is connected in series and formed in the n delay stages 11, 12, 13, ..., 1n, the number of unit delay circuits is one in the first stage, A delay control circuit having two second stages, ..., n-th stages connected in series; N control data allocated by one bit are stored in each of the n delay stages 11, 12, 13, ..., 1n of the delay control circuit, and the n delay stages ( A register file 31 having n-bit registers connected to an input terminal of each inverter I of 11, 12, 13, ..., 1n; A data input line (33) connected to an input terminal of the first delay stage (11) of the n delay stages (11, 12, 13, ..., 1n) of the delay control circuit and receiving an input signal; A data output line 35 connected to an output terminal of the nth delay stage 1n among the n delay stages 11, 12, 13, ..., 1n of the delay control circuit and outputting the delayed input signal; Delay control circuit using a register file, characterized in that provided. The delay control circuit according to claim 4, wherein the unit delay circuit comprises a resistor and a capacitor having a predetermined value.