JPH0772221A - Skew adlusting circuit - Google Patents

Abstract

PURPOSE:To easily integrate a circuit, to reduce the scale of the circuit and to eliminate a need for an increase in the scale of the circuit even when the number of pins for a tester is increased by a method wherein a gate delay circuit and a selector are cascade-connected. CONSTITUTION:Gate delay circuits 2B, 4B, 8B, 16B are constituted in such a way that two stages, four stages, eight stages and 16 stages of respective delay gates 1B are connected in series, and the delay amount of two times, four times, eight times and 16 times of the delay amount of the respective gates 1B is obtained. In addition, selectors 1A to 5A select either of two input signals which are input to a first input terminal A and a second input terminal B. When data bit signals DB27 to DB23 which are applied to respective selection terminals S exist, the terminal B is selected, and, when they do not exist, the terminal A is selected. The output signal of the selector 5A is input to the input terminal of a differential receiver 6A. Then, the amount of the signal is adjusted fine by an analog signal which is decided by delay control signals 28 to 31 from a D/A converter 7A.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a skew adjustment circuit, and in particular, when an IC device is tested by an IC tester, the timing of the driver waveform input to the measuring device is corrected to compensate for variations from pin to pin. This is about the skew adjustment circuit used.

[0002]

2. Description of the Related Art Next, a configuration of a conventional skew adjusting circuit is shown in FIG. 1Z is a digital-to-analog converter (hereinafter referred to as DAC), which controls the analog voltage of the output signal by the data bits input to the 8-bit data bit terminals DB24 to DB31. 2Z is a voltage adjustment type high speed variable delay line (hereinafter referred to as PD), which variably controls the delay amount of the input signal S by the analog voltage of the output signal of the DAC 1Z. The output signal S is taken out as an output signal S via the NOR gate 3Z and input to the PD 4Z. The PD 4Z variably controls the output signal of the NOR gate 3Z with the analog voltage of the output signal of the DAC 1Z to change the delay amount and output the output signal S0.

That is, in the skew adjusting circuit shown in FIG.
Depending on the combination of the data bits input to the data bit terminals DB24 to DB31 of the DAC1Z, the size of the analog voltage is varied, and the input signal S and the output signal S are delayed by a delay amount corresponding to this variable amount, and the total An output signal S0 having a given delay amount is obtained.

Next, the operation of the circuit shown in FIG. 3 will be briefly described with reference to FIG. FIG. 4 shows the data bit terminal DB24.
~ PD2Z and PD4Z when a signal is applied to DB31
5 is a chart showing the relationship of changes in the delay amount of the.

In the DAC1Z, the data bit terminal D
When only B31 has a signal, the output signal of PD2Z is delayed by 5 PS (picoseconds) with respect to the input signal S, and PD4
At Z, an additional 5P is applied to the output signal of PD2Z.
S delay. Therefore, the PD4Z
The output signal S0 is delayed by 10 PS.

Further, in order to delay the output signal S0 of the PD4Z by 160 PS with respect to the input signal S, the data bit terminals DB27, DB28 and DB30 of the DAC1Z are set to have signals. Then, the output signal of PD2Z is delayed by 80 PS, and the output signal of PD4Z is delayed by 80 PS with respect to the output signal. Therefore, the output signal S0 is 160 with respect to the input signal S
PS will be delayed. Data bit terminals DB24 to D
When all B31 have a signal, the output signal S is 3200 PS (= 3.2 NS (nano.sec)) with respect to the input signal S
It will be delayed.

[0007]

In the conventional queue adjusting circuit, since analog circuits are used as DA1Z, PD2Z, and 4Z, it is difficult to integrate the circuits, so that the skew adjusting circuits are required by the same number as the number of pins of the tester. Become. Therefore, there is a problem that the circuit scale also increases as the number of pins increases.

The present invention provides a skew adjustment circuit which facilitates circuit integration by adopting a digital logic circuit, reduces the circuit scale, and does not need to increase the circuit scale even if the number of pins of the tester increases. The purpose is to provide.

[0009]

To achieve this object, the present invention delays the first input signal of the ^n-th stage (n is a positive integer) by 2 ^n-1 times the reference gate delay time. n-stage gate delay circuit 1 for outputting as the n-th second input signal
B, 2B, 4B, 8B, 16B, the first input signal and the second
Input signals are selectively input, and n stages of selectors 1A, 2A, 3A, 4A, and 5A that selectively output one of the input signals to the output side as the first input signal of the (n + 1) th stage are set and gated. Delay circuits 1B, 2B, 4B, 8B, 16B and selectors 1A, 2A, 3A, 4A, 5A are cascaded in n stages, and a predetermined selection signal is applied to each selector 1A, 2A, 3A, 4A, 5A. , N-th stage selector 5A delays an input signal by a predetermined time and outputs the delayed signal.

[0010]

In the present invention, the gate delay circuit which can be constituted by the digital logic circuit is used as the element for determining the delay amount. The gate delay circuit is configured by connecting a plurality of delay gates in series, and the delay amount is determined by the number of connection stages. A plurality of stages of gate delay circuits having a delay amount that is a multiple of 2 are prepared, and these are connected in cascade through a selector. When the selection signal is applied to the selection terminal of the selector of each stage, the input signal passing through each stage is output after being delayed by a predetermined amount. When the selection signal is not applied, the input signal is output without delay.

Therefore, by changing the combination pattern of the selection signals applied to the selection terminals of each stage,
It is possible to obtain output signals with various delay amounts. Since the selectors and gate delay circuits can all be configured as digital logic circuits, integration is facilitated and an increase in circuit scale is prevented.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, FIG. 1 shows the configuration of a skew adjusting circuit according to an embodiment of the present invention. According to the present invention, selectors 1A to 5A which can be easily configured by digital logic circuits
And delay gate 1B and gate delay circuits 2B, 4B, 8
B · 16B (hereinafter collectively referred to as a gate delay circuit) is used.

Gate delay circuit 2B / 4B / 8B / 16B
Are delay gates 1B connected in series in two stages, four stages, eight stages, and 16 stages, respectively.
The delay amounts of 2 times, 4 times, 8 times, and 16 times of the delay amount of 1 are obtained. The selectors 1A to 5A perform an operation of selecting any one of the two input signals input to the first input terminal A and the second input terminal B, and each selector terminal S
The second input terminal B is selected when it is present and the first input terminal A is selected when it is not present, depending on the presence or absence of the data bit signals DB27 to DB23 applied to.

The selector 1A receives the input signal A and the output signal B of the delay gate 1B as a data bit signal D for delay control.
Controlled by B27, one of them is selected and output as an output signal C to the first input terminal of the selector 2A and the input terminal of the gate delay circuit 2B for two gates. Selector 2A
Controls the output signal C of the selector 1A and the output signal D of the gate delay circuit 2B corresponding to two stages of gates by the delay control signal DB26, and selects one of them as the output signal o to the first input terminal of the selector 3A. It outputs to the input terminal of the gate delay circuit 4B for four gates.

The selector 3A controls the output signal of the selector 2A and the output signal of the gate delay circuit 4B for four stages of gates by the delay control signal DB25, selects either one and outputs the output signal key of the selector 4A. The signal is output to the first input terminal and the input terminal of the gate delay circuit 8B for eight gates.
The selector 4A has a gate 8 and an output signal key of the selector 3A.
The output signal Q of the gate delay circuit 8B for each stage is controlled by the delay control signal DB24, and any one of them is selected and the output signal is input to the first input terminal of the selector 5A and the gate delay circuit 16B for 16 stages of gates. Output to the terminal.

The selector 5A controls the output signal K of the selector 4A and the output signal C of the gate delay circuit 16B for 16 stages of gates by the delay control signal DB23, selects either one and outputs the output signal as a differential receiver. Output to 6A.
7A is a D / A converter (hereinafter referred to as DAC), which is controlled by delay control signals DB28 to DB31 and outputs a predetermined analog voltage output signal to the differential receiver 6A.
Output to.

The output signal of the selector 5A is input to the input terminal of the differential receiver 6A and the delay control signals DB28 to DB31 applied to the control terminals of the differential receiver 6A.
The delay amount of the output signal is finely adjusted by the analog output signal S determined by

FIG. 2 is a chart showing the relationship of changes in the delay amount at each stage when a signal is applied to the delay control data bit signal terminals DB23 to DB31. When only one bit of the delay control signal terminal DB24 has a signal, the selectors 1A, 2A, 3A and 5A output the signal on the side of the first input terminal A, and only the selector 4A outputs the delay control signal DB.
By 24, the delayed signal on the side of the second input terminal B that has passed through the gate delay circuit 8B instead of the side of A is output. Therefore, the output signal S is delayed by 800 PS with respect to the input signal A due to the delay of the gate delay circuit 8B.

Further, the output signal S is set to 6 with respect to the input signal A.
To delay by 60 PS, delay control signals DB25 and 26
・ Set the 4 bits of 28 and 30 to have a signal. Then, the selectors 1A, 4A, 5A output the signal on the side of the first input terminal A rather than the side of the second input terminal B, and the selectors 2A, 3
Since A outputs the delayed signal on the B side that has passed through the gate delay circuit instead of the A side by the delay control signals DB25 and 26, the delay is 60 by the delay of the gate delay circuits 4B and 2B.
Delayed by 0PS and delayed by delay control signals DB28 and D30
60 PS is delayed by the AC 7A and the differential receiver 6A. Therefore, the output signal S is delayed by 660 PS with respect to the input signal A.

Further, delay control signals DB23 to DB31
When all 9 bits of are set to have a signal, selector 1A ・ 2
From A, 3A, 4A, and 5A, delay control signals DB23 to
The DB 27 outputs the delayed signal on the side of the second input terminal B which has passed through the gate delay circuits 1B, 2B, 4B, 8B and 16B instead of the side of the first input terminal A. 31 due to the delay of the gate delay circuit 1B / 2B / 4B / 8B / 16B
Delayed by 00 ps (3.1 ns), delay control signal DB28
~ DB31 delays 100 ps between DAC 7A and differential receiver 6A. Therefore, the output signal S is delayed by 3200 ps (3.2 ns) with respect to the input signal A.

[0021]

In the conventional skew adjusting circuit, it is difficult to integrate the circuit because it is an analog circuit that requires LC. However, by using the skew adjusting circuit of the present invention, the circuit can be easily integrated. Therefore, the circuit scale can be reduced to about 1/4 of the conventional circuit scale. Also, various delay amounts can be realized by adding a gate delay circuit.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a skew adjustment circuit according to an embodiment of the present invention.

FIG. 2 is a chart showing a relationship of changes in delay amount at each stage of the gate delay circuit.

FIG. 3 is a configuration diagram of a conventional skew adjustment circuit.

FIG. 4 is a diagram showing a relationship of changes in the delay amount of a conventional PD.

[Explanation of Codes] 1A / 2A / 3A / 4A / 5A Selector 6A Differential Receiver 7A D / A Converter (DAC) 1B Delay Gate 2B / 4B / 8B / 16B Gate Delay Circuit

Claims (1)

[Claims] 1. An n-stage gate delay for delaying the first input signal of the ^n- th stage (n is a positive integer) by 2 ^n-1 times the reference gate delay time and outputting it as the second input signal of the n-th stage. Circuit (1B,
2B, 4B, 8B, 16B), the first input signal and the second input signal are selectively input, and one of the input signals is sent to the output side as the (n + 1) th first input signal. N-stage selector (1A, 2A, 3A,
4A, 5A), gate delay circuit (1B, 2B, 4B, 8B, 16B) and selector (1A, 2A, 3A
A, 4A, 5A) are connected in cascade with n stages, and each selector (1A, 2A, 3A
A, 4A, 5A) applies a predetermined selection signal to the nth stage selector
A skew adjusting circuit which delays an input signal by a predetermined time from (5A) and outputs the delayed signal.