JPH10173496A - Phase compensating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a phase compensating circuit capable of automatically performing skew compensation of an input signal for a short time and of adjusting also a skew between signals providing a phase difference from the first. SOLUTION: Delay signals DO1 to DO5 that and input signal IPT is delayed by different delay times by plural delay circuits 101 to 105 respectively, are generated. Then, it is determined whether or not the phases of the output signals DO1 to DO5 of the plural delay circuits 101 to 105 are within a prescribed phase determination period. If it is determined that the phase of the output signal of the delay circuit is within the phase determination period by the phase determining circuit 110, the output signal of that delay circuit is selected by a selecting circuit 120 as the output OPT of the above phase compensating circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a phase correction circuit for controlling a skew, and more particularly to a phase correction circuit for automatically and quickly correcting a skew of an input signal. Also relates to a phase correction circuit that can be adjusted.

[0002]

2. Description of the Related Art Conventionally, in a digital circuit, a control signal such as a clock signal is distributed to circuit components on a semiconductor chip or a circuit board to control circuit operation. When each circuit component is randomly arranged at various positions on a semiconductor chip or a circuit board, a wiring distance for transmitting a control signal is different, and as a result, in each circuit component caused by a propagation delay, The difference between the arrival times of the control signals is called skew, and appears as a problem such as clock overlap.

In addition, skew can be reduced by, for example, equalizing the length of control signal wiring by arranging circuit components on a semiconductor chip or a circuit board or by wiring control signals. Can not. This skew control has become an important problem to be solved in digital circuit design, especially with the increase in circuit operating frequency in recent years.

In order to control and adjust such skew, various skew correction circuits have been conventionally proposed. For example, U.S. Patent Publication "US Patent 5,
414, 381 ”,“ METHOD OF AD ”
"JUSTING FOR CLOCK SKEW: Clock Skew Adjustment Method" (first conventional example) proposes a method of adjusting the delay time manually while observing the delay value of the delay circuit with an oscilloscope or the like.

[0005] Further, US Patent Publication “US Patent
5,384,781 "AUTOMATIC
SKEW CALIBRATION FOR MUL
TI-CHANNEL SIGNAL SOURCE
S: Automatic Skew Adjustment for Multi-Channel Signal Source "(second conventional example) proposes a method of automatically adjusting a delay time using a controller (microprocessor) and a phase determination circuit.

[0006]

However, in the clock skew adjustment method of the first prior art, since the adjustment of the delay time is performed manually, the adjustment requires time and effort, and the adjustment is not easy. There has been a problem that there is no guarantee that a desired delay adjustment can be made whenever necessary.

Further, in the automatic skew adjustment for the multi-channel signal source of the second conventional example, since the adjustment operation is sequential, it takes time for the adjustment.
There is a problem that the circuit scale may be increased because a microprocessor is required.

Further, the adjustment method of the second conventional example can be applied only to the comparison of signals having a phase difference because the phase determination circuit can only determine that the phase difference of the signal is zero. There was also a problem that it could not be done.
For example, as for the skew between the DS-LINK coded data signal and the strobe signal, only one of the signals makes a level transition at a time. Therefore, when both signals have skew, the skew is determined. Cannot be performed, and skew adjustment cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and has as its object to automatically and quickly perform skew correction and to reduce skew between signals having a phase difference. An object of the present invention is to provide an adjustable phase correction circuit.

[0010]

In order to solve the above-mentioned problems, a phase correction circuit according to the present invention comprises a plurality of delay circuits for delaying an input signal by different delay times and outputting the same, and an output of the plurality of delay circuits. A phase determination circuit that determines whether the phase of the signal is within a predetermined period, and when the phase determination circuit determines that the phase of the output signal of the delay circuit is within a predetermined period, And a selection circuit for selecting and outputting the output signal of the delay circuit.

In the phase correction circuit according to the present invention, the phase determination circuit may correspond to each of the plurality of delay circuits and determine whether a phase of an output signal of the corresponding delay circuit is within a predetermined period. Are provided with a plurality of sub-phase determining circuits.

Further, in the phase correction circuit according to the present invention, when the selection circuit determines that the phase of the output signal of the corresponding delay circuit is within a predetermined period by the sub-phase determination circuit, The output circuit includes a plurality of output selection units that output an output signal of the delay circuit and set the output to a high impedance state when it is determined that the output signal is not input.

Further, in the phase correction circuit according to the present invention, the sub-phase determination circuit stores first output means of a corresponding delay circuit at a start timing of the predetermined period,
Second storage means for storing the output signal of the corresponding delay circuit at the end timing of the predetermined period, wherein a true value is set when the contents of the first storage means and the contents of the second storage means are different. And outputs a signal that becomes a false value when they match.

Further, in the phase correction circuit according to the present invention, the outputs of the plurality of delay circuits have the same drivability with respect to voltage levels representing a true value and a false value, respectively.

Further, the phase correction circuit of the present invention delays a predetermined reference signal by a predetermined time and outputs a first timing signal defining a start timing of the predetermined period.
And a second variable delay circuit that delays the reference signal by a predetermined time and outputs an end timing signal that defines the end timing of the predetermined period.

Further, preferably, the phase correction circuit of the present invention is connected in series at a plurality of stages.

According to the phase correction circuit of the present invention, a plurality of delay circuits generate a delay signal obtained by delaying an input signal by different delay times, respectively, and the phase determination circuit determines a phase of output signals of the plurality of delay circuits. Is within a predetermined phase determination period. Then, when the phase determination circuit determines that the phase of the output signal of the delay circuit is within the phase determination period, the output signal of the delay circuit is selected as the output of the phase correction circuit by the selection circuit. .

As described above, the delay time of the input signal is adjusted by selecting the delay circuit so that the edge of the signal obtained by delaying the input signal falls within the predetermined phase determination period, and the input signal is delayed by the delay time. Since an input signal is used as an output signal, skew correction can be performed automatically and in a short time, and skew between signals having a phase difference can be adjusted.

Further, according to the phase correction circuit of the present invention, the phase of the output signal of the delay circuit corresponding to the sub-phase determination circuit is determined by the sub-phase determination circuit provided in correspondence with each of the plurality of delay circuits. If it is determined that it is within the phase determination period, the output signal of the delay circuit is output; otherwise, the output is held in the high impedance state.

Thus, for example, at the stage of circuit design,
If the number of sets of delay circuits, sub-phase determination circuits and selectors is arbitrarily set, and the delay time interval of the delay circuit is arbitrarily set, the skew adjustment accuracy and the adjustment range can be adjusted to the accuracy and accuracy according to the design specifications. It is possible to set a range. Further, when the plurality of sub-phase determination circuits determine that the phase of the output signal of the corresponding delay circuit is within the phase determination period, that is, even when the outputs of the plurality of selectors collide, the plurality of selectors The final output can be obtained in the form of averaging the output, and the timing accuracy can be improved.

In the phase correction circuit according to the present invention, a start timing signal is output by the first variable delay circuit and an end timing signal is output by the second variable delay circuit based on the reference signal. Is defined.
In the sub-phase determining circuit, the output signal of the delay circuit corresponding to the sub-phase determining circuit is controlled by the start timing signal to the first signal.
And the second storage means under the control of the end timing signal. If the contents of the first storage means and the contents of the second storage means are different, the output is set to a true value to indicate that the phase of the output signal of the delay circuit is within the phase determination period, and not otherwise. In this case the output is false.

As described above, the delay time of the input signal is adjusted by defining the desired phase determination period and selecting the delay circuit so that the edge of the signal obtained by delaying the input signal falls within the phase determination period. Since the input signal delayed by the delay time is used as the output signal, skew correction can be performed automatically and in a short time, and skew between signals having a phase difference can be adjusted.

Further, in the phase correction circuit of the present invention, the output of the phase correction circuit is connected in series as a plurality of input signals to the next-stage phase correction circuit. For example, a finer skew adjustment can be performed by setting a smaller phase adjustment period of the phase correction circuit and a smaller step of the delay time of the delay circuit as going to the phase correction circuit in the subsequent stage. Becomes possible.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of a phase correction circuit according to the present invention will be described in detail with reference to the drawings in the order of [first embodiment] and [second embodiment].

[First Embodiment] FIG. 1 is a configuration diagram of a phase correction circuit according to a first embodiment of the present invention. The phase correction circuit of the present embodiment determines a delay value such that the phase of the rising edge of the signal delayed from the input signal IPT falls within a predetermined phase determination period, and outputs an input signal delayed by this delay value. Things.

In FIG. 1, the phase correction circuit according to the present embodiment includes, as main components, five delay circuits 101 to 105 for delaying the input signal IPT by different delay times TD1 to TD5 and outputting the same, respectively. 101-105
A phase determination circuit 110 that determines whether the phases of the rising edges of the output signals DO1 to DO5 are within a predetermined phase determination period, and the output signals DO1 to DO5 of the delay circuits 101 to 105 by the phase determination circuit 110. And a selection circuit 120 for selecting, as the output of the phase correction circuit, the output signal of the delay circuit included in the phase determination period when it is determined that the phase is within the phase determination period. Have been.

The other components include a first variable delay circuit 131 for generating a start timing and an end timing of the phase determination period from the reference signal BCK, and a second variable delay circuit 131 for generating the second timing.
Variable delay circuit 132 and buffers 141 to 105 that drive output signals DO1 to DO5 of delay circuits 101 to 105, respectively.
145, buffers 151 and 152 for driving the output signals LDCK and TLCK of the first variable delay circuit 131 and the second variable delay circuit 132, and a buffer 150 for driving the output of the selection circuit 120.

Hereinafter, the operation and operation of each component of the phase correction circuit of the present embodiment will be described in detail with reference to the timing chart of FIG. 2 and the explanatory diagrams of FIG. 3 and FIG.

First, the first variable delay circuit 131 is configured as shown in FIG.
As shown in (a) and (b), the reference signal BCK is delayed by a predetermined time TLD, and the start timing of the phase determination period TP is defined as the rising edge of the start timing signal LDCK. Further, the second variable delay circuit 132
Is a reference signal BC as shown in FIGS. 2 (a) and 2 (c).
K is delayed by a predetermined time TTL, and the end timing of the phase determination period TP is defined as the rising edge of the end timing signal TLCK.

Further, the delay circuits 101 to 105
As shown in (e) to (i), the input signal IPT shown in FIG.
This is to generate output signals DO1 to DO5 delayed by D5.

The phase determination circuit 110 corresponds to each of the five delay circuits 101 to 105 and determines whether the phase of the rising edge of the output signal of the corresponding delay circuit falls within the phase determination period TP. It is configured to include five sub phase determination circuits 111 to 115 for determining whether or not the sub phase determination circuits 111 to 115 are used.

The sub-phase determination circuit 111 includes D-type flip-flops 201 and 202, a latch 203, a NOT gate circuit 204, and a two-input NAND gate circuit 205. The other sub-phase determination circuits 112 to 115 are also provided. The configuration is the same as that of the sub phase determination circuit 111.

For example, in the sub-phase determination circuit 111, the flip-flop 201 corresponds to the first storage means, and outputs the output signal DO1 of the corresponding delay circuit 101 to the start timing signal LDC indicating the start timing of the phase determination period TP.
Sample with K. The flip-flop 202
Corresponds to the second storage means, and the corresponding delay circuit 101
Is sampled with an end timing signal TLCK indicating the end timing of the phase determination period TP.

The two-input NAND gate circuit 205 performs a NAND operation on a signal obtained by inverting the output of the flip-flop 201 by the NOT gate circuit 204 and the output of the flip-flop 202. That is, 2-input NAN
The D gate circuit 205 outputs the output signal DO of the delay circuit 101.
1 at the start timing of the phase determination period TP.
L level and “H” level at the end timing of the phase determination period TP, that is, a true value when the phase of the rising edge falls within the phase determination period TP, and a false value otherwise. Is output.

For example, the output signal DO1 of the delay circuit 101
Changes from “L” level to “H” level after the start timing signal LDCK, the flip-flop 201
Is "0". Further, the output signal DO1 of the delay circuit 101 becomes “L” before the end timing signal TLCK.
When the level changes from “H” to “H”, the output of the flip-flop 201 becomes “1”. Thus, the outputs of the two flip-flops 201 and 202 are respectively "
When they are 0 "and" 1 ", the output signal D of the delay circuit 101
It can be seen that O1 is within the phase determination period TP.

The latch 203 latches the output of the two-input NAND gate circuit 205 at the timing of the sampling signal SMP and resets it at the timing of the reset signal RST. Note that the output of the latch 203 is output as a selection signal SL1 which is an output of the sub phase determination circuit 111. The selection signals SL2 to SL5 are similarly output from the other sub phase determination circuits 112 to 115.

Next, the selection circuit 120 is provided with five selectors 121 to 125 as output selection units respectively corresponding to the five sub phase determination circuits 111 to 115. For example, in the selector 121, the output signal D of the delay circuit 101 corresponding to the sub-phase determination circuit 111 is output.
If it is determined that the phase of the rising edge of L1 is within the phase determination period TP and the selection signal SL1 is output as a true value, the output signal DL1 of the delay circuit 101 is selected. High impedance terminal H
The output is set to a high impedance state by selecting iZ.

The outputs of the five selectors 121 to 125 are connected so as to be wired-ORed (Wired-OR), and the output of the wired OR 130 is sent via the buffer 150 to the output. This becomes the output signal OPT of the phase correction circuit.

The outputs of the five delay circuits 101 to 105 are connected to buffers 141 to 145 for driving output signals DO1 to DO5. Buffers 141 to
Reference numeral 145 denotes output signals DO1 to DO1 of the delay circuits 101 to 105.
DO5 is set so that the drive capability is the same for the voltage levels (“H” level and “L” level) represented by the true value “1” and the false value “0”, respectively.

FIG. 3 is a circuit diagram of the buffers 141 to 145. In addition to a NOT gate circuit 301, a p-channel MOS (PMOS) transistor 302, and an n-channel MOS (NMOS) transistor 303, which are a general buffer configuration, a current connected between the source of the PMOS transistor 302 and the power supply potential VCC. Source 304
(Drive current I0) and a current source 305 connected between the drain of the NMOS transistor 303 and the ground potential GND.
(Drive current I0).
The input of the buffer is supplied to a NOT gate circuit 301, and the output of the NOT gate circuit 301 is connected to a PMOS transistor 302 and an NMOS transistor 303. In addition, the drain of the PMOS transistor 302 and the source of the NMOS transistor 303 are connected to each other and output from the buffer.

That is, when the output nodes have the true value “1” and the false value “0” by the current source 304 and the current source 305, the output nodes are set so that the driving capabilities are the same for the voltage levels represented by the respective nodes. Is supplied with the current.

Next, the operation of the phase correction circuit of this embodiment will be described by applying specific numerical values to the delay time and the like. Here, the delay times TD1 to TD5 of the delay circuits 101 to 105 are represented by TD1 = 2 [ns] and T
D2 = 2.5 [ns], TD3 = 3 [ns], TD4 =
It is assumed that 3.5 [ns] and TD5 = 4 [ns] are set.

The specifications of the phase correction circuit are as follows: the phase of the rising edge of the input signal IPT is set to the reference signal BCK.
With a delay of 3 [ns]. Accordingly, the delay time TLD of the first variable delay circuit 131 and the delay time TTL of the second variable delay circuit 132 are set to TLD = 2.75 [ns] and TTL = 3.25 [n], respectively.
s] to define a phase determination period TP of 0.5 [ns].

Assuming that the input signal IPT has the relationship shown in FIGS. 2A and 2D with respect to the reference signal BCK, only the output signal DO2 of the delay circuit 102 becomes "L" at the start timing of the phase determination period TP. Since the level is “H” and the level is “H” at the end timing of the phase determination period TP, only the selection signal SL2 has a true value “1”, and the other selection signals SL1, SL2 to SL5 all have a false value “0”. ,
The selection circuit 120 selects the output signal DL2 of the delay circuit 102 and outputs it as an output signal OPT of the phase correction circuit via the buffer 150.

In this specific example, the number of sets of the delay circuit, the sub-phase determination circuit, and the selector is five, and the delay time interval of the delay circuit is set to 0.5 [ns].
The skew can be adjusted with an accuracy of 0.5 [ns] within the range of [s]. If the number of sets of the delay circuit, the sub-phase determination circuit and the selector and the delay time interval are different from those in this example, it is possible to further increase the accuracy of the skew adjustment and to widen the adjustment range. . Thus, the delay circuit,
If the number of sets of sub-phase determination circuits and selectors is set arbitrarily, and the delay time interval of the delay circuit is set arbitrarily, the adjustment accuracy and adjustment range of the skew adjustment can be adjusted according to the design specifications. Can be set.

In the specific example of FIG. 2, an example is shown in which only the phase of the rising edge of the output signal DO2 of the delay circuit 102 falls within the phase determination period TP. Depending on the set value of the time interval, the phases of the output signals of the plurality of delay circuits may fall within the phase determination period TP. In such a case, a plurality of selector outputs collide in the output signal OPT.

However, in the phase correction circuit of this embodiment, the output signals DO1 to DO of the delay circuits 101 to 105
5 is configured such that the outputs of the five buffers 121 to 145 and the five selectors 121 to 125 are wired logical OR so that the driving capability is the same for the “H” level and the “L” level. A final output signal OPT can be obtained by averaging a plurality of selector outputs, and timing accuracy can be improved.

FIG. 4 shows a timing chart in the case where the phases of the rising edges of the output signal DO1 of the delay circuit 101 and the output signal DO2 of the delay circuit 102 are included in the phase determination period TP. In such a case, in the phase correction circuit of the present embodiment, the output signal OPT
Is obtained as an intermediate signal between the output signal DO1 of the delay circuit 101 and the output signal DO2 of the delay circuit 102, as shown in FIG.

As described above, according to the phase correction circuit of the present embodiment, the delay circuits 101 to 101 are set such that the phase of the rising edge of the signal obtained by delaying the input signal IPT falls within the predetermined phase determination period TP. By selecting 105, the delay time of the input signal IPT is adjusted between TD1 and TD5, and the input signal delayed by the selected delay time is used as the output signal OPT. It can be performed in a short time, and the skew between signals having a phase difference can be adjusted.

Further, according to the phase correction circuit of the present embodiment, the desired phase determination period TP based on the reference signal BCK is defined, and the phase of the rising edge of the signal obtained by delaying the input signal IPT is determined by the phase determination period TP. Since the delay time of the input signal is adjusted between TD1 and TD5 by selecting the delay circuits 101 to 105 so as to fall within the range, the input signal delayed by the selected delay time is used as the output signal OPT. Skew correction can be performed automatically and in a short time, and skew between signals having a phase difference can be adjusted.

[Modification of the First Embodiment] In the phase determination circuit 110 of the phase correction circuit shown in FIG.
It is determined whether or not the phase of the rising edge of the output signals DO1 to DO5 of 105 is within the phase determination period TP, and the delay circuit of the input signal IPT is selected by selecting a delay circuit that falls within the phase determination period TP. The input signal adjusted between TD1 and TD5 and delayed by the delay circuit is output signal OP
Although it was set to T, the determination method is not limited to this.

That is, in each sub-phase determination circuit, it is determined whether or not the phase of the falling edge of the output signals DO1 to DO5 of the delay circuits 101 to 105 is within the phase determination period TP. It is also possible to determine whether or not the phases of the rising edge and the falling edge of the output signals DO1 to DO5 of 105 fall within the phase determination period TP, and select a delay circuit that falls within the phase determination period TP. Good.

FIG. 5 is a partial configuration diagram centering on a phase determination circuit 510 of a phase correction circuit according to a modification of the first embodiment. In the present modification, the sub phase determination circuit 511
To 515 are output signals DO1 of the delay circuits 101 to 105.
The phase of the falling edge of DO5 is the phase determination period TP
It is determined whether or not it is inside.

The sub-phase determining circuit 511 includes D-type flip-flops 211 and 212, a latch 213, a NOT gate circuit 214, and a two-input NAND gate circuit 215. The other sub-phase determining circuits 512 to 515 are also provided. The configuration is the same as that of the sub phase determination circuit 511.

For example, in the sub-phase determination circuit 511, the flip-flop 211 samples the output signal DO1 of the corresponding delay circuit 101 with the start timing signal LDCK indicating the start timing of the phase determination period TP. The flip-flop 212 is connected to the corresponding delay circuit 10
1 is sampled with an end timing signal TLCK indicating the end timing of the phase determination period TP.

The two-input NAND gate circuit 215 performs a NAND operation on the output of the flip-flop 211 and the signal obtained by inverting the output of the flip-flop 212 by the NOT gate circuit 214. That is, 2-input NAN
The D gate circuit 215 is connected to the output signal DO of the delay circuit 101.
1 at the start timing of the phase determination period TP.
When the signal is at the “H” level and at the “L” level at the end timing of the phase determination period TP, that is, when the phase of the falling edge falls within the phase determination period TP, the value becomes true. A signal that becomes a value will be output.

The latch 213 latches the output of the two-input NAND gate circuit 215 at the timing of the sampling signal SMP and resets it at the timing of the reset signal RST. Note that the output of the latch 213 is output as a selection signal SL1 which is an output of the sub phase determination circuit 511. The selection signals SL2 to SL5 are similarly output from the other sub-phase determination circuits 512 to 515.

FIG. 6 is a partial configuration diagram centering on the phase determination circuit 610 of the phase correction circuit according to a modification of the first embodiment. In the present modification, the sub phase determination circuit 611
To 615 are output signals DO1 of the delay circuits 101 to 105.
It is determined whether or not the phases of the rising edge and the falling edge of DO5 are within the phase determination period TP.

The sub phase determination circuit 611 includes D-type flip-flops 221 and 222, a latch 223, and an XOR gate circuit 225. The configuration of the other sub phase determination circuits 612 to 615 is the same as that of the sub phase determination circuit 612. This is similar to the circuit 611.

For example, in the sub-phase determination circuit 611, the flip-flop 221 samples the output signal DO1 of the corresponding delay circuit 101 with the start timing signal LDCK. Further, the flip-flop 222 samples the output signal DO1 of the corresponding delay circuit 101 with the end timing signal TLCK.

The XOR gate circuit 225 performs an exclusive OR operation between the output of the flip-flop 221 and the output of the flip-flop 222. That is, the XOR gate circuit 225 determines that the output signal DO1 of the delay circuit 101 has a different potential level at the start timing of the phase determination period TP and the potential level at the end timing of the phase determination period TP, that is, the rising edge or the rising edge. When the phase of the falling edge falls within the phase determination period TP, a signal having a true value is output. Otherwise, a signal having a false value is output.

The latch 223 latches the output of the XOR gate circuit 225 at the timing of the sampling signal SMP and resets it at the timing of the reset signal RST. Note that the output of the latch 223 is output as the selection signal SL1 which is the output of the sub phase determination circuit 611.
The selection signals SL2 to SL5 are similarly output from the other sub phase determination circuits 612 to 615.

[Second Embodiment] FIG. 7 is a block diagram of a phase correction circuit according to a second embodiment of the present invention. The phase correction circuit of the present embodiment is obtained by connecting the phase correction circuit of the first embodiment in two stages in series, and using the output of the first stage phase correction circuit as the input signal of the second stage phase correction circuit. I have.

In FIG. 7, the configuration of the first-stage phase correction circuit is the same as the configuration of the phase correction circuit of the first embodiment (see FIG. 1). The specific configuration of each component is also the same as that shown in the first embodiment and its modifications. Further, the phase determination period TP1 of the first-stage phase correction circuit includes a start timing signal LDCK1 and an end timing signal T.
It is defined by LCK1.

In FIG. 7, the configuration of the second-stage phase correction circuit is the same as the configuration of the phase correction circuit of the first embodiment (see FIG. 1). That is, the second-stage phase correction circuit has, as its main components, five delays that output the input signal (the output signal OPT1 of the first-stage phase correction circuit) delayed by different delay times TD21 to TD25, respectively. Circuits 701 to 705, a phase determination circuit 710 for determining whether or not the phases of the edges of the output signals DO21 to DO25 of the delay circuits 701 to 705 are within the phase determination period TP2; 701-
If it is determined that the phases of the edges of the output signals DO21 to DO25 are within the phase determination period, the output signal of the delay circuit included in the phase determination period is converted to the phase correction circuit of the second stage. Selection circuit 72 for selecting as the output of
0.

Other components include a third variable delay circuit 731 for generating a start timing and an end timing of the phase determination period from the reference signal BCK, and a fourth variable delay circuit 731.
Variable delay circuit 732 and a buffer 74 for driving output signals DO21 to DO25 of delay circuits 701 to 705.
1 to 745, and the output signals LDCK2 and TLCK2 of the third variable delay circuit 731 and the fourth variable delay circuit 732.
Buffers 751 and 752 for driving the
And a buffer 750 for driving the output of the S.20 and outputting the output signal OPT2. The specific configuration of each component is the same as that shown in the first embodiment and its modifications. The phase determination period TP2 of the second-stage phase correction circuit is defined by a start timing signal LDCK2 and an end timing signal TLCK2.

In the phase correction circuit of this embodiment, the phase adjustment period TP2 of the second-stage phase correction circuit is set shorter than the phase adjustment period TP1 of the first-stage phase correction circuit.
The steps of the delay times TD21 to TD25 of the delay circuits 701 to 705 of the second stage phase correction circuit are set smaller than the steps of the delay times TD1 to TD5 of the delay circuits 101 to 105 of the second stage phase correction circuit. .

For example, specific numerical values such as the delay time of the first stage phase correction circuit are shown in the first embodiment, that is, the delay times TD1 to TD5 of the delay circuits 101 to 105.
Is 0.5 [ns] in the range of 2 [ns] to 4 [ns].
The delay time TLD1 of the first variable delay circuit 131 and the delay time TT of the second variable delay circuit 132
Let L1 be TLD1 = 2.75 [ns], TT
L1 is set to 3.25 [ns], and the phase determination period TP1 is set.
= 0.5 [ns]. On the other hand, in the second-stage phase correction circuit, the delay time T
D21 to TD25 are changed from 2.75 [ns] to 3.25.
The delay time TLD2 of the third variable delay circuit 731 and the delay time TTL2 of the fourth variable delay circuit 732 are set at intervals of 0.25 [ns] within the range of [ns].
TTL2 = 2.875 [ns], TTL1 = 3.125
[Ns], and the phase determination period TP2 = 0.25 [n
s].

As described above, the phase adjustment period of the phase correction circuit is set to be shorter and the delay time of the delay circuit is set to be smaller as the phase correction circuit goes to the subsequent stage. Fine skew adjustment can be performed.

[0070]

As described above, according to the phase correction circuit of the present invention, skew correction can be performed automatically and in a short time, and skew between signals having a phase difference can be adjusted. A possible phase correction circuit can be provided.

According to the phase correction circuit of the present invention, for example, at the stage of circuit design, the number of sets of the delay circuit, the sub-phase determination circuit and the selector is arbitrarily set, and the delay time of the delay circuit is determined. If set arbitrarily, the adjustment accuracy and adjustment range of the skew adjustment can be set to the accuracy and range according to the design specification.Moreover, in a plurality of sub-phase determination circuits, the output signals of the corresponding delay circuits can be adjusted. Provided is a phase correction circuit capable of obtaining a final output in the form of averaging a plurality of selector outputs even when it is determined that the phase falls within a phase determination period, and performing highly accurate skew adjustment. be able to.

According to the phase correction circuit of the present invention, the output of the phase correction circuit is connected in series as a plurality of input signals to the next-stage phase correction circuit. By setting the phase adjustment period of the phase correction circuit to be short and the delay time of the delay circuit to be small, it is possible to provide a phase correction circuit capable of performing finer skew adjustment.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a phase correction circuit according to a first embodiment of the present invention.

FIG. 2 is a timing chart illustrating the operation of each component of the phase correction circuit according to the first embodiment.

FIG. 3 is a circuit configuration diagram of a buffer in the phase correction circuit of the first embodiment.

FIG. 4 is a timing chart in the case where the phases of rising edges of output signals of a plurality of delay circuits enter a phase determination period in the phase correction circuit of the first embodiment.

FIG. 5 is a partial configuration diagram (part 1) centering on a phase determination circuit of a phase correction circuit according to a modification of the first embodiment.

FIG. 6 is a partial configuration diagram (part 2) centering on a phase determination circuit of a phase correction circuit according to a modification of the first embodiment.

FIG. 7 is a configuration diagram of a phase correction circuit according to a second embodiment of the present invention.

[Description of Signs] 101 to 105: delay circuit, 110: phase determination circuit, 1
20 ... selection circuit, 131 ... first variable delay circuit, 132
... Second variable delay circuit, 141 to 145, 150, 15
1, 152 buffer, 111-115 sub phase determination circuit, 201 D-type flip-flop (first storage means), 121-125 selector, 130 wiring OR, 202 D-type flip-flop 2), 203... Latch, 204... NOT gate circuit, 2
05: two-input NAND gate circuit, IPT: input signal of the phase correction circuit, BCK: reference signal, OPT: output signal of the phase correction circuit, TD1 to TD5: delay time of the delay circuit,
TLD, TTL: delay time of variable delay circuit, TP: phase determination period, DO1 to DO5: output signal of delay circuit, LD
CK: Start timing signal, TLCK: End timing signal, SMP: Sampling signal, RST: Reset signal, SL1 to SL5: Select signal, HiZ: High impedance terminal, 301: NOT gate circuit, 302: PM
OS transistor, 303 ... NMOS transistor, 3
04, 305: current source, VCC: power supply potential, GND: ground potential, 510: phase determination circuit, 511 to 515: sub phase determination circuit, 211, 212: D-type flip-flop, 213: latch, 214: NOT gate circuit , 21
5 ... 2-input NAND gate circuit, 610 ... Phase determination circuit, 611-615 ... Sub-phase determination circuit, 221,22
2 ... D-type flip-flop, 223 ... latch, 225 ...
XOR gate circuit, 701 to 705... Delay circuit, 710
... Phase determination circuit, 720 ... selection circuit, 731 ... third variable delay circuit, 732 ... fourth variable delay circuit, 741-7
45,750,751,752 ... buffer, TD21-
TD25: delay time of delay circuit, TLD1, TTL2,
TLD3, TTL4 ... delay time of variable delay circuit, TP
1, TP2: phase determination period, DO21 to DO25: output signal of delay circuit, LDCK1, LDCK2 ... start timing signal, TLCK1, TLCK2 ... end timing signal, OPT1 ... output signal of first-stage phase correction circuit, OP
T2: output signal of the second-stage phase correction circuit.

Claims (7)

[Claims] 1. A plurality of delay circuits for delaying input signals by different delay times and outputting the delayed signals, and a phase determination circuit for determining whether or not the phases of the output signals of the plurality of delay circuits are within a predetermined period. And a selection circuit for selecting and outputting the output signal of the delay circuit when the phase determination circuit determines that the phase of the output signal of the delay circuit is within a predetermined period. . 2. The phase determination circuit according to claim 1, further comprising: a sub-phase determination circuit configured to individually determine whether a phase of an output signal of the corresponding delay circuit is within a predetermined period. 2. The phase correction circuit according to claim 1, wherein the phase correction circuit includes a plurality of the plurality of phase correction circuits. 3. The selection circuit outputs an output signal of the delay circuit when the sub-phase determination circuit determines that the phase of the output signal of the corresponding delay circuit is within a predetermined period. 3. The phase according to claim 2, further comprising: a plurality of output selectors for setting an output to a high-impedance state when it is determined that the plurality of output selectors do not enter. Correction circuit. 4. The first sub-phase determination circuit stores first and second output signals of a corresponding delay circuit at a start timing of the predetermined period, and stores an output signal of the corresponding delay circuit at an end timing of the predetermined period. And a second storage means for storing a signal which becomes a true value when the contents of the first storage means and the contents of the second storage means are different, and outputs a false value when they match. The phase correction circuit according to claim 2. 5. The phase correction circuit according to claim 1, wherein the outputs of the plurality of delay circuits have the same drivability for voltage levels representing a true value and a false value, respectively. 6. A first variable delay circuit for delaying a predetermined reference signal by a predetermined time and outputting a start timing signal for defining a start timing of the predetermined period, wherein the first variable delay circuit delays the reference signal by a predetermined time, 2. The phase correction circuit according to claim 1, further comprising: a second variable delay circuit that outputs an end timing signal that defines an end timing of the predetermined period. 7. A phase correction circuit in which the phase correction circuit according to claim 1 is connected in a plurality of stages in series.