JP3351971B2 - Integrated circuit for signal delay - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a delay circuit for adjusting a minute unit time, and more particularly, to an integrated circuit capable of adjusting a delay time to adjust a signal timing. .

[0002]

2. Description of the Related Art Today, various delay circuits are used in order to request timing between a specific signal and another signal. Conventionally, as this delay circuit, one or a plurality of delay elements for transmitting a specific signal for a set delay time have often been incorporated in the line of the specific signal.

In recent years, a circuit as shown in FIG. 6 has been used as a delay circuit capable of adjusting and changing the delay time. The delay circuit 11 has a plurality of delay elements 19 connected in series, and the number of delay elements 19 through which an input signal passes using the selector 23, that is, a delay time can be changed.

That is, as shown in FIG. 6, the 0th input terminal D0 of the selector 23 is connected to the signal input terminal 13, and the first input terminal D1 of the selector 23 is connected to the signal input terminal via the first delay element 19-1. To the signal input terminal 13 via the first delay element 19-1 and the second delay element 19-2, and further to the third input terminal of the selector 23. D3
Are sequentially connected in series so as to be connected to the signal input terminal 13 via the first to third delay elements 19-1 to 19-3. Are connected to the input terminals of the selector 23, respectively. The control terminal S of the selector 23 is connected to the controller 21, and the output terminal Dout of the selector 23 is used as the signal output terminal 15 of the delay circuit 11.

Accordingly, in the delay circuit 11, when a selection signal is input from the control input terminal 17, a switching control signal is output from the controller 21 to the control terminal S of the selector 23 based on the selection signal, and the selector 23 Input terminals D0, D1,
Only specific input terminals of D2,..., Dn are connected to the output terminal of the selector 23. As described above, when the connection between the input terminal and the output terminal of the selector 23 is selected based on the selection signal input to the control input terminal 17, for example, by connecting the 0th input terminal D0 to the output terminal DOUT, this delay Circuit 11
The signal output to the signal output terminal 15 of the
Has a delay time of 0 with respect to the signal input to. The first input terminal D1 of the selector 23 is connected to the output terminal DO of the selector 23.
When connecting to the UT, the signal output to the signal output terminal 15 is delayed by the delay time set by the first delay element 19-1. When the second input terminal D2 of the selector 23 is connected to the output terminal DOUT of the selector 23, the sum of the delay time set by the first delay element 19-1 and the delay time of the second delay element 19-2 is used. The signal delayed only by the signal output terminal 15 is output from the signal output terminal 15, and by selecting the input terminal of the selector 23, the setting of the delay time can be changed so that the timing of the signal output from the signal output terminal 15 is shifted. It is.

Incidentally, in the delay circuit 11 which can change the setting of the delay time by using the delay elements 19 in series as described above, the delay times of the respective delay elements 19 are often set to be the same as much as possible. It is designed to be set in advance.

[0007]

At present, there is a demand for a delay circuit capable of controlling a minute unit time of delay time as a delay circuit whose delay time can be adjusted. In a delay circuit using a gate circuit as a delay element, a minute delay time of 1 nanosecond or less can be set in each delay element.

However, if a plurality of gate circuits each serving as a delay element are connected to one selector, the circuit connection becomes complicated, and the L component and the C component in the connection line between the selector and each gate circuit cause the connection of each gate circuit. The time required for the signal to reach the input terminal of the selector from the output terminal may be problematic. That is, when a minute time of about nanosecond is set as the delay time of each delay element, a connection line between the input side of the delay element and the selector in the X-th delay element among a number of delay elements in series. , The signal propagation time on the connection line between the output side of the delay element and the selector may be relatively short. In other words, a signal reaching the selector from the input side of the delay element may be later than a signal reaching the selector from the output side via the delay element.

For this reason, in a delay circuit in which an input signal is sequentially delayed by a large number of serially arranged delay elements, if the delay time of each delay element is extremely short, this delay element is used for a specific delay element. A reversal phenomenon called a skew in which the passed signal has a shorter delay time than the signal not passing through the delay element has occurred, and it has been extremely difficult to design and manufacture a delay circuit that can change the delay time with a small delay time. .

[0010]

The present invention comprises a plurality of delay gate blocks, each delay gate block having a plurality of delay gate elements in series and outputting an input signal as two output signals. In addition, the delay time of at least one output signal can be adjusted, one output signal of each delay gate block is input to another delay gate block, each delay gate block is connected in series, and the other Is input to a delay selection selector, and the delay selection selector selects any one of the signals output from the respective delay gate blocks and outputs the signal from a signal output terminal.

As described above, in this delay circuit, by selecting a signal to be output to the signal output terminal by the delay selection selector, it is possible to output a signal having a different delay time based on the delay time determined by each delay gate block. it can. Also, each delay gate block outputs two signals,
Since the delay time of at least one output signal can be adjusted, if a reverse time called a skew occurs due to a very short delay time determined by each delay gate block, a delay gate block in the preceding stage that causes the reverse phenomenon The skew can be eliminated by shortening the delay time of the signal output to the delay selection selector or increasing the delay time of the signal output to the next-stage delay gate block.

[0012] Then, the present invention, a plurality of delay gates block obtained by connecting a plurality of delay gate elements in series is provided, each delay gate block, the output of the delay gate element in the final stage in the delay gate block The terminal is connected to the first-stage delay gate element in another delay gate block to make each delay gate block in series, the input terminal of the first-stage delay gate element in the first delay gate block is connected to the signal input terminal, and , Each delay gate block is provided with an adjustment selector, and each input terminal of the adjustment selector is connected to an output terminal of a different delay gate element in the delay gate block, and an output terminal of each adjustment selector is connected to a delay selection selector. And an output terminal of the delay selection selector connected to the signal output terminal. .

As described above, a plurality of delay gate elements are provided in series in the delay gate block, and the delay gate blocks are connected in series. A large number of delayed signals having sequentially different delay times can be formed. Then, since signals from the delay gate blocks in series are sent to the delay selection selector, if any of the signals input to the delay selection selector is selected and output to the signal output terminal, signals having different delay times are output. And a signal delay integrated circuit that can be used. Also, since the delay time in the delay gate block can be adjusted and changed by the adjustment selector provided in each delay gate block and sent to the delay selection selector, the signal reaching the delay selection selector suffers from a reversal phenomenon called skew. If this occurs, the control signal input to the adjustment selector is switched, and the skew can be eliminated by adjusting the delay time of the signal to be sent to the delay selection selector in the delay gate block.

According to the present invention, it is preferable to provide a signal delay integrated circuit in which a multi-bit shift register is provided, and each bit output terminal of the shift register is connected to each control terminal of a different adjustment selector. Thus, if a shift register for storing a control signal for controlling the adjustment selector is provided, a multi-bit signal can be serially input to the shift register, and the number of external terminals of the signal delay integrated circuit can be reduced. can do.

According to the present invention, a plurality of delay gate blocks in which a plurality of delay gate elements are connected in series are formed, and each delay gate block is provided with a correction selector to delay each input terminal of the correction selector. The output terminals of the different delay gate elements in the gate block are connected to the output terminals of the modified selectors, and the output terminals of the modified selectors are connected to the first-stage delay gate elements in the other delay gate blocks, so that each delay gate block is connected in series, and the first-stage delay gate is connected. Connect the input terminal of the first-stage delay gate element in the block to the signal input terminal,
An output terminal of an appropriate delay gate element in each delay gate block may be connected to an input terminal of a delay selection selector, and an output terminal of the delay selection selector may be connected to a signal output terminal to form a signal delay integrated circuit.

As described above, a plurality of delay gate elements are provided in series in the delay gate block, and the delay gate blocks are connected in series. A large number of delayed signals having sequentially different delay times can be formed. Since a correction selector is provided in each delay gate block to adjust the delay time of a signal transmitted to the next-stage delay gate block, the delay of a signal input to the delay selection selector via the next-stage delay gate block is delayed. Time can be adjusted. Therefore, if skew occurs due to the small delay time in each delay gate block, the small delay time is set while eliminating the skew by adjusting the delay time of the signal sent to the next delay gate block. A delay circuit integrated circuit that can be changed can be easily configured.

The present invention is preferably a signal delay integrated circuit having a multi-bit shift register, wherein each bit output terminal of the shift register is connected to each control terminal of a different correction selector. As described above, if the shift register that stores the control signal for controlling the correction selector is provided, it is possible to serially input a multi-bit signal to the shift register, thereby reducing the number of external terminals of the signal delay integrated circuit. be able to.

Further, according to the present invention, a plurality of delay gate blocks in which a plurality of delay gate elements are connected in series are formed, and two selectors are provided in each delay gate block as an adjustment selector and a correction selector. Connect each input terminal of the adjustment selector to the output terminal of a different delay gate element in the delay gate block, and connect each input terminal of the correction selector to the output terminal of a different delay gate element in the delay gate block. By connecting the output terminal of each correction selector to the first-stage delay gate element in another delay gate block, each delay gate block is connected in series, and the input terminal of the first-stage delay gate element in the first-stage delay gate block is signal-input. And the output terminal of each adjustment selector is connected to the input terminal of the delay selection selector. Also be a signal delay integrated circuit connected to force terminal to the signal output terminal.

As described above, a plurality of delay gate elements are provided in series in the delay gate block, and the delay gate blocks are connected in series. A large number of delayed signals having sequentially different delay times can be formed. Then, since signals from the delay gate blocks in series are sent to the delay selection selector, if any of the signals input to the delay selection selector is selected and output to the signal output terminal, signals having different delay times are output. And a signal delay integrated circuit that can be used. Further, since the delay time in the delay gate block can be adjusted and changed by the adjustment selector provided in each delay gate block and sent to the delay selection selector, a signal arriving at the delay selection selector has a reversal phenomenon called skew. If this occurs, the skew is eliminated by switching the control signal input to the adjustment selector to adjust the time for the signal to reach the delay selection selector and further adjusting the delay time of the signal sent to the next-stage delay gate block. In addition, it is possible to easily configure a delay circuit that can change the setting of the minute delay time in units of a fixed time.

It is to be noted that the present invention provides a signal delay integrated circuit having a multi-bit shift register, wherein each bit output terminal of the shift register is connected to each control terminal of a different adjustment selector and correction selector. Is preferred. By providing a shift register that stores a control signal that controls the adjustment selector and a shift register that stores a control signal that controls the correction selector, a multi-bit signal can be serially input to the shift register. Thus, the number of external terminals of the signal delay integrated circuit can be reduced .

[0021]

[0022]

[0023]

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a delay circuit 10 according to the present invention, as shown in FIG.
A plurality of delay gate elements 33 are used as a delay gate block 31 while 33 are connected in series. The delay gate block 31 is provided with a selector to provide an adjustment selector 35, and an output terminal of the adjustment selector 35 is connected to an input terminal of the delay selection selector 25 to provide a delay circuit 10 capable of adjusting a delay time. Things.

The delay circuit 10 is formed as an integrated circuit, and includes a plurality of delay gate elements 33 connected in series.
The input terminal of the first-stage delay gate element 33 is connected to the signal input terminal 13 of the delay circuit 10. Also, a plurality of delay gate elements 33 connected in series constitute a delay gate block 31, and the last-stage delay gate element 33 in each delay gate block 31 is the first-stage delay gate in the next-stage delay gate block 31. The delay gate block 31 is also connected in series with the element 33.

The adjustment selector 35 in each of the delay gate blocks 31 connects the output terminal of a different delay gate element 33 in the delay gate block 31 to the input terminal of the adjustment selector 35. Is connected to the input terminal of the delay selection selector 25. Further, the output terminal of the delay selection selector 25 is connected to the signal output terminal 15 of the delay circuit 10, and the delay selection selector
25 control terminals are connected to the controller 21 and the controller
The input terminal 21 is connected to the control input terminal 17 of the delay circuit 10.

The control terminal of the adjustment selector 35 is connected to the bit output terminal of the shift register serving as the adjustment data storage means 41, and the input terminal of the shift register is connected to the adjustment data input terminal 45. In this embodiment, 256 delay gate blocks 31 are formed, and the delay selection selector 25 selects one of the signals from each delay gate block 31 by using an 8-bit control signal and outputs a signal. Output to terminal 15 is assumed.

Each delay gate block 31 has at least five delay gate elements 33 connected in series, and an adjustment selector 35 has four input terminals connected to different delay gate elements 33 according to a 2-bit adjustment signal. One of the signals is sent to the delay selection selector 25. For this reason, the shift register serving as the adjustment data storage means 41 is a shift register capable of outputting a 512-bit parallel signal as an adjustment signal, and receives a 512-bit adjustment data signal from an adjustment data input terminal 45 and outputs a clock signal. A clock signal is input from the terminal 47 so that the adjustment data signal, which is a serial signal, can be stored in the adjustment data storage unit 41.

As described above, the delay circuit 10 has a plurality of delay gate elements 33 connected in series and delays a signal by the operation delay time of the gate element. Can be extremely short, for example, on the order of several hundred picoseconds. Further, since the delay gate block 31 is configured with a plurality of gate elements in series, 1
An extremely short delay time of, for example, about 1 nanosecond to several nanoseconds can be set per delay gate block 31 to form a delay signal.

Accordingly, when a selection signal is input from the control input terminal 17 and the input terminal connected to the output terminal of the delay selection selector 25 is switched by the control signal from the controller 21, the input signal input from the signal input terminal 13 On the other hand, a signal having a delay due to the delay time set in each delay gate block 31 and a signal having a signal propagation time difference in a connection line from each delay gate block 31 to the delay selection selector 25 are output from the signal output terminal 15. become.

Since the delay circuit 10 has the adjusting selector 35 in each delay gate block 31, the delay gate block 31
, The output timing of the signal output from the delay gate block 31 to the delay selection selector 25 can be adjusted. Therefore, the time required for a specific delay gate block 31 to reach the delay selection selector 25 for a signal output to the delay selection selector 25 is equal to the delay gate block 31 of the next stage.
When a reversal phenomenon called skew occurs which is slower than the time when the delay selector arrives at the delay selection selector 25 via the delay selector block 25, the input of the adjustment selector 35 in the delay gate block 31 which is the preceding stage of the specific delay gate block 31 causing the skew By switching the terminals, the delay time of the signal output to the delay selection selector 25 by the specific delay gate block 31, which is the preceding stage, can be shortened.

Therefore, this particular delay gate block 31
From the delay gate block 31 at the next stage to the delay selection selector 25
This particular delay gate block than the signal input to the
It is possible to adjust so that the signal input from 31 to the delay selection selector 25 is advanced, and skew can be eliminated. Therefore, when designing the delay circuit 10 capable of changing the delay time in minute time units, there is no need to design a circuit that does not completely cause skew, and the design of the signal delay integrated circuit is facilitated.

In the adjustment test of the delay circuit 10 for making such a minute change in the delay time, a delay element 51 and a pulse generator 53 having a fixed delay time and a pulse counter or a frequency measuring device 59 are used. It is. That is, as shown in FIG. 2, one input terminal of the two-input selector 55 is connected to the pulse generator 53, and the other input terminal of the two-input selector 55 is connected to the output terminal of the delay element 51. The output terminal of the two-input selector 55 is connected to the signal input terminal 13 of the delay circuit 10.
, And the signal output terminal 15 of the delay circuit 10 is connected to the input terminal of the delay element 51 and the input terminal of the frequency measuring device 59.

In this manner, a closed circuit is formed by the delay circuit 10 and the delay element 51. As shown in FIG. 3, when the select signal A is at the H level, one H pulse is generated by the pulse generator 53. The input signal B is output. It is to be noted that, when the select signal A is H
When the level is at the level, the input terminal of the two-input selector 55 to which the pulse generator 53 is connected is connected to the output terminal of the two-input selector 55. When the select signal A is at the L level, the two-input selector 55 to which the delay element 51 is connected is connected. Is connected to the output terminal of the two-input selector 55.

The pulse width of the H pulse output from the pulse generator 53 is a time width shorter than the delay time Δt of the delay element 51. The H level time of the select signal A is longer than the sum of the delay time Δx set in the delay circuit 10 and the delay time Δt of the delay element 51, and the pulse generator 53 outputs an H pulse. The timing is immediately before returning the select signal A to the L level.

As described above, when the select signal A is set to the H level, the L level signal from the pulse generator 53 is first input to the delay circuit 10, and the output signal of the delay circuit 10 is reliably set to the L level. After the output signal of 51 is also at L level, the H pulse from the pulse generator 53 is input to the delay circuit 10 and the connection of the input terminal of the delay circuit 10 is switched to the output terminal of the delay element 51 by the two-input selector 55. It is.

Accordingly, the H pulse input to the delay circuit 10 is output from the signal output terminal 15 of the delay circuit 10 with a delay of the delay time Δx of the delay circuit 10 and input to the delay element 51. The H pulse output from the delay circuit 10 is
The signal is again input to the delay circuit 10 with a delay of the delay time Δt of the delay element 51 by the delay element 51. Therefore, the delay circuit
Thereafter, H pulses are output at time intervals equal to the total time of the delay time Δx of the delay element 51, the delay time Δt of the delay circuit 10, and the signal propagation time Δt ′ in the closed circuit. H pulses are generated in the output signal C at regular time intervals.

A limiter is inserted between the two-input selector 55 and the delay circuit 10. When a signal of a certain level or more is input to the limiter, the signal is output as an H level signal of a predetermined voltage, and is output below a certain level. Is preferably input to a limiter to output a predetermined L level signal such as 0 volt. Thus, if a limiter is inserted between the two-input selector 55 and the delay circuit 10, when the H pulse circulates through the closed circuit formed by the delay circuit 10 and the delay element 51, the level of the H pulse decreases, or , The H level other than the H level is prevented from rising, and the H pulse is circulated in a closed circuit, that is, the H state in which the H state is generated at a constant cycle is reliably maintained to form the H pulse at a constant interval. Can be maintained.

Then, the input terminal of the delay selection selector 25 is sequentially switched by a selection signal input from the control input terminal 17 of the delay circuit 10 to change the delay time Δx. As the change of the delay time Δx, for example, the delay time Δx of the delay circuit 10 is sequentially changed from the minimum delay time to the maximum delay time, or from the maximum delay time to the minimum delay time. As described above, when the selection signal is switched so that the delay time of the delay circuit 10 is sequentially increased, for example, the interval of the H pulse output from the delay circuit 10 becomes longer, and the oscillation frequency of the closed circuit becomes lower sequentially.

Therefore, the selection signal input to the control input terminal 17 is switched while the output signal of the delay circuit 10 is confirmed by the frequency measuring device 59, and the oscillation frequency confirmed by the frequency measuring device 59 is increased. It can be easily confirmed that the inversion of the delay time has occurred due to the signal propagation time from the specific delay gate block 31 to the delay selection selector 25 in 10.

Since the delay gate block 31 whose delay time is inverted can be specified by the selection signal at this time, the adjustment data signal is input from the adjustment data input terminal 45, and the delay in which the delay time is inverted is generated. The adjustment selector 35 of the preceding delay gate block 31 in the gate block 31 is switched to shorten the delay time in the delay gate block 31.

Thus, each delay gate block 31
If the delay time is adjusted, the delay selection selector 25 sequentially switches the delay gate blocks 31, whereby the delay circuit 10 can surely increase or decrease the delay time sequentially. The measurement of the oscillation frequency of the closed circuit is not limited to the case where the frequency measuring device 59 is used, but the pulse interval can also be obtained by measuring the time during which a required number of pulses are output from the delay circuit 10 using a pulse counter.

Further, the delay time by the delay gate block 31 of each stage can be obtained based on the change of the frequency.
When the signal propagation time difference in the connection line from each delay gate block 31 to the delay selection selector 25 is small, the adjustment signal input from the adjustment data storage unit 41 to the adjustment selector 35 is changed, and the delay time at substantially equal intervals is set. You can also.

In the case where the skew is eliminated and the delay time is changed by the selection signal, the adjustment data for changing the delay time with a delay time having the same time difference is provided outside the signal delay integrated circuit. If you want to memorize,
The adjustment data storage means 41, which is a shift register incorporated in the delay circuit 10, may be held in the adjustment data storage means 41 by not configuring a clear reset.

As another embodiment of the delay circuit 10, as shown in FIG. 4, a plurality of delay gate elements 33 are provided.
And a plurality of delay gate elements 33 are used as a delay gate block 31, and a selector as a correction selector 37 is provided.
31 is connected in series. In the delay gate block 31 of the delay circuit 10, a plurality of delay gate elements 33 are connected in series.For example, the output terminal of the first-stage delay gate element 33 is connected to the next-stage delay gate element 33, and the delay selection is performed. It is connected to the input terminal of the selector 25.

The input terminal of the correction selector 37 in the delay gate block 31 is the output terminal of the delay gate element 33 at the last stage of each delay gate element 33 connected in series in the delay gate block 31, and This is connected to the output terminal of the delay gate element 33 in the preceding stage. The output terminal of the modified selector 37 is connected to the first-stage delay gate element 33 in the other delay gate block 31, so that the delay gate block 31 is connected in series.

The connection between the delay selection selector 25 and each delay gate block 31 is limited to the connection between the output terminal of the first stage delay gate element 33 in the delay gate block 31 and the delay selection selector 25. is not. Then, a shift register as the correction data storage means 43 is provided, a bit output terminal of the shift register is connected to a control terminal of the correction selector 37, and an input terminal of the shift register is connected to the correction data input terminal 46.

The serial data input terminal of the shift register serving as the correction data storage means 43 is a correction data input terminal.
46, and the clock terminal of the shift register is connected to the clock input terminal 48. As described above, the delay circuit 10 includes a plurality of serially-connected delay gate elements.
Delay gate block by 33 and one correction selector 37
The delay gate block 31 is formed by inputting the output of the correction selector 37 to the delay gate block 31 of the next stage.
Are serialized, so that the correction signal to the correction selector 37 output from the correction data storage means 43 allows the delay time when transmitting the input signal to the next-stage delay gate block 31 via the specific delay gate block 31 to be increased. Correction can be changed.

Therefore, in the delay circuit 10, the signal from the delay gate element 33 in the preceding stage as much as possible in the delay gate block 31 is transmitted to the delay gate block 31 in the next stage by each correction selector 37 in each delay gate block 31. When the signal from each delay gate block 31 is selected by the delay selection selector 25 and the signal is output from the signal output terminal 15, the signal from the delay gate block 31 in the subsequent stage is output from the delay gate block 31 in the previous stage. When the delay time is shorter than that of the signal, the input terminal of the correction selector 37 is switched by changing the input terminal of the correction selector 37 so as to increase the delay time of the signal transmitted from the preceding delay gate block 31 to the next delay gate block 31. It is possible to eliminate the reversal of the delay time.

In still another embodiment, as shown in FIG. 5, a delay gate block 31 is formed by connecting a plurality of delay gate elements 33 in series, and a required number of delay gates are sequentially arranged from the preceding stage. The output terminal of the element 33 is connected to the input terminal of the adjustment selector 35, and the output terminals of the required number of delay gate elements 33 in the final stage and the appropriate stage from the final stage are connected to the input terminals of the correction selector 37. .

The connection of the output terminal of the adjustment selector 35 to the input terminal of the delay selection selector 25 and the provision of the adjustment data storage means 41 are the same as those of the delay circuit 10 shown in FIG. Further, the output terminal of the correction selector 37 is connected to the delay gate block 31 of the next stage so that each delay gate block 31 is connected in series.
Is similar to that of the delay circuit 10 shown in FIG.

Therefore, in this embodiment, the delay time in each delay gate block 31 in the signal output from each delay gate block 31 to the delay selection selector 25 can be adjusted, and the input signal from the signal input terminal 13 can be adjusted. Selector 35 for adjusting the time until the data is transmitted to the delay selection selector 25.
Can be adjusted by controlling. Further, the time required for transmitting a signal input from each delay gate block 31 to the next-stage delay gate block 31 can also be adjusted by controlling the correction selector 37.

Therefore, it is possible to easily set the delay time at equal intervals by the time difference at which the input signal input from the signal input terminal 13 reaches the delay selection selector 25 via each delay gate block 31. The delay circuit shown in FIG.
In 10, the input terminal of the shift register as the adjustment data storage means 41 is connected to the adjustment data input terminal 45, and the input terminal of the shift register as the correction data storage means 43 is connected to the correction data input terminal 46. Correction data storage means 43
Connect the input terminal of the adjustment data storage means 41 to the serial output terminal, or read the data of the adjustment data storage means 41 as a correction data storage means 43 as a latch circuit,
The adjustment data signal and the correction data signal may be serially input from the adjustment data input terminal.

Further, the adjustment data storage means 41 and the correction data storage means 43 may be omitted, and the adjustment selector 35 and the correction selector 37 may be controlled by externally inputting the adjustment data signal and the correction data signal in parallel. However, if the number of delay gate elements 33 is large and the number of adjustment signals and correction signals increases, the adjustment data storage means 41 and correction data storage means 43 are provided, and the adjustment data signals forming the adjustment signals are serialized. And the correction data signal forming the correction signal is input serially, the number of external terminals of the integrated circuit can be reduced, and the handling of the connection of the integrated circuit can be facilitated.

Further, the delay circuit 10 shown in FIGS. 1, 4 and 5 forms 256 delay gate blocks 31 and 8
Although the delay selection selector 25 is controlled by a bit control signal, the number of the delay gate blocks 31 is 25
The number is not limited to six, and may be several tens.
Also, the number of delay gate elements 33 in the delay gate block 31 is not limited to 5 or 6, but may be about 2 or 3, or about 10 in some cases.

Further, in the delay circuit 10 shown in the drawing, all the delay gate blocks 31 have the same structure, and the last-stage delay gate block 31 has the same structure as the other delay gate blocks 31. The design is easy. However, since the final stage delay gate block 31 includes the delay gate element 33 not used for signal transmission, the final stage delay gate block 31 omits the unused delay gate element 33 and the modified selector 37. It may be a gate block.

[0057]

【The invention's effect】

According to a first aspect of the present invention, there are provided a plurality of delay gate blocks in which a plurality of delay gate elements are connected in series, and each delay gate block is a final stage delay gate in the delay gate block. The element is connected to the first-stage delay gate element in another delay gate block to make the delay gate block in series, the input terminal of the first-stage delay gate element in the first-stage delay block is connected to the signal input terminal, and The delay gate block has a selector for adjustment whose input terminal is connected to the output terminal of a different delay gate element in the delay gate block, and the output terminal of each adjustment selector is connected to the input terminal of the delay selection selector. The output terminal of the delay selection selector is a signal delay integrated circuit connected to the signal output terminal.

Therefore, it is possible to adjust the delay time in each delay gate block of the signal output from each delay gate block to the delay selection selector. For this reason, the delay time until a signal reaches the delay selection selector via each delay gate block is adjusted for each delay gate block, and a signal delay integration capable of minutely changing the delay time without generating skew. The circuit can be easily designed and manufactured.

According to a second aspect of the present invention, a multi-bit shift register is provided as adjustment data storage means, and each bit output terminal of the shift register is connected to a control terminal of a different adjustment selector. It is an integrated circuit. Therefore, control signal data for controlling the adjustment selector can be stored in the shift register. Therefore, the control data of the adjustment selector can be input as a serial signal, and the number of external terminals of the signal delay integrated circuit can be reduced, so that the handling of the signal delay integrated circuit can be facilitated.

Further, the invention according to claim 3 has a plurality of delay gate blocks in which a plurality of delay gate elements are connected in series, and each delay gate block has an input terminal different from that in the delay gate block. A modified selector connected to the output terminal of the delay gate element, the output terminal of the modified selector being connected to the first-stage delay gate element in another delay gate block, the delay gate block being connected in series, and the first-stage delay block , The input terminal of the first-stage delay gate element is connected to the signal input terminal, and the output terminal of the first-stage delay gate element in each delay gate block is connected to the input terminal of the delay selection selector, and the output terminal of the delay selection selector is connected. Is an integrated circuit for signal delay connected to the signal output terminal.

Accordingly, it is possible to adjust the delay time in each delay gate block of the signal output from each delay gate block to the next delay gate block. For this reason, the delay time until the signal reaches the next-stage delay gate block via each delay gate block is adjusted for each delay gate block, so that the delay time can be changed without causing skew. An integrated circuit can be easily designed and manufactured.

The invention according to claim 4 has a multi-bit shift register as correction data storage means,
Each bit output terminal of the shift register is a signal delay integrated circuit connected to a control terminal of a different correction selector. Therefore, control signal data for controlling the correction selector can be stored in the shift register.
Therefore, the control data of the correction selector can be input as a serial signal, and the number of external terminals of the signal delay integrated circuit can be reduced, so that the handling of the signal delay integrated circuit can be facilitated.

The invention according to claim 5 has a plurality of delay gate blocks in which a plurality of delay gate elements are connected in series, and each delay gate block includes two selectors for adjusting and correcting. Have it as a selector,
Each input terminal of the adjustment selector is connected to an output terminal of a different delay gate element in the delay gate block, and each input terminal of the correction selector is connected to an output terminal of a different delay gate element in the delay gate block. The output terminal of each correction selector is connected to the first-stage delay gate element in the other delay gate block to make the delay gate block in series, and the input terminal of the first-stage delay gate element in the first delay block is used as a signal input terminal. The output terminals of the adjustment selectors are connected to the input terminals of the delay selection selectors, and the output terminals of the delay selection selectors are signal integrated circuits connected to the signal output terminals.

Therefore, it is possible to adjust the delay time in each delay gate block of the signal output from each delay gate block to the delay selection selector. Therefore, the delay time until the signal reaches the delay selection selector via each delay gate block is adjusted for each delay gate block, and the signal reaches the next delay gate block via each delay gate block. It is possible to easily design and manufacture a signal delay integrated circuit in which the delay time until the delay is adjusted for each delay gate block and the delay time can be minutely changed to a constant change time without causing skew. it can.

The invention according to claim 6 has a multi-bit shift register as adjustment data storage means and correction data storage means, and each bit output terminal of the shift register has a different adjustment selector and correction selector. This is a signal delay integrated circuit connected to each control terminal. Therefore, the data of the control signal for controlling the adjustment selector can be stored in the shift register, and the data of the control signal for controlling the correction selector can also be stored in the shift register. Therefore, the control data of the adjustment selector and the correction selector can be input as a serial signal, and the number of external terminals of the signal delay integrated circuit can be reduced, so that the handling of the signal delay integrated circuit can be facilitated.

[0067]

[0068]

[0069]

[Brief description of the drawings]

FIG. 1 is a diagram showing a first embodiment of a delay circuit according to the present invention.

FIG. 2 is a circuit configuration diagram for measuring a delay time according to the present invention.

FIG. 3 is a time chart in the delay time measuring method according to the present invention.

FIG. 4 is a diagram showing another embodiment of the delay circuit according to the present invention.

FIG. 5 is a diagram showing another embodiment of the delay circuit according to the present invention.

FIG. 6 is a diagram illustrating an example of a conventional delay circuit.

[Explanation of symbols]

10, 11 delay circuit 13 signal input terminal 15 signal output terminal 17 control input terminal 19 delay element 21 controller 23 selector 25 delay selection selector 31 delay gate block 33 delay gate element 35 adjustment selector 37 correction selector 41 adjustment data storage means 43 Correction data storage means 45 Adjustment data input terminal 46 Correction data input terminal 47, 48 Clock input terminal 51 Delay element 53 Pulse generator 55 2-input selector 59 Frequency measuring device

──────────────────────────────────────────────────の Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H01L 21/82 H03H 11/26 H03K 5/14 H01L 27/04

Claims (6)

(57) [Claims] 1. A plurality of delay gate elements are connected in series.
Each of the delay gate blocks has a plurality of
Output terminal of the last delay gate element in the block
Is the first stage delay gate in another delay gate block
Connect the delay gate block in series with the element
First stage delay gate device in a delay gate block
Input terminals are connected to the signal input terminals,
Each block has a selector for adjustment.
Each input terminal of the selector is different in the delay gate block
Connected to the output terminal of the delay gate element,
Connected to the input terminal of the delay selection selector.
Output terminal of the delay selection selector is connected to the signal output terminal
An integrated circuit for signal delay, comprising: 2. A multiple-bit shift register adjustment Day
Each bit output of the shift register
The terminal is the adjustment selector in each delay gate block.
2. The method according to claim 1, wherein the control terminal is connected to a control terminal.
The integrated circuit for signal delay as described . 3. A plurality of delay gate elements are connected in series.
Each of the delay gate blocks has a plurality of
The block has a selector for modification, and this modification selector
Input terminals of the delay gate block have different delay gates.
Connected to the output terminal of the correction element
Child is the first stage delay gate in another delay gate block.
The delay gate block is connected in series with the
Input of the first-stage delay gate element in the first-stage delay block
Input terminal is connected to the signal input terminal, and each delay gate block
Output terminal of one of the delay gate elements
Connected to input terminal of selection selector, delay selection selector
The output terminal is connected to the signal output terminal
Signal delay for the integrated circuit to be. 4. A multi-bit shift register having a modified data
Each bit output of the shift register
The terminal controls the correction selector in each delay gate block.
4. The terminal according to claim 3, wherein the terminal is connected to a control terminal.
Placing the signal delay integrated circuits. 5. A plurality of delay gate elements are connected in series.
Each of the delay gate blocks has a plurality of
The block consists of two selectors, one for adjustment and one for correction.
And each input terminal of the adjustment selector is delayed
Output terminals of different delay gate elements in the gate block
And each input terminal of the correction selector
Connected to the output terminals of different delay gate elements in the
The output terminal of each correction selector is connected to another delay gate
Connected to the first-stage delay gate element in the lock
Extension gate blocks in series, and
The input terminal of the first-stage delay gate element is a signal input terminal.
And the output terminal of each adjustment selector is
Connected to the input terminal of the delay selector
A terminal is connected to a signal output terminal . The integrated circuit for signal delay. 6. A shift register having a multi-bit shift register.
Shift register has different bit output terminals.
Connected to each control terminal of the selector and correction selector
The signal delay integrated circuit according to claim 5, wherein: