JPS62122492A - Video signal processing circuit - Google Patents

Abstract

PURPOSE:To contrive to attain the coincidence of sequential line signals and to improve the S/N with a small-sized circuit by providing a one-H delaying circuit to delay the output of the one-H delaying circuit of a coincidence circuit for another one H, and adding the output of said circuit with an input signal by an adder circuit. CONSTITUTION:The sequential line signals i.e. color-difference signals R-Y and that B-Y are inputted to one terminal of the adder circuit 8 from an input terminal 1 alternately for each one-H period. The output of the circuit 8 goes through the first one-H delaying circuit 2 and the second one-H delaying circuit 9, and comes to be the signal having two-H delay signal and inputted to the other terminal of the circuit 8. Accordingly, the color difference signals R-Y and B-Y do not mix each other in the output of the circuit 8. And the signals R-Y and B-Y alternately form a cyclic filter to attain the improvement of S/N. Also, by switching changeover switches 3 and 4, a color difference signal R-Y which is made coincident is obtained from the first output terminal 5, and one B-Y that is coincident is obtained from the second output terminal 6.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is based on a video signal processing circuit used in a video camera, etc., and particularly in a line sequential signal synchronization circuit. It's about improvement.

[Conventional technology]

FIG. 2 is a circuit diagram showing a conventionally widely used line sequential signal synchronization circuit, and FIG. 3 is a signal waveform diagram for explaining its operation.

In FIG. 2, (1) is an input terminal for a line 11th order signal, and (2) is one horizontal scanning period (hereinafter abbreviated as "1H").

) Delay circuit, (3) and (4) are changeover switches, (5)
and (6) are the first and second output terminals, respectively.

As shown in FIG. 3(a), color difference signals RY and BY are alternately input to the input terminal (1) for each LH. The selector switch (3) is switched between the selector terminals (3a) and (3b), and the selector switch (4) is switched between the selector terminals (4a) and (3b).
4b), and FIG. 3(1)) shows the waveform of the switching signal. When this signal goes to the high level C'H"), the terminals (3a) and (4a) side, and the low level C"L'')
, it is switched to the terminals (3b) and (4b). Therefore, if the timing relationship between the color difference signals R-Y and B-Y and the switching signal is as shown in FIGS. 3(a) and (b), the third output terminal (5) Figure (0)
A color difference signal R-Y as shown in K is sent to the second output terminal (6).
In this case, color difference signals B-Y as shown in Fig. 3(d) K are output and synchronized.
This is a circuit diagram showing an example of a conventional circuit for improving the S/N ratio of the signals shown in Figure 3), etc., where (7) is the input terminal of the synchronized signal, (8) is the addition circuit, (9) is a 1H delay circuit, and Ql is an output terminal.

The signal input to the input terminal (7) is a synchronized signal, so there is a correlation between lines, and the 1H delay circuit (9)
By adding the signals delayed by 1H at the adder circuit (8), the S/N ratio is improved and the output terminal α1
Output to.

[Problem that the invention seeks to solve]

In these conventional circuit systems, in order to achieve the two purposes mentioned above, that is, to synchronize line sequential signals and improve the S/N ratio, it is necessary to use two of the circuits shown in FIG. 4 for the synchronized signals. The circuit of FIG. 4 must be implemented using quadrature modulated nine-color signals. In this case, if the synchronization circuit is included, there will be three 1H delay circuits, and in the latter case, a 1H delay circuit for high frequency will be required, resulting in an increase in circuit scale.The present invention was made to solve the above drawbacks. The purpose of this method is to obtain a video signal processing circuit that can simultaneously synchronize line-sequential signals and improve the S/N ratio using a small circuit. In the video signal processing circuit according to the invention, an adder circuit is provided in the input circuit of the conventional line sequential signal synchronization circuit, and an LH delay circuit is provided to delay the output of the 1H delay circuit of the synchronization circuit by an additional K1H. The output is added to the input signal by the adder circuit.

[Effect]

By doing this, the line sequential signals are added with a delay of 2H in the adding circuit, so it is possible to improve the S/N ratio, and it is possible to improve the S/N ratio at the same time as the original signal synchronization. Embodiment] FIG. 1 is a circuit diagram of an embodiment of the present invention, in which the same reference numerals as in the conventional example shown in FIGS. 2 and 4 indicate equivalent parts.

A line sequential signal as shown in FIG. 3(a) is input to the input terminal (1). That is, the color difference signals RY and B
-Y is input alternately every 1H. The input signal is input to one terminal of the adder circuit (8).

The output of the adder circuit (8) passes through the first 1H delay circuit (2) and the second 1H delay circuit (9), becomes a signal shifted by 2H, and is input to the other terminal of the adder circuit (8). Therefore, in the output of the adder circuit (8), the color difference signals R-Y and B-Y are not mixed together, and the color difference signals Q, -Y and B-Y alternately form a cyclic filter and S/ ) T ratio can be achieved.

As mentioned above, at the output of the adder circuit <8), the color difference signal R-
Since Y and B-Y are not mixed and are in the linear form (line) F, it is the same as the conventional example in Fig. 2. By turning the selector switches (3) and (4) at the timing shown in Fig. 3524 (b), the output from the first output terminal (5) is as shown in Fig. 3 (0). A synchronized color difference signal RY is obtained, and a synchronized color difference signal B- is output from the second output terminal (6) as shown in FIG. 3(d)K.
0 where Y is obtained Although the color difference signals R-Y and B-YiC have been described above, the present invention can also be applied to color signals R, B, and the like.

〔Effect of the invention〕

As described above, in the present invention, with a simple circuit configuration, it is possible to simultaneously synchronize line sequential signals and improve the S/N ratio.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of a conventional line sequential signal synchronization circuit.
4 is a circuit diagram of a conventional 87N ratio improvement circuit. In the figure, (1) is an input terminal, (2) is a first 1H delay circuit, (3), (4) ) is a changeover switch, (5) is a first output terminal, (6) is a second output terminal, (8) is an addition circuit, and (9) is a second 1H delay circuit. °In addition, the same reference numerals in the figures indicate the same or equivalent parts. 0 Figure 1 Figure 2 Figure 4 Figure 3

Claims (1)

[Claims] (1) An addition (or subtraction) circuit in which a line sequential signal of two signals is input to one input terminal, and the output of this addition (or subtraction) circuit is input for one horizontal period (hereinafter referred to as "1H").
It is abbreviated as. ) a first 1H delay circuit that delays the output, a second 1H delay circuit that receives the output of the first 1H delay circuit, delays it further by 1H, and supplies it to the other input terminal of the addition (or subtraction) circuit; A changeover switch is provided for switching and outputting the input signal and output signal of the first 1H delay circuit to a first output terminal and a second output terminal, respectively, or to a second output terminal and a first output terminal, respectively, every 1H. video signal processing circuit.