JPH04227189A - Color signal demodulating data selector - Google Patents

Abstract

PURPOSE: To increase the signal processing speed of a data selector which can digitally demodulate the I signals and Q signals of NTSC type carrier chrominance signals and, at the same time, to reduce the size and cost of the selector. CONSTITUTION: The I and Q components of carrier chrominance signals are sampled by driving a plurality of buffers so that a phase difference of 90 deg. can be obtained between each buffer by utilizing a reference clock having a frequency which is four times as high as a carrier frequency by utilizing such a fact that the I and Q components have a phase difference of 90 deg. between them. The outputs of the buffers are outputted in the I and Q signals through latches alternately driven at a frequency which is twice as high as the carrier frequency. Therefore, the size and cost of a chrominance signal demodulator can be reduced easily, because the data processing speed of the demodulator can be increased and the constitution of the demodulator can be simplified.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data selector for demodulating color signals, and more particularly to a data selector capable of digitally demodulating a carrier color signal in an NTSC TV system.

0002

2. Description of the Related Art In an NTSC TV system, an image signal is separated into a luminance signal Y and a color signal, that is, an I signal indicating hue and a Q signal indicating saturation, and these two color signals I and Q are divided into 3. It is modulated with a 58 MHz carrier wave to form a carrier color signal. This carrier color signal is mixed with the luminance signal Y, sent out by the receiver, separated again from the luminance signal Y by the receiver, and then separated and demodulated into the I signal and Q signal.

0003

In forming such a carrier color signal, the I signal and the Q signal are respectively modulated by an I carrier wave (ICW) and a Q carrier wave (QCW) having a phase difference of 90 degrees. Therefore, in the conventional receiver, I,
Separation of the Q signal is normally performed by applying a synchronous signal to the carrier color signal, respectively, an I carrier wave (ICW) and a Q carrier wave (QCW), using a so-called synchronous detection method. In order to perform such synchronous detection digitally, two digital multipliers are used to add carrier waves (ICW, QCW) corresponding to each of the I and Q signals. This method not only slows down the signal processing speed and increases the size of the circuit, but also increases the overall cost.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned conventional problems and provide a data selector as a color signal demodulating device that has a high signal processing speed and can be made smaller and lower in cost.

[0005]

[Means for Solving the Problems] In order to achieve the above-mentioned object, a data selector according to the present invention digitally converts a carrier color signal including an I signal and a Q signal modulated by carrier waves having a phase difference of 90 degrees. In the demodulator for separating,
9 for each of the carrier waves in response to the carrier color signal.
A plurality of buffers that buffer and output with a phase difference of 0 degrees, a plurality of latches that alternately output the outputs of the buffers at twice the frequency of the carrier wave, and a pulse generator that provides drive signals for the buffers and latches. It is characterized by being configured with the following.

[0006]

With such a configuration, the present invention can provide a color signal demodulation device with a simple circuit configuration, high processing speed, and easy integration. As a result, the data selector for demodulating color signals according to the present invention can be widely applied to the field of digital processing of image signals, such as digital TVs, VTRs, video telephones, and video conference systems.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The principles and preferred embodiments of the present invention will be explained in detail below with reference to the drawings.

The basic principle of the present invention is that the carrier frequency is 3.5.
This method utilizes the fact that the I and Q signals in the carrier color signal modulated at 8 MHz have a phase difference of 90 degrees. This carrier frequency is the synchronous frequency fSC in reproducing the transmission signal.
Since the carrier color signal is input at 4fSC, that is, 1
By sampling at 4.32 MHz, it is possible to separate the I signal component and Q signal component having a mutual phase difference of 90°.

To explain this in more detail, if the period of the carrier wave, that is, the period of the synchronization signal is TSC, then TS
C=1/fSC=0.28μsec, but in the carrier color signal, the Q component is 1/4・TSC= than the I signal component.
Since the signal is transmitted with a phase delay of about 0.07 μsec, the two signals can be separated by sampling the carrier color signal using a reference clock that is 1/4 TSC.

In FIG. 1, the digital carrier color signals subjected to A/C conversion and luminance component separation are separated by 4f so that they have a phase difference of 90°, that is, a driving time difference of 1/4·TSC.
Two 3 clocks driven alternately by the SC reference clock
The signal is input to the state buffering means, separated into an I signal component and a Q signal component, and output. The separated output signal is applied to a digital filter (not shown) and filtered. Here, the three-state buffering means buffers the input and outputs it only when the control clock is applied, and the reference clock has a phase difference of 90 degrees with respect to the carrier frequency, that is, the synchronization frequency fSC. is desirable.

FIG. 2 is a block diagram of a data selector applying the principle illustrated in FIG. In the drawing, there are four buffers 10, 11, 12, 13, each of which is a 3-state buffer.
latches 30, 31, 40, and 41 are connected to their respective output terminals upon receiving the A/D converted carrier color signal. Two latch outputs are connected to each of the I and Q outputs. On the other hand, a pulse generator 100 that provides drive timing pulses is connected to the control terminals of this buffer and latch. The pulse generator 100 receives 4fSC (4fSC) supplied from a reference clock generator (not shown).
Each buffer 1 receives a reference clock of 1/4・TSC).
Drive signals D, E, F, and G are supplied to each latch 30, 3 with a time difference of 1/4 TSC to 0, 11, 12, and 13.
Drive signal B is supplied to signals 1, 40, and 41 at a cycle of 1/2·TSC.

[0012] As a result, each buffer 10, 11, 12,
13 have durations (d
(3) A drive signal of 1/4·TSC is supplied with a period of TSC. On the other hand, the drive signal B is supplied to the latches 30 and 40 at a period of 1/2·TSC, and the latches 31 and
41 is supplied with a drive signal C=B which is an inverted drive signal of drive signal B, that is, a drive signal C=B having a phase delay of 180°.

The operation of the circuit illustrated in FIG. 2 will now be described with reference to FIG.

3.58MH with a mutual phase difference of 90°
The carrier color signal, which is a mixture of the I signal and Q signal modulated by the carrier wave of z(fSC), is A/
D-converted and input. On the other hand, an oscillation circuit (not shown) generates a reference clock of 4 fSC, and a reference pulse as shown in FIG. 3A is input to the pulse generating section 100.

[0015] As a result, the pulse generating section 100 is configured as shown in FIG.
~ Generate a drive signal as shown in FIG. 3G and drive each buffer 10.
-Open in the order of 12-11-13. This results in
The 2-bit signals of the I component are sampled from the buffers 10 and 11 in their respective orders.

On the other hand, the pulse generator 100 has a latch 30
, 31, 40, and 41, each latch is opened at intervals of 1/4 TSC in the order of 30-40-31-41, and each latch is opened at intervals of 1/2 TSC.
- Make it latched by the duration of TSC. As a result, the outputs of the buffers 10 and 11 are outputted through the latches 30 and 31 and added at the contacts to form an I signal component, and the outputs of the buffers 12 and 13 are outputted through the latches 40 and 31.
Q is output through 41 and added at the contact point.
form a signal component. The I and Q signals separated in this manner are inputted to subsequent circuits such as digital filters (not shown) and subjected to processing such as detection, thereby digitally separating the I and Q signals.

Another embodiment, shown in FIG. 4, is specifically for processing 8-bit input signals. This embodiment uses eight three-state buffers 10A, 10B, 11A, 11
B, 12A, 12B, 13A, 13B and 4 latches 3
It is composed of 0A, 30B, 40A, and 40B. The pulse generator also includes a counter 50 that receives a 4fSC reference clock and generates a 2fSC output, and a drive signal (respectively) having a phase difference of 90 degrees with respect to a 3.58 MHz carrier wave upon receiving the output of this counter 50. Figure 3
D to FIG. 3G).

In particular, in the embodiment of FIG.
, 11B and the latch 30B, and the buffers 21A, 21
Adders 20A and 20 are installed between B and latch 40B, respectively.
B, 21A, and 21B are connected. This adder is provided to match the counting characteristics of a digital filter (not shown) connected to a circuit subsequent to the circuit of the present invention. This is the complement (co) of the negative (-) region of the signal applied due to the phase difference.
This constitutes a complement circuit for performing the conversion function, and the I and Q signals having positive (+) components are
They are output through latches 30A and 40A, respectively, and the negative (
-), the I and Q signals having components of
A, 20B) and (21A, 21B) are subjected to complement conversion and outputted through latches 30B and 40B. Other operations are the same as those in the embodiment shown in FIG. 2, so redundant explanation will be omitted.

[0019]

[Effects of the Invention] As described above, according to the present invention, the circuit is simpler than the conventional synchronous detection method using multipliers, so the data processing speed is fast, and a small and inexpensive data selector can be used. can be provided. This results in N
The present invention can be widely used in color demodulation devices for TSC image signals.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle of a data selector according to the present invention.

FIG. 2 is a circuit diagram of an embodiment according to the present invention.

FIG. 3 is a timing chart showing the operation of the device shown in FIG. 2;

FIG. 4 is a circuit diagram showing another embodiment according to the present invention.

[Explanation of symbols]

11, 12, 13, 14 (3 states) buffer 30,
31, 40, 41 Latch 50 Counter 60 Decoder 100 Pulse generator

Claims (4)

[Claims] 1. A demodulation device that digitally separates a carrier color signal including an I signal and a Q signal modulated by carrier waves having a phase difference of 90° from each other, which receives the carrier color signal and separates the carrier color signal from the carrier wave. a plurality of buffers each buffering and outputting with a phase difference of 90°, a plurality of latches alternately outputting the outputs of the buffers at twice the frequency of the carrier wave, and a pulse generator providing drive signals for the buffers and latches. 1. A data selector for demodulating a color signal, comprising: a data selector for demodulating a color signal; 2. The data selector according to claim 1, wherein a complement circuit for performing complement conversion of output data is connected to some of the plurality of buffers. 3. The pulse generator receives a reference clock having a frequency four times as high as the carrier wave frequency, and supplies drive signals having a phase difference of 90° to the plurality of buffers, respectively, and provides a drive signal having a phase difference of 90° to the plurality of latches. 2. The data selector according to claim 1, wherein the data selector supplies drive signals having a phase difference of . 4. The data selector of claim 1, wherein each of the buffers is a three-state buffer driven by the drive signal.