KR19980050932A - Low Speed Data Frame Phase Aligner - Google Patents

Abstract

1. TECHNICAL FIELD OF THE INVENTION

Frame phase aligner that allows frame phase alignment at low speeds.

2. The technical problem to be solved by the invention

It lowers the frequency of the control signals (EN, RD) input to the phase aligner and serial converter, prevents glitches, and synchronizes the phase shifting and the serial conversion process where the signal is restored to the reference clock (CKr). .

3. Summary of Solution to Invention

Johnson counters 4 and 5, which can generate relatively low frequency address signals, are used, and instead of using the address signals of counters 4 and 5 directly, a low frequency of 1 bit without glitches is used. By using the synchronous phase aligners 8 and 9 and the serial converters 12 and 13 using control signals, a separate data reproduction process is unnecessary.

4. Important uses of the invention

Applied to phase aligners in exchanges or repeaters.

Description

Slow Data Frame Phase Aligner

The present invention aligns the frame phase of the received data with the frame phase of the reference frame signal at a low speed, and requires a separate data reproduction process by using a parallel / serial (Paralle1-to-Serial: P / S) converter which is a synchronous multiplexer. Data frame phase aligner.

The present invention relates to digital signal processing for phase-aligning a received data frame phase on an input link with a frame phase of a reference frame signal in a communication system such as an exchange or a repeater.

In a conventional data frame phase aligner, a shifter register (S / P converter) is used to convert received data Di and a reference frame signal (FPr) in parallel, and then uses an address of a binary counter. By delaying the parallel signals of the received frames to the frame phase (Fr) of the reference frame signal (FPr) and multiplexing them using an asynchronous multiplexer, the frame phase of the received data is aligned with the frame phase of the reference frame signal. I use it.

In this manner, inevitably, due to skew of the high frequency address signal of the binary counter connected to the asynchronous multiplexer, jitter occurs in the output signal of the restored multiplexer, thus requiring an additional data reproduction process.

In the present invention, to solve the above problems without using a separate regenerator, to lower the frequency of the control signal (EN, RD) input to the phase aligner and the serial converter and to prevent the glitches (Glitch) occurs The aim is to provide a frame phase aligner that ensures that the phase alignment and the serial conversion of the signal is synchronized to the reference clock (CKr).

1 is an input / output signal relationship diagram of a frame phase aligner;

2 is an input / output timing diagram of a frame phase aligner;

3 is a detailed configuration diagram of a frame phase aligner;

4 is an n / 2-bit Johnson counter input and output timing (n = 8).

5 is a timing diagram of a frame phase aligner.

In order to achieve the above object, the present invention, by demultiplexing the reception data into a parallel signal, the first parallel converter for synchronously outputting in synchronization with the reception clock according to the first write control signal, and by demultiplexing the received reference frame into a parallel signal A second parallel converter for outputting the second write control signal in synchronization with a reference clock, and a first n / 2 bit for counting and outputting a first frame signal driven and received by a receive click provided to the first parallel converter; A synchronous counter, a second n / 2-bit synchronous counter that counts and outputs a second frame signal that is input by being bent by the reference click, and receives the output of the first n / 2-bit synchronous counter and receives the first parallel A first write control signal generator for providing a first write control signal to a converter, an output of the second n / 2-bit synchronous counter, and a second write control to the second parallel converter A second write control signal generator for providing a signal, a first phase aligner for receiving the output of the first parallel converter and aligning the phase of the received data by synchronizing the reference clock according to a phase control signal and outputting the same; The PJ doctor inputs the output of the parallel converter and registers it to the reference clock according to the phase control signal to output the second phase aligner and the output of the second n / 2-bit synchronous counter. A phase control signal generator that provides a phase control signal to a phase aligner, and receives phase-aligned received data, which is an output of the first phase aligner, and stores and converts the data into serial data according to a read control signal, and outputs them in synchronization with a reference click. A first serializer and a phase-aligned frame that is an output of the second phase aligner, and are stored and stored according to a read control signal. A read control signal for converting to serial data and outputting in synchronization with a reference clock and receiving the output of the second n / 2-bit synchronous counter and providing read control signals to the first and second serial converters; It is characterized by including a generator.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

The present invention is a frame phase aligner 1 having an input / output signal relationship as shown in FIG. 1, and as shown in FIG. 3, a 1-to-n parallel converter (2,3), n / 2 bits. Johnson counter (4,5), phase aligner (8,9), write control signal generator (6,7), phase alignment control signal generator (10), read signal generator (11), n-to-1 series converter (Para1le1-to-Serial Converter: 12,13)

Looking at the configuration and operation of each component constituting the present invention in detail.

The 1-to-n Seria1-to-Parallel Converters 2 and 3 receive data respectively coming into the input terminal Si in synchronization with clocks CKi and CKr as shown in FIG. Di, the reference frame FPr is demultiplexed into n-bit parallel signals Di, _{(n-1: 0) ±} / n, FPr / n, whose signal width is nT, as shown in (Fig. 5), and then the OE stage When the input signal is 0, it is supplied to _n- bit parallel output P _{(n-1: 0)} in synchronization with CKi and CKr, respectively. The write control signals WRi and WRr input to the OE stage are phase-locked to the frame signals FP _i , _± and FP _r respectively input to the clear stage Clr of the Jhonson counter 4 and 5, and the period is nT. It has a phase relationship shown in 4.

That is, WRi and WRr become ₀ when the output address signal CP _{(7: 0)} of the counters 4 and 5 is (1E) H, and CP _{(7: 4)} becomes (OF) _H and at the same time Di, _{(n-1: 0 / n} , FP _r / n are output to P _{(n-1: 0)} , respectively, in synchronization with clocks CKi and CKr.

The output P _{(n-1: 0)} of the 1-to-n parallel converters 2, 3 is correspondingly connected 1-1 to the input D _{(n-1: 0)} of the phase aligners 8,9. In the case of 1-to-n-parallel converter (3), since the frame signal processing FPr except P ₀ P1, P2 ..., the value of P _(nl) is not always used in the 0, P ₀ only To the input D of the phase aligner 9.

The n / 2-bit synchronous Johnson counters 4 and 5 (shown when n is 8) are driven by clocks Cki and CKr, respectively, and output address signals by FPi and FPr input to the clear stage Clr. The phases of the cycles CP ₀ , CP ₁ , ..., CP ₇ are synchronized. That is, the transition phase on the rising edge and falling edge of CP ₀ , CP ₁ , ..., CP ₇ based on FPi and FPr are delayed by T in order, as shown in FIG. 4. Duty is 50% of nT. And, as shown in FIG. 4, Since it has a complementary phase relationship of, the actual effective address signal number is n / 2 bits.

That is, since CP ₄ , CP ₅ , CP ₆ , and CP ₇ can be generated using CP ₀ , CP ₁ , CP ₂ , and CP ₃ signals, a counter of n / 2 bits is used. (CP ₀ , CP ₃ ), (CP ₁ , CP ₄ ) and (CP ₀ , CP ₇ ) are connected to inputs a and b of control signal generators 7,10 and 11, respectively, and CP ₂ , CP ₅ and CP ₆ are not used.

In the process of demultiplexing and restoring the received data, the present invention has improved jitter characteristics compared to the conventional method, because the output address signals CP ₀ , CP ₁ , ..., CP of the Johnson counters 4 and 5 are used. _Since the frequency of ₇ is reduced to 1 / n compared to the output address signal of the binary counter, when these are used, the control signals WRi input to the control inputs 0E, E, and LD of 2, 3, 8, 9, 12, and 13 are used. The frequencies of, WRr, EN and RD can also be reduced. In addition, as shown in FIG. 4, Since one or more signals do not change at the same time, only a combination of two different bits can generate a control signal without glitches indicating n timeslots within one period nT.

In the present invention, the phase control and read control signals EN, RD, and (CP1, CP4) are used in the periods β and δ using (CP ₀ , CP ₃ ) and (CP ₀ , CP ₇ ). Create each of them.

The write control signal generators 6 and 7 are implemented with two-input NAND gates, each input (a, b) connected to the outputs CP1 and CP4 of the counters 4 and 5, each output Z being a parallel converter. As shown in Fig. 4, WRi and WRr, which are output signals of the phase detectors 8 and 9, have a period nT, which means that the Jhonson counter 4,5 Each additional recording is phase-registered to the frame signals FPi and FPr input to the clear stage Clr. That is, the values of the outputs P _{(nl: 0)} and P ₀ of the parallel converters 2 and 3 become zero only during the time when the output address signal CP _{(7: 0} ) of the counters 4 and 5 is (1E) _H. This change is made, and the value remains 1 in the remaining (n-1) T intervals.

The phase aligners 8 and 9 are implemented as D-flip flops with the control signal E, and when E is 0, the data coming into D is synchronized with the reference clock CKr and outputted as Q. When E is 1, the previous value is maintained. The phase aligner 8 aligns the phase of the parallelized received data Di, _{(n-1: 0) ±} / n, and another phase aligner 9 aligns the phase of the parallelized reference frame FPr / n. . Each output signal Q _{(n-1: 0)} , Q is connected to P _{(n-1: 0)} , P ₀ which are input terminals of the serial converter 12,13.

The phase and read control signal generators 10, 11 are implemented with two-input NAND gates, each input (a, b) having an output (CP ₀ , CP ₇ ), (CP ₀ , CP ₃ ) of the counter (5). ), And each output Z is connected to the E stage, which is the control stage of the phase aligners 8, 9, and the LD of the serial converters 12, 13, respectively. In EN and RD, the period is nT, and each period is phase-locked to the frame signals FPi and FPr inputted to the clear terminal Clr of the Jhonson counter 5. That is, the phase control signal EN becomes ₀ during the time at which the output address signal CP _{(7: 0)} of the counter 5 is (F ₀ ) _H , and the phase controller 8 at the moment when the value transitions to (78) _H. The values of the inputs D _{(n-1: 0)} and D ₀ of, 9) are phase-aligned and appear in the output Q _{(n-1: 0)} , which is maintained in the remaining (n-1) T intervals. . On the other hand, the read control signal RD becomes ₀ during the time when the output address signal CP _{(7: 0)} of the counter 5 is (0F) _H , so that the input P _{(n-1: 0)} of the serial converter 12, 13 is present _. , The value of P ₀ is serially converted and appears in the nT interval. As shown in Fig. 4, the output signals Di, _{(n-1: 0)} / n ', FPr / n' phase-aligned at the phase aligners 8 and 9 by EN are nT / 2 from EN. By RD having a phase margin, the n-to-1 serial converters 12 and 13 are synchronously serially converted to CKr.

The n-to-1 serial conversion process in the n-to-1 parallel-to-serial converter (12, 13) involves the parallelism of P _{(n-1: 0) in} the nT time interval. Since the signal is uniformly distributed in red, the width of the signal output to So becomes T reduced by 1 / n compared to the signal width of P _{(n-1: 0)} . Accordingly, as shown in FIG. 3, the phase-aligned parallel data Di, _{(n-1: 0)} / n, and the parallel frame FPr /, which are commonly synchronized with the reference clock CKr and come into the parallel input P _{(nl: 0)} and P ₀ . 5, when the read control signal RD inputted to LD is 0, as shown in FIG. 5, parallel storage is performed, and when RD is 1, they are sequentially converted to serial signals D ₀ and FP ₀ whose signal width is T, and S _0. Will output For serial converter 13 is, because the handle frame signal FPr / n of one bit except for _{P 0 P 1, P 2 ...} , the value of P _nl is always kept to zero, does not connected.

In the frame phase aligner proposed in the present invention, as shown in FIG. 2, the phase θ _D of the frame bit Fi of the received data D ₀ at the aligner output is a frame of the reference frame signal FP ₀ . Match the phase (θ _FP ) of the bit Fr (θ _D (Do = Fi) CKr = θ _FP (FP ₀ + Fr)

Then, the maximum allowable deviation between FPr and FPi, which is capable of frame phase alignment, is limited to ((n / 2) -1) T around (θ _± ) FPr.

For example, when n = 8, the maximum allowable deviation is 3T, and the outputs Di, _{(n-1: 0) ±} / n, and FPr / n of the parallel converters (2,3) always overlap each other. α, β will be present.

In the present invention, in the beta section, the output EN of the phase control signal generator 10 input to the LDs of the phase aligners 8 and 9 becomes 0 (that is, EN _{θ = β} = 0), Di, _{( Let n-1: 0) ±} / n and FPr / n produce the phase alignment signals Di, _{(n-1: 0)} / n 'and FP / n', respectively, stably sampled by a common reference clock CKr. . When Di, _{(n-1: 0)} / n ', and FPr / n' are phase aligned by EN of the phase control signal generator 10, a read control signal having nT / 2 and phase margin from the phase alignment moment of EN By the output RD of the generator 11, Di, _{(n-1: 0)} / n, FPr / n are stored in parallel in synchronization with CKr of the serial converters 12 and 13, and then serially converted.

The present invention described above is capable of various substitutions, modifications, and changes within the scope without departing from the technical spirit of the present invention for those skilled in the art to which the present invention pertains, and thus is limited to the above-described embodiments and drawings. It is not.

Therefore, the present invention configured and operated as described above has the following effects.

First, the frame phase alignment scheme devised in the present invention is the output of the control signal generators 10 and 11 connected to the phase aligners 8 and 9 for controlling the phase alignment and the serial converters 12 and 13 for restoring the signal. Low frequency of signal EN, RD and no glitches ensure stable phase alignment and signal recovery at low speed.

Secondly, since the received data and the reference frame to be phase aligned are operated in synchronization with the reference clock CKr until they are restored by the serial converters 12 and 13, no signal reproduction process is required.

Claims (4)

A first parallel converter 2 which demultiplexes the received data into a parallel signal and synchronously outputs the received data in synchronization with the reception clock according to the first write control signal; and demultiplexes the received reference frame into a parallel signal to reference the second write control signal. A second parallel converter 3 which outputs in synchronization with a clock, and a first n / 2-bit synchronous type that counts and outputs a first frame signal driven and driven by a received click provided to the first parallel converter 2; A counter (4), a second n / 2-bit synchronous counter (5) for counting and outputting a second frame signal driven and driven by the reference clock, and the first n / 2-bit synchronous counter (4) A first write control signal generator 6 that receives an output and provides a first write control signal to the first parallel converter, and an output of the second n / 2-bit synchronous counter 4 that receives the output; A second providing a second write control signal to the converter A first phase aligner 8 for receiving the write control signal generator 6 and the output of the first parallel converter and aligning the phases of the received data by synchronously outputting in synchronization with a reference clock according to a phase control signal; A second phase aligner 9 for aligning the phases of the frame by receiving the output of the two parallel converters in synchronization with a reference clock according to a phase control signal, and an output of the second n / 2-bit synchronous counter 5 A phase control signal generator 10 for receiving a phase control signal and providing a phase control signal to the first and second phase aligners 8 and 9 and phase-aligned received data which is an output of the first phase aligner 8. Receives a first serial converter 12 for storing and converting into serial data according to a read control signal and outputs the same in synchronization with a reference clock and a phase-aligned frame that is an output of the second phase aligner 9. Save according to read control signal The first and second serial converters 12 and 13 receiving the outputs of the second serial converter 13 and the second n / 2-bit synchronous counter 5, which are converted into column data and synchronized with a reference clock to be output; And a read control signal generator (11) for providing a read control signal to the low speed data frame phase aligner. 2. The low speed data frame phase aligner of claim 1, wherein each of said first and second write control signal generators (6,7) is comprised of two input gates. 2. The low speed data frame phase aligner of claim 1, wherein each of said first and second phase aligners (8,9) consists of a D flip-flop with a control stage (E). 2. The low speed data frame phase aligner of claim 1, wherein each of the phase control signal generator (10) and the read control signal generator (11) comprises a two-input NAND gate.