JPS62281634A - Frame synchronizing system - Google Patents

Abstract

PURPOSE:To quickly set up the frame synchronization by storing the pattern that does not exist in other slots into a frame header consisting of at least two slots to use as a synchronizing pattern. CONSTITUTION:The pattern that does not exist in other slots is stored into frame header as a synchronizing pattern. In an 8B1C coding system a single time slot consists of the 8-bit data and a C bit serving as a 1-bit complementary code. Even in case the final bit (C bit) of the time slot is equal to '1' and the first 8 bits of the following time slot are equal to '1', the 9th bit of the latter time slot is equal to '0'. Therefore >=10 pieces of '1' never follow in any cases and also 10 pieces of '0' never follow either. While 10 pieces of '1' follow at the frame header part. Such an array of 10 pieces of '1' is never found in other slots, therefore the frame header can be easily detected by detecting those 10 continuous pieces of '1'.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Configuration of the Invention] (Field of Industrial Application) The present invention relates to a frame synchronization method in data transmission.

(Prior art) With the development of information processing technology, various systems have been developed in which a plurality of distributed information processing devices are connected to an information transmission path through a station, and information is transmitted between these information processing devices. has been done. This type of system is increasing in scale from local area networks (LANs) to metropolitan area networks (VANs).

FIG. 3 is a diagram showing the principle of communication in such a system. As shown in the figure, stations 1 and 3 are connected via a transmission line 5. Stations 1 and 3 each have a transmission section 7a.
, 7b and logic sections 9a and 9b. Transmission section 7a, 7
b sends and receives data. The logic units 9a and 9b control the transmission units 7a and 7b.

In the transmission units 7a and 7b of such a communication system, the following requirements are required for the transmission method. That is, (1) the same code does not continue for a long time, (2) static pattern jitter is suppressed, and (2) the increase in transmission line speed is suppressed to a low level.

On the other hand, the requirements for the transmission system in the logic units 9a and 9b include: (1) being able to send information of any pattern; and (2) being able to detect frame synchronization in a simple manner and in a short time.

There is a transmission path coding (m81C coding) method as a transmission method that partially satisfies such requirements.

FIGS. 4 and 5 are block diagrams showing the configurations of the transmitting side and receiving side of this mB1C encoding system.

As shown in FIG. 4, the transmitter side includes a parallel-to-serial converter 11, a scrambler 13.8B1C encoder 15, a transmitter 17, a transmission timing generator 19, and a frame header generator 21.

The parallel-to-serial converter 11 converts parallel transmission data into serial data. The scrambler 13 randomizes the transmitted data converted into serial data to suppress static pattern jitter. The 8B1C encoding unit 15 inserts a C bit into every 8 bits of the scrambled transmission data. This C bit is the 8th bit complementary code data.

FIG. 6 shows the encoded data by this 881C encoder 15. The first 8 bits are the data part, and the 9th bit is the complementary code of the 8th bit ('O' in this case). C bit is inserted.

Furthermore, the following 8 bits are the data part, and the next 1 bit is inserted as the C bit.

The transmission timing generator 19 provides a reference clock signal to the parallel-to-serial converter 11, the scrambler 13.8B1C encoder 15, and the frame header generator 21.

A frame header generation unit 21 generates a frame header indicating the beginning of a frame. The transmitter 17 transmits the data encoded by the 8B1C encoder 5 via the transmission line 5, with a frame header generated by the frame header generator 21 added to the beginning of the frame.

FIG. 7 is a format diagram of a frame transmitted from this transmitter 17. As shown in the figure, one frame is 12
5 μs, and the frame header FH is placed at the beginning of the frame.
is inserted, followed by a 9-bit time slot consisting of 8 bits of scrambled data and 1 C bit.

FIG. 5 is a configuration block diagram of the receiving side, and as shown in the figure, this receiving side includes a receiver 23, a word synchronization establishment protection unit 2
5, a word timing generating section 27, a frame synchronization detecting section 29, a descrambler 31, and a multilayer conversion section 33.

The receiver 23 receives the data sent from the transmission path 5, and the word synchronization establishment protection unit 25 detects breaks in time slots that satisfy the complement rule. If so, a signal is sent to the word timing generator 27. This word timing generator 2
7 receives the signal from the word synchronization establishment protection section 25 and sends the signal to the frame synchronization detection section 29.

When the two frame synchronization detectors receive a signal from the word timing generator 27, they determine this as a slot break, and detect the frame header from this slot break. In this case as well, it is assumed that frame synchronization has been achieved if the frame header is detected multiple times at a fixed frame period.

Note that the descrambler 31 descrambles the data sent from the receiver 23, and the parallel converter 33 converts serial type data into parallel type data.

(Problems to be Solved by the Invention) As described above, in the conventional frame synchronization method, word synchronization is performed to establish frame synchronization on the receiving side.
Since frame synchronization is performed roughly, there are problems in that the circuit configuration on the receiving side is complicated and it takes a long time to establish synchronization.

The present invention has been made in view of these problems, and an object thereof is to provide a frame synchronization method in which a circuit for performing frame synchronization is simple and frame synchronization can be quickly established.

[Structure of the Invention] (Means for Solving the Problems) In order to solve the above problems, the present invention provides a data transmission frame that transmits a frame in which mB1C encoded (m+1) bit slots are multiplexed. In the synchronous method,
It is characterized in that a pattern that does not exist in other slots is stored as a synchronization pattern in a frame header consisting of at least two slots.

(Function) Therefore, give 2 slots 1 or more as a frame header,
Since a pattern that does not exist in other slots is given to this frame header slot, frame synchronization can be easily achieved on the receiving side by detecting this pattern.

(Example) Hereinafter, embodiments will be described in detail based on the drawings.

FIG. 1 shows a frame header FH of a frame synchronization system according to an embodiment of the present invention.

This frame header consists of two slots, the first slot is '1' or 9 consecutive bits are arranged, the first bit of the second slot is the same code as '1' to the first slot l, and the second The first bit is a complementary code "O", followed by 6 bits of command information, and finally a C hit as a complementary code of the last hit of the command information.

FIG. 2 is a configuration circuit diagram of a frame synchronization detection section on the receiving side. As shown in the figure, this frame synchronization detection section 35 consists of an 11-bit shift register 37, three inverters, and an AND gate 41. . Data is input to the shift register 37 from the data input terminal in accordance with a clock signal input from the tarlock input terminal CK, and the data is shifted one bit at a time.

Next, the operation of this embodiment will be explained.

Since this example uses the 881C encoding method,
One time slot 1- consists of 8-bit data and a C bit as a 1-bit complementary code. That is, in one time slot l, the number of consecutive same codes is limited to eight at most. If the last bit (C bit) of the current time slot is "1" and the first 8 bits of the following time slot are "1", then the 9th bit of the required time slot is O'. Therefore, under no circumstances will ten or more "1's" be consecutively lined up.

Similarly, there are no more than 10 "○"s in a row.

On the other hand, in the frame header part, "1' is 1" as shown in the previous).
I'm trying to line up 0 items. Since this arrangement of 10 '1's is not seen in other time slots, the frame header can be easily detected by detecting these 10 consecutive '1's.

Q of shift register 37 as shown in FIG.

When bits 1 to 09 become "1" and the QA bit becomes ○, the output of and goo (~41 becomes "1". In other words, the first 11 bits of the frame header shown in Figure 1
Only when a bit is captured by this shift register, the output of AND gate 41 becomes "1".

In this manner, in this embodiment, frame synchronization can be quickly established using a simple circuit.

Note that the present invention can be modified in various ways within the scope of its technical idea.

For example, in this embodiment, the frame header is 10
In this case, in the circuit shown in FIG. 2, the QoC bits are inverted by an inverter, so that 1's are lined up (or 101 O's are lined up. The QA bit inverter 39 can be removed.

In this example, the 881C encoding method is taken as an example, but the 881C encoding method is used as an example.
It is not limited to 81C, and may be, for example, 1081C. In the case of the 10B1C encoding system, the synchronization pattern consists of 12 consecutive bits of the same code and 13 bits of its complementary code.

Roughly speaking, in this embodiment, the second slot of the frame header is used as command information, or it can be fixed as a synchronization pattern, and 2 slots and 18 bits can be used as the synchronization pattern. In this case, since the number of bits in the synchronization detection pattern is large, the probability of pseudo-invention occurring due to a code error is extremely small.

[Effects of the Invention] As described above in detail, according to the present invention, the circuit for performing frame synchronization is simple, and frame synchronization can be quickly achieved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a frame header pattern in one embodiment of the present invention, FIG. 2 is a circuit diagram showing the configuration of a main part of a frame synchronization detection circuit according to the same embodiment, and FIG. 3 is a data transmission diagram. Figures 4 and 5 do not show the principle of 8BI.
FIG. 6 is a block diagram of the configuration of the transmitting side and receiving side of data transmission using the C encoding method. FIG. 6 is a diagram showing an example of the data configuration using the 881G encoding method. FIG. 7 is a diagram of the frame format in the 881G encoding method. . 35... Frame synchronization detection circuit 37... Shift register 39... Inverter 41... ANDGATE Applicant Toshiba Corporation Patent attorney Satoshi Suyama - Figure 1 Figure 2 Figure 3

Claims (3)

[Claims] (1) In a frame synchronization method for data transmission that transmits a frame in which mB1C encoded (m+1) bit slots are multiplexed, a pattern that does not exist in other slots is used as a synchronization pattern in a frame header consisting of at least two slots. A frame synchronization method characterized by storage. (2) The frame synchronization method according to claim 1, wherein the synchronization pattern consists of a continuous identical code string of (m+2) bits, a complementary code of 1 bit, and a command information bit of (m-2) bits. (3) The frame synchronization method according to claim 1, wherein the synchronization pattern consists of a continuous identical code string of (m+2) bits, a complementary code of 1 bit, and a fixed pattern bit of (m-2) bits.