JPS62292037A - Synchronizing code detection circuit - Google Patents

Abstract

PURPOSE:To detect a synchronizing signal by a few number of constituents, by multiplexing plural input code groups by every bit, and comparing an output after multiplexing, with a prescribed synchronizing signal detecting signal. CONSTITUTION:Inputted plural input code groups are multiplexed by every bit by a multiplexing circuit 1. The output is compared with the prescribed synchronizing signal detecting signal at the first comparator 2, and also, it is code-converted at a code converter 4. By comparing the sizes of a code- converted conversion signal, and a prescribed conversion signal at the second comparator 6, a specific synchronizing code is outputted from the plural input code groups. Thereby, since the circuit 1 multiplexes the input code group corresponding to synchronizing codes included over entire plural input code groups, the constitution of a detection circuit, etc., can be simplified.

Description

[Detailed Description of the Invention] 3. Detailed Description of the Invention [Field of Industrial Application] This invention detects a synchronization code necessary to determine the timing of receiving a burst in a burst communication system such as a TDMA satellite communication system. This invention relates to a synchronization code detection circuit.

[Conventional technology]

Conventionally, in burst communication systems, synchronization codes are detected to determine the burst reception timing.
Often this detection involves not only one type of input signal sequence;
There are cases where it is required to simultaneously receive two series of signals and detect the synchronization code contained in the series. FIG. 3 shows a conventional phrase period code detection circuit disclosed in Japanese Unexamined Patent Publication No. 177058/1983 as a general configuration of a circuit that meets such requirements. In the figure, 7a.

7b receives the input signal 8a or 8b, determines whether the Hamming distance between the input signal and the synchronization code to be detected is smaller than a predetermined value, and generates a signal according to the result. Generated detection circuit, 9a, 9bt! These are output signals of the detection circuits 7a and 7b. This detection circuit 7a
, 7b are added by the parallel adder 4, and the Hamming distance value 4 obtained by the parallel adder 4 is
The comparator 6 compares a with a threshold value for the Hamming distance given by the data generator 5.

The output of the comparator 6 is taken out as the M detection signal 6a.

FIG. 3 shows the detection circuit 7a in FIG. 4 above.

7b shows a specific circuit configuration. In the figure, 8 is a shift register that accommodates an input signal 8a applied through an input terminal, and its length is determined to be equal to the code length of the synchronization code to be detected.

In addition, the comparator 2 outputs the output from the shift register 8 and the code generator 3 that generates a replica of the synchronization code to be detected.
The bits are compared bit by bit, and when both have lost, a logical value of ``1'' is generated, and when there is a mismatch, a logical value of ``0'' is generated.

9 is a parallel adder that converts the number "1" indicated by the comparison result of the comparator 2 into, for example, a double code; 9a is an output signal of the parallel adder 9;

Next, the operation of the conventional configuration shown in FIGS. 3 and 4 will be explained. First, in the detection circuit 7a of FIG.
A case will be described in which the Hamming distance between the input signal 8a and the synchronization code is detected. That is, the input signal 8a is serial-parallel converted by the shift register 8, and the result is led to the comparator 2. The comparator 2 performs a bit-by-bit comparison between the output of the serial-to-parallel conversion and the output of the code generator 3, and as a result,
A logic value "1" is output for bits that are found to match, and a logic value "0" is output for bits that do not match. Here, the code generator 3 always generates a replica of the synchronous code, so that the shift register 8
When the code sequence accommodated in exactly corresponds to the synchronization code, the comparator 2 outputs a number of "1"s equal to the synchronization code word length. Furthermore, when the code sequence stored in the shift register has a Hamming distance P with respect to the synchronization code, there are P logical values "0" and "1" as many as the code word length minus P.
is output from comparator 2. Subsequently, the parallel adder 9 expresses the number of logical values rlJO present in its input signal by a corresponding numerical value. For example, it is converted into a double code and outputted as the output signal 9b of the parallel adder 9.

Since the signal modulated into 4-phase PS becomes a two-channel code sequence, detection of synchronization codes must be performed in parallel and simultaneously. In this case, a specific synchronization code is detected by using the circuit configuration shown in FIG. The parallel adder 4 calculates the sum of the output signals 9a, 9b of the parallel adder 9 obtained independently by the detection circuits 7a, 7b.

The output signal of the parallel adder 4 is converted into, for example, a double code, and compared with the code generated by the data generator 5 in a comparator 6. The comparator 6 converts the code generated by the data generator 5 into L-
If the code length is determined to correspond to a code length M, when a code whose Hamming distance from the synchronization code to be detected is smaller than M is stored in the shift register 8, the output signal 6
A logical value "1" is output as a. Here, L is the code length of the synchronization code.

[Problem that the invention seeks to solve]

Conventional synchronization code detection circuits are configured as described above, so in order to detect a specific synchronization code from parallel code sequences, it is necessary to provide as many detection circuits as there are code sequences, making the circuit configuration complicated. , and there were also problems such as a large number of constituent elements.

This invention was made to solve the above problems, and even when detecting a specific synchronization code included in multiple code sequences, it is possible to use a synchronization code detection circuit with a smaller number of elements and the same circuit structure. The purpose is to obtain.

[Means for solving problems]

The synchronization code detection circuit according to the present invention multiplexes a plurality of input code sequences bit by bit using a multiplexing circuit 1,
The first comparator 2 compares this output with a predetermined synchronization code detection signal, the code converter 4 converts the code, and the second comparator 6 converts the code into a predetermined conversion signal. A specific synchronization code is output from the plurality of input code sequences by comparing the sizes.

[Effect]

In the synchronization code detection circuit according to the present invention, since the multiplexing circuit 1 multiplexes input code sequences corresponding to synchronization codes included over a plurality of input code sequences, the configuration of the detection circuit and the like is simplified.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, 1 is a multiplexing circuit that multiplexes bits, la, l
b is an input signal sequence containing a specific synchronization code to be detected, and is given from the outside. IC is multiplexing circuit 1
This is the output of A code generator 3 generates a replica of the synchronous code to be detected, and its output is led to a comparator 2.

The comparator (first comparator) 2 is a circuit that inputs the output 1c of the multiplexing circuit and the output of the code generator 3 and compares them bit by bit. leads the logic value "0" to the parallel adder 4 as the output signal 2a of the comparator 2. The parallel adder (code converter) 4 is a circuit that converts the number of "1"s output by the comparator 2 into, for example, 2-way code data, and provides a converted signal 4a to the comparator 6. 5 is a data generator that generates data to be compared with the 2-way code data 4a provided by the parallel adder 4; 6 is a data generator that compares the magnitude relationship between the converted signal 4a output from the parallel adder and the output signal of the data generator 5; This is a comparator (second comparator) that makes a determination and provides the result, and its output is taken out to the outside as a synchronization code detection signal 6a.

Next, the operation of an embodiment of the synchronization code detection circuit according to the present invention having the above configuration will be described. In FIG. 1, input signal sequences 1a and l containing the synchronization code to be detected are shown.
b is given from the outside and input to the multiplexing circuit bit by bit. The multiplexing circuit 1 multiplexes input signals at the timings shown at la, lb, and lc in FIG. The multiplexed signal becomes a parallel signal IC with a number of bits equal to the code length of the synchronization code, and is led to a comparator 2, where a bit comparison is performed with a replica of the synchronization code given from the code generator 3 as a fixed pattern. The synchronization code recorded in the code generator 3 is a code obtained by multiplexing the synchronization codes included in the input signal sequences la and lb. Therefore, input signal series 1
When a and lb match the synchronization code, the signal 1c input to the comparator 2 and the output signal of the code generator 3 become the same.

On the other hand, only when the same code is compared, the comparator 2 outputs a logical value "1" corresponding to the code length of the synchronization code.
is obtained as the input signal 2a. The parallel adder 4 outputs the logical value “
Since the circuit converts the number of "1" into, for example, a 2-bit code, as a result of the comparison by the comparator 2, the number of matching bits is shown in, for example, a binary number. Therefore, the data generator 5
If it is determined that the base number -M is generated, the comparison will be made when the input signals 1a and lb of the multiplexing circuit 1 contain a code whose Hamming distance from the synchronization code to be detected is smaller than M. The output 6a of the device 6 becomes a logical value "1". The signal indicated by 6a in FIG. 2 is a specific example.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of input code sequences are multiplexed bit by bit, the output after multiplexing is compared with a predetermined synchronization code detection signal, code conversion is performed, and the converted signal is converted into a predetermined signal. Since the configuration is configured to output a specific synchronization code by comparing the magnitude with the converted signal, the synchronization code can be detected with a small number of components.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of a synchronization code detection circuit according to an embodiment of the present invention, FIG. 2 is an explanatory diagram showing an example of signals of main parts in the synchronization code detection circuit of FIG. 1, and FIG. 4 is a block diagram showing the general configuration of a synchronization code detection circuit that detects synchronization codes included across a plurality of input signal sequences, and FIG. 4 is a block diagram showing details of the synchronization code detection in FIG. 3. 1... Multiplexing circuit, la, lb... input signal, IC
... Multiplexing circuit output signal, 2 ... Comparator (first comparator), 2a ... Comparator output signal, 3 ... Code generator, 4 ... Parallel adder (code conversion 4a...Parallel adder output signal, 5...Data generator, 6...Comparator (second comparator), 6a...Comparator output signal. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] A multiplexing circuit that inputs a plurality of input code sequences including synchronous codes and multiplexes the input code sequences bit by bit, and a synchronous code detector that receives an output signal from the multiplexing circuit and that is stored in a code generator in advance. a first comparator for comparing the signal;
a code converter that converts the output of the comparator and outputs a converted signal; and a code converter that converts the output of the comparator and outputs a converted signal; a second comparator that outputs a specific synchronization code from an input code sequence.