JPS6347848A - Parity checking method - Google Patents

Abstract

PURPOSE:To obtain a parity checking method with high reliability, by selecting a four bit pattern in which a disparity does not go to 0, out of a 3B/4B block, and setting three bits decoded corresponding to four bits as parity check signals. CONSTITUTION:A data of eight bits is divided into high order three bits and low order five bits, and it is converted to the data of ten bits with four bits and six bits, by an 8B/10B code conversion circuit 15, and a parity generator 8. Next, the data of ten bits is divided into the data of eight bits with high order three bits, and low order five bits, by a 10B/8B decoding circuit 17, and the parity generator 8, and the high order three bits are used as parity check bits. In this way, it is possible to perform the error check of the data of eight bits equivalent to ordinary parity check in 8B/10B code conversion, and to improve the reliability of a command in line switching, etc.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a parity check method.

[Prior Art] Data transmission often requires code conversion. Regarding this, for example, JP-A-59-100
As disclosed in Japanese Patent No. 56, an 8B/10B code conversion method for expanding 8-bit data to 10-bit data is known.

This code conversion method separates 8 bits into 5 bits 1- and 3 bits, expands them to 6 bits and 4 bits, and
The purpose is to obtain a 0 bit.

Tables 1 and 2 show the data and their expanded and converted numerical values.Table 1 shows the case of converting 5-bit data to 6-bit data, and Table 2 shows the case of converting 3-bit data to 4-bit data.
Shows the case of converting to bit data.

For each person, Do indicates the difference between the number of "1" and rOJ after code conversion, that is, disparity. ).

Table 1 *DO: Difference between the numbers of 1 and O after sign conversion, disparity.

Table 2 *Do: Difference between the numbers of 1 and O after code conversion, disparity.

Next, FIG. 3 shows a state transition diagram during code conversion.

In the figure, state 1 and state 2 have disparity (+
) and (-). State 1j33 and state fl14 indicate a transition between state 1 and state B2 depending on whether the disparity is (+). In states 5 and 6, the disparities are both (0), indicating that states 1 and 2 are maintained as they are. In each state in the figure, encoding is performed so that discovery does not occur irregularly, so using this rule, code errors and
In other words, coding rule errors can be detected.

Regarding this type of technology, 1. So, A, X, Widmc
r, P, A, l”ranaszek: “A Day-
Sea Balanced, Partitioned Block, 8B
/10B Transmission Code", ("A DC-Balanced 1Partiti
oncd-B 1ock18 B/ 10 B Tr
anmission Code ” >IBM J
, RES, DEVELOP, VOL27.

[Problems to be Solved by the Invention] As mentioned above, in one conventional code conversion, error detection is performed based on the code law of disparity.
This error cannot necessarily be detected in the block where the error occurred. FIG. 4 shows the situation at this time.

In the figure, Da represents the disparity that occurs when the 8B/10B code is repeated alternately with the 5B/6B block and the 3B/4B block, with (+) in the upper row and ((+) in the middle row).
0), the bottom row is (-).

Db represents the state of disparity, and shows the case where the disparity changes from (+) to (-) corresponding to state 3.4 in FIG.

Further, DC represents the case where a sign rule error is detected from [)a and Db.

In each case of Da, Db, and Dc, a solid line represents a state without error.

Now, as shown by the broken line a in Oa in the same figure, the disparity is (
If an error occurs from (0) to (-), the state of disparity will respond as shown by mb, as shown by Db, and will change from (→-) to (-). However, since this disparity state Db originally transitions from (+) to (-), even if a change like the one shown by the broken line occurs, it cannot be determined as an error, and therefore an error cannot be detected. . In this case, detection is performed using the broken line a and the broken line C1 indicated by the code rule error Dc.

Further, since the conventional 88/IOB code is decoded based on Tables 1 and 2, a 1-bit error will cause a maximum of 5 errors in a burst error.

In a normal parity check, for example, 1 bit of parity is added to 7 bits of data to check the validity of the data, but in the case of 8B/10B codes, such a parity check should be performed due to the problems mentioned above. I can't. For example, by adding odd parity to the 7-bit data shown as [00000101,
0], and from Tables 1 and 2, 88/IOB
When converted into a code, it becomes [0110001001].

Now, if the sixth bit from the left of this bit string causes an error, this bit string becomes [0110011001]. When this is decoded, it becomes [011001001, and even if it is a military error, the error cannot be detected by parity. Furthermore, in this bit string, [011001] and [10011] both have disparity (0), so they cannot be detected due to an 8B/10B sign rule error.

As described above, in the conventional 8B/10B code conversion, it is difficult to detect errors, which poses a problem that hinders system operation.

An object of the present invention is to provide a highly reliable parity check method in 8B/10B code conversion.

[Means for Solving the Problems] The present invention combines a 3B/4B block for expanding 3-bit data into 4-bit data and a 5B/6B block for expanding 5-bit data into 6-bit data to generate 8-bit input data. In 8B/10B code conversion for converting data into 10-bit data, a 4-bit pattern whose disparity does not become zero is selected from the 3B/4B block, and in addition to the 6-bit pattern of the 5B/6B block, the 4-bit pattern is
bits and 6 bits, and then convert these 4 bits and 6 bits into a string of bits and 6 bits.
Decode the bit string into 10 bits and extract the upper 3 bits and lower 5 bits.
A highly reliable parity check method characterized in that the decoded 3 bits that are converted into an 8-bit string and decoded corresponding to the previous 24 bits are used as a parity check signal to detect an error τ in the input 8-bit data. The objective was to be achieved by ensuring that the

[Function 1] In the parity check method of the present invention, 8-bit data is divided into upper 3 bits and lower 5 bits, and this is divided into 8B/1
The 0B code conversion circuit and the parity generator convert it into 10 bits, 4 bits and 6 bits, and then these 10 bits are converted into 8 bits, the upper 3 bits and the lower 5 bits, by the IOB/8B decoding circuit and the parity generator.
Since the upper three bits are used as parity check bits, a reliable parity check method can be obtained.

[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a parity generation circuit diagram of an embodiment of the parity check method of the present invention, which is a circuit for converting 8 bits into 10 bits.

FIG. 2 is also a parity check circuit diagram, and is a circuit for detecting errors based on the recovered validation signal.

In these figures, 7 is input data, which is composed of 8 bits from 8 to 1. 8 is a parity generator which inputs the 5-bit data of A to E of the input data 7 and generates odd parity or even parity. 9
is a parity select signal which selects whether to output the 8-bit data as is or to add parity to the data of the lower 5 pits. 10-1
4 is a gate circuit, and when adding parity, the upper 3 bits F G
H is converted to [001] or [0001], and when parity is not added, the upper 3 bits FGH are passed through as is. 15 is an 8B/10B code conversion circuit, and 16 is a 10-pit output of the converted 8B/10B code.

Next, 17 is a 10B/8B decoding circuit which inputs the output 16 of the 8B/10B code and decodes 10 bits into 8 bits. 18 indicates a sign rule error signal. 19 is a set/reset type flip-flop that stores the sign rule error signal 18; 20 is an exclusive OR gate which converts the output parity of the parity generator 8 into a 10B/8B decoding circuit 17.
Errors are detected by comparing the parity generated from the

21 to 23 are gate circuits that output the occurrence of an 8B/IOB code rule error or a parity error.

24 is an error detection signal terminal.

In the parity generation circuit and parity check circuit of this embodiment, if the parity select signal 9 is rOJ,
Since the gate circuits 10 to 14 are turned on, the 8-bit signals A to G1 of input data 7 are converted to the 8B/10B code conversion circuit 1.
5, and the code is converted.

When the parity select signal 9 becomes "1", the operation of the gate circuit 10 causes
Only the lower 5 bits of E are significant for data and 1) and are input to the 8B/10B code conversion circuit 15. F to H
For the top three pits, the output of parity generator 8 is “1”.
” is converted to [001], and “O” is converted to [0
00] and input to the 8B/10B code conversion circuit 15. The codes of these 3 bits input to the 8B/10B code conversion circuit 15 are based on Table 2, and [001] is [001].
0010] and [000] are converted into 4-bit codes as [01001, and their disparities DO are both (-). (Table 2 also shows the complements of these codes).

The output data 16 of the 8[3/10B code thus converted is input to the composite circuit 17 and decoded.

In FIG. 2, when the parity select signal 9 is rOJ, only the sign rule error 18 is output to the error detection terminal 24 because the gate circuit 22 is off. When the parity select signal 9 is "1", it indicates the parity check state, and the lower 5 bits A to E of the 8-bit data obtained from the decoding circuit 17 are input to the parity generator 8 and the parity signal P is extracted. . By comparing this parity signal P and the most significant bit H of the decoded data at the exclusive OR gate 20, if the comparison values are different, an error signal is output from the terminal 24, indicating that an error has been detected. Become.

When performing a parity check, since the F bit and G bit are fixed to rOJ,
1” appears, gate circuits 21 to 23 operate [)
, an error signal is output from the terminal 24.

When detecting an error in 8B/10B code, the error is 5B.
/6B block has an even number, 3B/4B block has an odd number, 5B/6B block has an odd number, 3B/4[
There are two possible cases where there is an even number of blocks in three blocks. If the former 3 B/4 B block has an odd number of errors, it is converted to data other than [000] and [001] from Table 2, and an output is generated to the OR gate 21 to detect the error.

In the latter case, if there is no error in the 3B/4B block, 3B
Since the disparity of the /4B block is not "0", an error will be detected by checking the disparity of the 5B/6B block or the 3B/4B block. However, disparity becomes "0" due to an odd number of errors in the 5B/6B block, and an even number of errors occur in the 3B/4B block, such as [
0100] to [1011] or [1101], or [0010] to [1101] or [1011]
Error detection becomes difficult if a situation arises in which the values are the same or have opposite signs.

If an even number of errors occur in both the 5B/6B block and the 3B/4B block, the error can be detected.

In addition, in the above explanation, the data in the 3 B/4 B block is number O [0001 and number 4 [0001] from Table 2.
001], but in the case of this embodiment, the disparity does not need to be "0", so in Table 2, any arbitrary number from among these three numbers, including number 7 [111], can be used. You can choose between the two and use them to avoid parity pits.

In addition, in conventional 88/IOB code conversion, 5B/6B blocks are encoded first, and decoding is also performed first, but these encoding and decoding are performed first on 3B/4B blocks. Then, it becomes possible to set the data to 3 bits and select any two blocks whose disparity does not become "0" from among the 5-bit blocks as parity pits and make them correspond to each other.

As described above, by using this actual droplet example, the following effects can be obtained. (In 118B/10B code conversion, an error check equivalent to a normal parity check can be performed on 5-bit data. (Z @ It is possible to improve the reliability of commands in line exchange, etc.)

[Effects of the Invention] According to the present invention, a highly reliable parity check method in 8B/10B code exchange can be provided.

[Brief explanation of drawings]

FIG. 1 is a parity generation circuit diagram of an embodiment of the parity check method of the present invention, FIG. 2 is a parity check circuit diagram, FIG. 3 is a state transition diagram during code conversion, and FIG.
The figure is an explanatory diagram when an error occurs. 2: Paris day generator, 4 to 8 gate circuit, 9: 8B/10B code conversion circuit, 11: 10B/88 decoding circuit, 14 to 17: gate circuit. Figure 1 Akira 3rd Figure 4

Claims (1)

[Claims] (1) 3B that expands 3-bit data to 4-bit data
In 8B/10B code conversion that converts input 8-bit data to 10-bit data by combining a /4B block and a 5B/6B block that expands 5-bit data to 6-bit data, disparity is extracted from the 3B/4B block. Select a 4-bit pattern in which is not zero, add it to the 6-bit pattern of the 5B/6B block, convert it into a 4-bit and 6-bit string, and then decode 10 bits of the 4-bit and 6-bit string. A parity check characterized in that the data is converted into an 8-bit string of upper 3 bits and lower 5 bits, and the decoded 3 bits corresponding to the 4 bits are used as a parity check signal to detect errors in the input 8-bit data. Method.