GB2109200A - Digital data encoding - Google Patents
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- GB2109200A GB2109200A GB08127791A GB8127791A GB2109200A GB 2109200 A GB2109200 A GB 2109200A GB 08127791 A GB08127791 A GB 08127791A GB 8127791 A GB8127791 A GB 8127791A GB 2109200 A GB2109200 A GB 2109200A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
- G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
- G11B20/10—Digital recording or reproducing
- G11B20/14—Digital recording or reproducing using self-clocking codes
- G11B20/1403—Digital recording or reproducing using self-clocking codes characterised by the use of two levels
- G11B20/1423—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code
- G11B20/1426—Code representation depending on subsequent bits, e.g. delay modulation, double density code, Miller code conversion to or from block codes or representations thereof
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/001—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used
- H03M7/005—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits characterised by the elements used using semiconductor devices
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Abstract
An encoder for converting an input binary word into an output word with a greater number of bits has a first coding section (PROM 1, I1) responsive to a first group of the input bits (L1, bits 1-9) to produce a first group of output bits (L2, bits 1-10), whilst the remaining output bits are produced by a second coding section (logic CL, PROM2, PG), in dependence on the remaining input bits and on the first group of bits and/or (as shown) outputs (j, k) of the first coding section. A coding method involves generating output words in each of which (a) there are a predetermined number of binary ones and zeroes, (b) the number of consecutive identical bits in each output word is not more than a predetermined limit and (c) the numbers of consecutive identical bits at the beginning and end of the output word are not more than respective ones of a pair of predetermined numbers the sum of which is equal to the said predetermined limit, whereby the number of successive identical bits which can occur in a serial data transmission of successive output words does not exceed the said predetermined limit. <IMAGE>
Description
SPECIFICATION
Digital data encoding
The present invention relates to methods and apparatus for encoding of digital data. It is especially, although not exclusively, concerned with coding of data into forms for subsequent transmission into bit-serial form, and will be discussed particularly with reference to the recording of such encoded serial signals, although it is not limited to such applications.
The aim of recording channel coding (as used, for example, in digital video recorders) is to convert input binary coded data into a form that can be recorded and replayed from magnetic tape. It is difficult to recover
DC information from this medium using conventional tape heads and it therefore necessary to code a particular sequence of input data into a unique block of coded data which must possess over a certain period a nearly equal number of binary "1's" and "0's". Furthermore, it is desirable to keep strings of single valued digits as short as possible. If this is not done, bit-cell boundaries in the tape domain are indeterminate. Long periods without data transitions can also put great demands on clock recovery circuits and require off-tape data "jitter" to be extremely low.
According to one aspect of the present invention there is provided a method of coding digital data in which an input binary word having a plurality of bits is converted into an output word having a greater number of bits, comprising generating in response to each input bit combination, a respective output word, wherein:
(a) each of the said output words has a predetermined number of binary ones and zeroes;
(b) the number of consecutive identical bits in each output word is not more than a predetermined limit; and
(c) the numbers of consecutive identical bits at the beginning and end of the output word are not more than respective ones of a pair of predetermined numbers the sum of which is equal to the said predetermined limit, whereby the number of successive identical bits which can occur in a serial data transmission of successive output words does not exceed the said predetermined limit.
Preferably each of the said output words has an equal number of binary 1's and 0's.
There will now be described some examples of 20: 16 channel codes embodying the invention. The channel code involves transforming a word or block of input data of 16 bits into a word or block of output data of 20 bits. The input data is free to have any value in the 16 bit range (i.e. 0 to 65,535), but the output word conforms to certain properties. These are:
(1) all twenty-bit words contain ten binary "1's" and ten binary "O's".
(2) comparing the first and second ten bit blocks of which the twenty bit word is composed, then the disparity of binary "1's" (or "0's") between them is no more than two. In other words, each ten-bit block will have 4, 5 or 6 binary "1's" and 6, 5 or 4 binary "0's".
(3) considering the distance between the beginning of the word and the first transition and the distance between the last transition and the end of the word, then the sum of these two is no more than 4 bit cells.
Different codes may be developed by apportioning these four bits differently between the ends of the word.
In any one code the distribution of these is the same for all code words to ensure that the string length between any two data words, when transmitted serially in succession, does not exceed 4 bit cells.
(4) within any twenty-bit word the maximum distance between any adjacent transitions (i.e. the maximum number of consecutive identical bits) is 4 bit cells.
There are approximately 87,000 words which conform to these parameters, compared to the 65,536 needed for a 16 bit coding range. The 20,000 spare code words can be used, if desired, for control purposes, for example - in the case of video recording - for framing and/or communicating other data such as line numbers, sync edges etc. In particular, there are spare code words which are distinguishable from the notional 20-bit word which may straddle the boundary between any two valid data words, and these are especially useful in framing applications.
Encoding and decoding operations for this code can be implemented using a read-only-memory look-up table. Although implementation of this does not present any technical problems, the memory requirement would be in excess of 16 M bits which represents a substantial cost, although improvements in memory technology with the availability of larger, cheaper memories may well make this a more attractive proposition.
Unfortunately, there does not seem to be any direct algorithm for effecting the coding or decoding operations for the code described, in order to avoid the use of look-up. However, an alternative code is proposed, with, with a slightly relaxed specification, which substantially simplifies the storage requirement, using about 2 K bytes of memory and some sequential coding logic.
The alternative code is based on dividing the input data word into smaller blocks. The first of the smaller blocks is then coded as an entity, with the coding of the second block being carried out taking regard of any limitations imposed by the nature of the first. In this way successive blocks would carry less information as they would be subject to more preconditions. Thus the sixteen-bit input word is regarded as comprising a first block of nine bits and a second block of seven. Each of these is transformed into ten bits of output data.
This separation of the encoding processing into two parts reduces the number of output bit combinations which can be obtained, and the number of possibilities is therefore increased by relaxing the "consecutive bits" requirement from four cells to five cells. The first nine input bits can then be coded into a ten-bit output block, whilst the remaining seven bits can be encoded into ten output bits taking account of the result of the encoding of the first block. In order to simplify the degree of dependence of the coding of the second block on that of the first, an additional restriction is imposed, namely that each block is subject to restrictions as to the number of consecutive identical bits which may occur at the beginning and end.Thus this alternative embodiment of the coding method of the invention requires that no more than the first three bits of any block may be the same as one another and no more than the last two bitsh may be the same as one another.
This limits the maximum number of consecutive bits at transitions between blocks or between words to a maximum of five.
Data encoded according to this method has, when converted to a serial output, a relatively low low-frequency content, most components being contained in a four octave range.
The invention also extends to an encoder which may be employed for implementing the method just discussed, although its application is not limited to this particular code.
In another aspect, therefore, the invention provides an encoder for converting an input binary word having a plurality of bits into an output binary word having a greater number of bits, comprising first coding means responsive, in use, to a first input group consisting of only some of the input bits to produce a first group of output bits and second coding means responsive in use, to a second input group consisting of the remaining input bits and to outputs of the first coding means and/or the said first group of input bits to produce a second group of output bits.
An exemplary embodiment of the invention will now be described with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of a 20:16 encoder:
Figure2 shows in detail the coding logic of the coder of Figure 1: and
Figure 3 is a block diagram of a decoder for decoding the encoded signal produced by the encoder of
Figure 1.
Considering firstly the encoder shown in Figure 1, a 16-bit binary word to be coded is supplied to an input latch L1. This is to be encoded and supplied as a 20-bit digital word to an output latch L2, in the form of two 10-bit blocks. The output word is subject to the condition that it always contains 10 binary ones and 10 binary zeroes, and each of the two 10-bit halves of the output word is subject to the conditions that it may not contain less than four or more than six binary ones, it may not contain more than five consecutive identical bits, and it may not contain more than three consecutive identical bits at the beginning or more than two consecutive identical bits at the end. There are 512 10-bit output blocks which conform to these properties.
This enables 9 bits of input data to be coded into the first 10-bit output block. This code set may be divided into two equal subsets each of 256 bits, and each of the ones-complement the other. Considering the whole codeset of 512, it is clear that any digit of an arbitrary word has an equal chance of being a "one" or a "zero".
Each subset could therefore be labelled (given the original codeset) by specifying its first digit as a "one" or a "zero".
Furthermore, considering an arbitrarily chosen input 9-bit block (which is free to have any value), any of its digits will have an equal chance of being "one" or a "zero". Thus the first digit of the first 9-bit block of input data may, in the coding process, become the first digit of the 10-bit output block of data. The remaining 8 bits of input data are coded into one of the subsets described above, using a programmable read only memory
PROM1, but omitting the first digit of the output word. The address inputs of the memory PROM1 are
connected to bits 2 to 9 inclusive of the input latch L1 and it has nine outputs a to i inclusive for coded output
data. In this way, one subset of output data is obtained from a subset of input data which may both be
labelled by the value of their first digit.The other possible output words (i.e. the other subset) are obtained
by inverting the previous subset of output data and will be obtained from those input words with the oppositely valued first digit. Thus input bit 1 is connected directly to bit 1 of the output latch L2, whilst the data outputs a to i inclusive of PROM1 are connected to bits 2 to 10 inclusive of the output latch via an
inverter 11 which is arranged to invert the output data whenever bit 1 is logic zero.
Having coded the first 10 bits of output data into either a 4:6, 5:5 or 6:4 word, the second 10-bit block has
been partially defined and must be either a 6:4,5:5 or 4:6 word respectively. The number of bits that may be coded into the second output block is therefore limited, and will be determined by the number of 10-bit words which conform to the code rule described above and have the property of being 4:6,5:5 or 6:4 words.
This is 154 for the 4:6 and 6:4 words. The number of 5:5 words is greater still and therefore does not impose
a limitation. This permits the coding of seven bits of input data into the second ten bits of output data.
The encoding of the second input block is carried out employing coding logic CL, a further programmable
read-only memory PROM2, and a parity generator PG. To reduce the required memory size, the first output
digit of the second output block (i.e. bit 10 of the input latch L1) is, in the manner described above, connected to the first bit of the output (i.e. bit 11 of the output latch L2). It will be appreciated that the second-stage
encoding arrangement needs to be informed of the number of binary ones already generated in the first 10
bits, and therefore PROM 1 has additional outputs, kwhich indicate the number of binary ones produced on
outputs a to i, and these, together with bit 1 of the first block supply the necessary information to the coding
logic CL. The coding logic CL is also supplied with the first bit of the second block, and produces, from these
inputs, a 2-bit word, (x, y) indicating the total number of binary ones or (zeros) in output bits 1 to 11 inclusive
(or alternatively, the number of binary ones which need to be supplied to bits 12 to 20 of the output latch L2).
The second read-only memory, PROM2, therefore has its address lines connected to these outputs from the coding logic and to bits 11 to 16 inclusive of the input latch L1, and supplies eight output bits to bits 12 to 19 inclusive of the output latch L2. There is no reason why the memory PROM2 should not also supply the last output bit (bit 20), but in order to reduce the memory size (particularly since 8-bit PROMS are readily available), the last bit is supplied by a parity generator PG whose inputs are connected to the outputs of
PROM2 and to a further outputz of the coding logic which indicates the parity of output bits 1 to 11 inclusive.
The coding logic is shown in more detail in Figure 2, and its truth table is given below.
1's:O's l's:O's
in bits Input Input Coding Logic Output
a-i PROM1 bit bit Output bits
PROM1 j k 10 1 x y z 12-20
0 0 0 0 1 4:5
3:6 1 0 0 1 1 1 1 6:3
1 0 1 0 0 3:6
1 1 0 1 0 5:4
0 0 0 1 0 5:4
4:5 0 0 0 1 0 1 0 5:4
1 0 0 0 1 4:5
1 1 0 0 1 4:5
0 0 1 1 1 6:3
5:4 0 1 0 1 0 0 1 4:5
1 0 0 1 0 5:4
1 1 1 0 0 3:6
The coder output may be converted into serial form by a suitable serial-to-parallel converter (not shown).
Figure 2 shows a decoder for decoding a 20-bit word encoded by the apparatus of Figure 1. The decoding operation is considerably simpler than coding. The two 10-bit blocks are fed from an input latch L3 to two 512 x 8-bit programmable read-only memories, PROM3 and PROM4, the first digit of each block being fed directly to its position in a 16-bit output latch L4, and not being connected to the PROMs. The 8-bit output of
PROM3 and the 6-bit output of PROM4 represents the remainder of the decoded 16-bit word. In connection with PROM3, it may be noted that no attempt is made to compensate the inversion of bits 2 to 10 of the encoded input, PROM3 being programmed so that a given word applied to its address lines and the complement of that word both produce the same data output.
Figure 2 also shows a parity checking unit PC connected to the input: this could be a full scale code rule violation checking device if desired. A more economical way of checking for invalid codes is to sacrifice one of the output codes from each of the two memories PROM3 and PROM4 (for example all 1's or all 0's) and program the PROMs to produce this code when an invalid code is received: this can then be detected by an error code detector ED. This of course would result in a reduction in the data-handling capacity of the system.
The input to the coder of Figure 3 may of course be supplied by a serial to parallel converter.
The described alternative 20:16 code can be compared favourably to existing codes, for example that described in UK patent application No.7829935 (Serial No. 2001789A) which describes a 10:8 channel code in which the 10-bit encoded word is constrained to have five 1's and five 0's thus providing 252 possible code words.
The alternative 20:16 code described provides that, in a coded serial data stream, a transition is guaranteed to occur at least every five bit-celis, compared with every ten bit-cells for the 10:8 code.
Secondly, use of the code permits (using suitable checking circuitry) detection of all single bit errors and 93% of all other error patterns, compared with the 10:8 code where detection of all single bit errors but only 75% of other errors is possible. Thirdly, there exist valid 20-bit code words which are distinguishable from any notional 20-bit words taken from the serial coded to data stream in any bit phase. These words may be regarded as lying outside the 16-bitcodesetofthe 20:16 code, and, because of their unique properties, are extremely valuable forframing and synchronising functions. The 10:8 code does not include similar words.
Claims (23)
1. An encoder for converting an input binary word having a plurality of bits into an output binary word having a greater number of bits, comprising first coding means responsive, in use, to a first input group consisting of only some of the input bits to produce a first group of output bits and second coding means responsive, in use, to a second input group consisting of the remaining input bits and to outputs of the first coding means and/or the said first group of input bits to produce a second group of output bits.
2. An encoder according to claim 1, arranged for converting a sixteen-bit input binary word into a twenty-bit output binary word.
3. An encoder according to claim 1 or 2, arranged in operation to produce, in response to each input bit combination, a respective output word, all of which output words have a predetermined number of binary ones and zeroes.
4. An encoder according to claim 1, 2 or 3, in which each of the said output words has an equal number of ones and zeroes.
5. An encoder according to claim 4, in which the two output groups have the same number of bits.
6. An encoder according to claim 5, in which, in each output word, the difference between the number of binary ones in the first group of bits and the number of binary ones in the second group of bits is not more than two.
7. An encoder according to any one of the preceding claims in which the number of consecutive identical bits in each output word is less than a predetermined limit, and the numbers of consecutive identical bits at the beginning and at the end of the word are not more than respective ones of a pair of predetermined numbers the sum of which is equal to the said predetermined limit whereby the number of successive identical bits which can occur in a serial data transmission of successive output words does not exceed the said predetermined limit.
8. An encoder according to claim 7, in which the numbers of consecutive identical bits at the end of the first output group and at the beginning of the second output group are not more than respective ones of a pair of predetermined numbers the sum of which is equal to the said predetermined limit.
9. An encoder according to claim 8, in which the second coder means is arranged to receive signals from the first coder means indicating the number of binary ones in the first group.
10. An encoder according to claim 9, in which the first coder means comprises a read only memory having inputs arranged to receive all but one of the said group of input bits, followed by an inverter controlled by the remaining bit thereof, the said remaining bit and the outputs of the inverterforming the first group of input bits.
11. An encoder according to claim 10 in which the second coder means comprises coding logic responsive in use to outputs of the first coder means, and said remaining bit of the first input group, which together provide the said signal indicating the number of binary ones in the first group, and to a first bit of the second input group to produce outputs indicating the total number of binary ones in the first input group and the said first bit, and further coding means responsive to the coding logic outputs and to the remaining bits of the second input group, the said first bit of the input group and the outputs of the further coding means forming the second group if output bits.
12. An encoder according to claim 11 in which the further coding means comprises a second read-only memory responsive to all but one of the said remaining bits of the second input group to produce all but one of the outputs of the second coder means, and a parity generator responsive to the output of the second read-only memory and to a signal indicating the parity of the other output bits to produce the remaining output bit of the second group.
13. An encoder according to any one of claims 7 to 12 when dependent on claim 2, in which the said predetermined limit is five.
14. An encoder according to claim 13, in which the numbers ofthe said pair are two and three.
15. An encoder according to any one of the preceding claims including a parallel to serial converter connected to convert the output word thereof into bit-serial form.
16. An encoder for converting an input binary word having a plurality of bits into an output binary word having a greater number of bits, substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.
17. A method of coding digital data in which an input binary word having a plurality of bits is converted into an output word having a greater number of bits, comprising generating in response to each input bit combination, a respective output word, wherein:
(a) each of the said output words has a predetermined number of binary ones and zeroes;
(b) the number of consecutive identical bits in each output word is not more than a predetermined limit; and
(c) the numbers of consecutive identical bits at the beginning and end of the output word are not more than respective ones of a pair of predetermined numbers the sum of which is equal to the said predetermined limit, whereby the number of successive identical bits which can occur in a serial data transmission of successive output words does not exceed the said predetermined limit.
18. A method according to claim 17 in which each of the said output words has an equal number of binary ones and zeroes.
19. A method according to claim 18 in which the number of binary ones in each half of the output word does not differ by more than two.
20. A method according to claim 19 in which the input and output binary words have respectively sixteen and twenty bits and the said predetermined limit is five.
21. A method according to claim 20 in which the said predetermined limit is four.
22. A method according to claim 21 in which the number of consecutive identical bits at the end of the first half and the beginning of the second half of the output word are not more than respective predetermined numbers the sum of which is equal to the said predetermined limit.
23. A method according to claim 15 substantially as hereinbefore described.
23. A method according to claim 17 substantially as hereinbefore described.
New claims or amendments to claims filed on 8 Nov 82.
Superseded claims 1 to 23.
New or amended claims:
1. An encoder for converting an input binary word having a plurality of bits into an output binary word having a greater number of bits, comprising first coding means responsive, in use, to a first input group consisting of only some of the input bits to produce, independently of the values of the remaining input bits, a first group of output bits and second coding means responsive, in use, to a second input group consisting of the remaining input bits and to outputs of the first coding means and/or the said first group of input bits to produce a second group of output bits, the coding means being arranged in operation to produce, in response to each input bit combination, a respective output word, all of which output words have a predetermined number of binary ones and zeroes.
2. An encoder according to claim 1, arranged for converting a sixteen-bit input binary word into a twenty-bit output binary word, in which the first and second groups of input bits consist of nine and seven bits respectively, and the first and second groups of output bits each consist of ten bits.
3. An encoder according to claim 2, in which each of the said output words has an equal number of ones and zeroes.
4. An encoder according to claim 3, in which, in each output word, the difference between the number of binary ones in the first group of bits and the number of binary ones in the second group of bits is not more than two.
5. An encoder according to any one of the preceding claims in which the number of consecutive identical bits in each output word is not more than a predetermined limit, and the numbers of consecutive identical bits at the beginning and at the end of the word are not more than respective ones of a pair of predetermined numbers the sum of which is equal to the said predetermined limit whereby the number of successive identical bits which can occur in a serial data transmission of successive output words does not exceed the said predetermined limit.
6. An encoder according to claim 5, in which the numbers of consecutive identical bits at the end of the first output group and at the beginning of the second output group are not more than respective ones of a pair of predetermined numbers the sum of which is equal to the said predetermined limit.
7. An encoder according to claim 5 or 6, when dependent on claim 2, in which the said predetermined limit is five.
8. An encoder according to claim 7, in which the numbers of the said pair are two and three.
9. An encoder according to any one of the preceding claims, in which the second coder means is arranged to receive signals from the first coder means indicating the number of binary ones in the first group.
10. An encoder according to claim 9, in which the first coder means comprises a read only memory having inputs arranged to receive all but one of the said group of input bits, followed by an inverter controlled by the remaining bit thereof, the said remaining bit and the outputs of the inverter forming the first group of output bits.
11. An encoder according to claim 10, in which the second coder means comprises coding logic responsive in use to outputs of the first coder means, and said remaining bit of the first input group, which together provide the said signal indicating the number of binary ones in the first group, and to a first bit of the second input group to produce outputs indicating the total number of binary ones in the first input group and the said first bit, and further coding means responsive to the coding logic outputs and to the remaining bits of the second input group, the said first bit of the input group and the outputs of the further coding means forming the second group of output bits.
12. An encoder according to claim 11, in which the further coding means comprises a second read-only memory responsive to all but one of the said remaining bits of the second input group to produce all but one of the outputs of the second coder means, and a parity generator responsive to the output of the second read-only memory and to a signal indicating the parity of the other output bits to produce the remaining output bit of the second group.
13. An encoder according to any one of the preceding claims including a parallel to serial converter connected to convert the output word thereof into bit-serial form.
14. An encoder for converting an input binary word having a plurality of bits into an output binary word having a greater number of bits, substantially as hereinbefore described with reference to Figure 1 of the accompanying drawings.
15. A method of coding digital data in which an input binary word having a plurality of bits is converted into an output word having a greater number of bits by generating, in response to each input bit combination, a respective output word, all of which output words have a predetermined number of ones and zeroes, comprising, in dependence on a first input group consisting of only some of the input bits, generating, independently of the values of the remaining bits, a first group of output bits and, in dependence on a second input group consisting of the remaining input bits and on the first group of input bits, generating a second group of output bits.
16. A method according to claim 15 in which the input and output binary words have respectively sixteen and twenty bits, the first and second groups of input bits consist of nine and seven bits respectively and the first and second groups of output bits each consist of ten bits.
17. A method according to claim 16 in which each of the said output words has an equal number of binary ones and zeroes.
18. A method according to claim 17, in which, in each output word, the difference between the number of binary ones in the first group of bits and the number of binary ones in the second group of bits is more than two.
19. A method according to any one of the preceding claims, in which the number of consecutive identical bits in each output word is not more than a predetermined limit, and the numbers of consecutive identical bits at the beginning and end of the word are not more than respective ones of a pair of predetermined numbers the sum of which is equal to the said predetermined limit, whereby the number of successive identical bits which can occur in a serial data transmission of successive output words does not exceed the said predetermined limit.
20. A method according to claim 19, in which the number of consecutive identical bits at the end of the first output group and the beginning of the second of the output group are not more than respective ones of a pair of predetermined numbers the sum of which is eqqual to the said predetermined limit.
21. A method according to claim 21 or 22, when dependent on claim 18, in which the said predetermined limit is five.
22. A method according to claim 23 in which the numbers of the said pair are two and three.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08127791A GB2109200B (en) | 1981-09-15 | 1981-09-15 | Digital data encoding |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB08127791A GB2109200B (en) | 1981-09-15 | 1981-09-15 | Digital data encoding |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| GB2109200A true GB2109200A (en) | 1983-05-25 |
| GB2109200B GB2109200B (en) | 1985-07-03 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB08127791A Expired GB2109200B (en) | 1981-09-15 | 1981-09-15 | Digital data encoding |
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|---|---|
| GB (1) | GB2109200B (en) |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2131656A (en) * | 1982-12-06 | 1984-06-20 | Western Electric Co | Dc cancellation in ternary-coded data systems |
| FR2551277A1 (en) * | 1983-08-29 | 1985-03-01 | Sony Corp | METHOD AND APPARATUS FOR CONVERTING DIGITAL DATA |
| EP0275585A1 (en) * | 1986-12-12 | 1988-07-27 | Optical Storage International Holland | Method of transmitting n-bit information words, information transmission system for carrying out the method, and encoding device and decoding device for use in the information-transmission system |
| EP0348805A2 (en) * | 1988-06-27 | 1990-01-03 | Deutsche Thomson-Brandt GmbH | Transmission system with a transmission code for binary data |
| EP0426033A2 (en) * | 1989-10-31 | 1991-05-08 | Sony Corporation | Digital modulating apparatus and digital demodulating apparatus |
-
1981
- 1981-09-15 GB GB08127791A patent/GB2109200B/en not_active Expired
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2131656A (en) * | 1982-12-06 | 1984-06-20 | Western Electric Co | Dc cancellation in ternary-coded data systems |
| FR2551277A1 (en) * | 1983-08-29 | 1985-03-01 | Sony Corp | METHOD AND APPARATUS FOR CONVERTING DIGITAL DATA |
| EP0275585A1 (en) * | 1986-12-12 | 1988-07-27 | Optical Storage International Holland | Method of transmitting n-bit information words, information transmission system for carrying out the method, and encoding device and decoding device for use in the information-transmission system |
| US4855742A (en) * | 1986-12-12 | 1989-08-08 | Optical Storage International Holland | Method of transmitting n-bit information words, information transmission system for carrying out the method, and encoding device and decoding device for use in the information-transmission system |
| EP0348805A2 (en) * | 1988-06-27 | 1990-01-03 | Deutsche Thomson-Brandt GmbH | Transmission system with a transmission code for binary data |
| EP0348805A3 (en) * | 1988-06-27 | 1990-09-05 | Deutsche Thomson-Brandt GmbH | Transmission system with a transmission code for binary data |
| EP0426033A2 (en) * | 1989-10-31 | 1991-05-08 | Sony Corporation | Digital modulating apparatus and digital demodulating apparatus |
| EP0426033A3 (en) * | 1989-10-31 | 1992-01-22 | Sony Corporation | Digital modulating apparatus and digital demodulating apparatus |
| US5155485A (en) * | 1989-10-31 | 1992-10-13 | Sony Corporation | Digital modulating apparatus and digital demodulating apparatus |
Also Published As
| Publication number | Publication date |
|---|---|
| GB2109200B (en) | 1985-07-03 |
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| PCNP | Patent ceased through non-payment of renewal fee |
Effective date: 19930915 |