JP3273580B2 - Data modulation method, data modulation device, recording medium, data demodulation method, and data demodulation device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data modulation method and a data modulation method.
Modulator, recording medium, data demodulation method, and data
With respect to a demodulation device , in particular, a data modulation method and a data modulation method that are suitable for use in a case where data is modulated so as to be suitable for data transmission and recording on a recording medium, and a modulation code obtained by the modulation is demodulated to reproduce data. Equipment, recording media, data
The present invention relates to a data demodulation method and a data demodulation device .

[0002]

2. Description of the Related Art When transmitting data or recording data on a recording medium such as a magnetic disk or an optical disk, for example,
The data is modulated so as to be suitable for transmission and recording. A block code is known as one of such modulation codes. In this block code, a data sequence is divided into units of m × i bits (hereinafter, referred to as data words), and the data words are converted into code words of n × i bits according to an appropriate coding rule. . This code is
When i = 1, the code becomes a fixed length code. When a plurality of i can be selected, that is, when i ≧ 1, the code becomes a variable length code. This block-coded code is a variable-length code (d, k;
m, n; r).

Here, i is called a constraint length, and a maximum constraint length i _max is r (hereinafter, referred to as a maximum constraint length r). Also, d indicates the minimum number of consecutive identical symbols, that is, a so-called minimum run of, for example, 0, and k indicates the maximum number of consecutive identical symbols, that is, a maximum run of, for example, 0.

When the variable-length code obtained as described above is recorded on, for example, an optical disk or the like, the variable-length code is further converted into a so-called NRZI (Non Return to Zero Inv).
erted), and performs recording based on a NRZI-modulated variable-length code (hereinafter, referred to as a recording waveform sequence). The data recorded on the recording medium is N
RZI demodulation is performed, and a variable length code is decoded to restore the original data.

That is, a procedure for recording data on a recording medium and reproducing the data is sequentially performed as shown in FIG.

By the way, the minimum inversion interval of the recording waveform sequence is T
_When the maximum inversion interval is _Tmax and the maximum inversion interval is _Tmax , it is preferable that the minimum inversion interval _Tmin is longer, that is, the minimum run d is larger from the viewpoint of the recording density. Also, from the viewpoint of clock reproduction and so-called jitter, the maximum inversion interval T _max
Is preferably short, that is, the maximum run k is preferably small. Further, the detection window width T _W (= the jitter tolerance value)
(M / n) × T) is also preferably large (T is a bit interval). That is, it is preferable that the conversion ratio (m / n) is large.

In order to evaluate various modulation methods, the product of the minimum inversion interval T _min and the detection window width T _W (= T _min × T _W ) is used. It can be said that a larger value is a more preferable modulation method.

Table 1 shows (1, 7) RLL used for the magnetic disk, and (2, 7) RLL modulation method.
EF used for optical recording of compact discs
It shows the characteristics of the modulation method of M (Eight to Fourteen Modulation).

[0009]

[Table 1]

As shown in Table 1, the minimum inversion interval T
The value of the product of _min and the detection window width T _W is (1, 7) RLL is 0.
89 is the largest, then (2,7) RLL is 0.75, and EFM is the smallest, 0.66.

As described above, even if (1,7) RLL has the largest value of T _min × T _W , the value is 0.9 or less, which is close to the theoretical limit value 1.0 of the NRZI system. is there. In addition, there is a limit in producing a high-efficiency conversion table, and it is difficult to expect a large increase in recording density and recording speed by this method.

[0012]

As described above, in order to record more data on a recording medium by a modulation method in which the recording density cannot be increased in principle, a recording medium itself such as a disk or a cassette tape must be enlarged. It is necessary to increase the recording speed. However, if the size of the recording medium is increased, the size of the recording / reproducing apparatus is also increased. Further, there is a physical or mechanical limit in increasing the relative speed between the recording medium and the head.

The present invention has been made in view of such a situation, and enables higher-density recording.

[0014]

According to the data modulation method of the present invention, a code word is represented by N-value data (N is 3 or more),
If the maximum or minimum number of consecutive
At least one has a limit, and the maximum constraint length r is set.
Characterized in that it is.

In the variable length coding, the constraint length i is determined,
Based on the conversion table selected according to the judgment result
That can be done.

The code word is an indeterminate code having an indeterminate bit.
No. can be included.

Variable-length coding is a method in which a data word is binarized once.
Convert to N-valued codeword after converting to N-ary representation
can do.

The code word is signal level at logic level 0.
When the logic level does not change and the logic level is 1, 2, ..., N
First, the change in the signal level in the larger direction is the first priority.
And a change to a closer signal level is defined as a second priority.
And sequentially assigned to a predetermined signal level change,
It can be represented as a signal.

According to the data modulation apparatus of the present invention, the code word is N
Value data (N is 3 or more)
At least one of the large continuous number and the minimum continuous number
And a maximum constraint length r is set.
I do.

According to the recording medium of the present invention, the code word has N-value data.
(N is 3 or more) and the maximum continuation of the same symbol
Restrictions on at least one of the number and the minimum number of continuous
And the maximum constraint length r is set.

According to the data demodulation method of the present invention, when the code word is N
Value data (N is 3 or more)
At least one of the large continuous number and the minimum continuous number
And a maximum constraint length r is set.
I do.

In the data demodulation device of the present invention, the code word is N
Value data (N is 3 or more)
At least one of the large continuous number and the minimum continuous number
And a maximum constraint length r is set.
I do.

[0023]

[0024]

[0025]

[0026]

The data modulation method, the data modulation device,
In a recording medium, a data demodulation method, and a data demodulation device , a codeword is represented by N-value data (N is 3 or less).
Above), maximum or minimum number of consecutive identical symbols
Has a limit on at least one of
Is set. Therefore, higher density can be achieved.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, the present invention is applied to a modulator for converting data into a variable length code (d, k; m, n; r) and a demodulator for performing the reverse conversion.
FIG. 2 is a block diagram showing a specific circuit configuration of the modulation device.

As shown in FIG. 1, the modulation device converts the input binary data into m-bit units (in the case of the embodiment shown in FIG.
= 3, m = 1 in the case of the embodiment of FIG. 3, and m = 2) in the case of the embodiment of FIG. 4, and the constraint length of data supplied in m-bit units from the shift register 11 It has an encoding processing circuit 12 that determines i (i = 1 to r) and detects data to be converted into a code including an uncertain bit (hereinafter, referred to as an uncertain code). The conversion table (ROM) 14 _i stores binary data having a basic data length of m bits and variable-length codes (d, k; m, n; r) of N values (N ≧ 3) having a basic code length of n bits. (A specific example thereof will be described later with reference to FIGS. 2 to 4, but in these examples, a conversion table for converting binary data into data of a binary-coded ternary representation.) I remember.

The multiplexer 15 includes a conversion table 14
The code from _i is synthesized and supplied to the buffer memory 17. The buffer memory 17 temporarily stores the variable length code from the multiplexer 15. The level converter 18 converts the binary-coded ternary representation data supplied from the buffer memory 17 into N-value (ternary in the case of the embodiment) data and outputs it. The uncertain level processing circuit 16 includes a multiplexer 15
, An indeterminate bit (“11” in FIG. 4) is detected, and a detection signal is output to the level converter 18. The clock generation circuit 19 supplies a clock to the buffer memory 18 and the like.

In the present embodiment, binary data is converted into ternary data and output. In the conversion table _14i , binary data is converted into binary-coded ternary data. Is done. 2 to 4 show examples of tables stored in the conversion table _14i .

In the embodiment of FIG. 2, the variable length code (d, k; m, n; r) is (0, 2, 3, 2, 1). Then, the 3-bit binary data “000” to “111” is converted into ternary (ternary) data. The binary data “001” to “111” are
The ternary data “01” to “21” are sequentially associated. However, in order not to use “00” as ternary data, “22” is used as ternary data corresponding to binary data “000”.

Further, since it is difficult to store the ternary data in the memory, the ternary data is converted into a binary-coded ternary representation according to the principle shown in Table 2.

[0033]

[Table 2]

That is, the ternary data "0", "1", "
"2" is a binary ternary representation, "00", "0"
It is set to 1 "or" 10. "The uncertain bit" * "of the ternary data is set to" 11 "in a binary-coded ternary representation.

Therefore, as shown in FIG.
The data “01” through “21” are represented by “00 01” through “1001” in a binary-coded ternary representation. Further, the ternary data “22” is represented by a binary ternary expression “1”.
0 10 ".

In the embodiment of FIG. 3, the variable length code (d, k; m, n; r) is (1, ∞; 1, 1; 2). In this embodiment, 2-bit binary data "11", "10", "01" correspond to ternary data "10", "20", "00", respectively.
The 3-bit binary data “001” and “000” correspond to the ternary data “010” and “020”, respectively. In addition, the ternary data is expressed as 2 according to the principle of Table 2.
It is made to be represented by an evolutionary ternary expression.

Further, in the embodiment of FIG. 4, the variable length codes (d, k; m, n; r) are (3, 8; 2,
3; 3). 2-bit binary data "11"
And "10" are ternary data "100" and "2", respectively.
00 ". The 2-bit binary data" 01 "corresponds to the ternary data" 00 * ". This" * "represents an indefinite bit. ing.

Further, 4-bit binary data "001"
1 "," 0010 "," 0001 "are ternary data"
010000 "," 020000 "," 002000 "
And 6-bit binary data "
0000011 ”,“ 000010 ”,“ 00000 ”
1 "," 000000 "is ternary data" 01000 "
1000 "," 0100002000 "," 020001
000 "and" 020002000 ", respectively, and these ternary data are expressed in a binary-coded ternary representation in accordance with the principle of Table 2 as in the case described above. Thus, the uncertain bit “*” is
In the binary-coded ternary representation, it is "11".

For example, in the table of the embodiment of FIG.
The conversion table corresponding to i = 1 is the conversion table 14 ₁
Stored in, the conversion table corresponding to the i = 2, is stored in the conversion table 14 _2, the conversion table corresponding to the i = 3, it is stored in the conversion table 14 _3.

Next, the operation will be described. Now
The conversion table 14 _i is assumed to conversion table shown in FIG. 4 are stored.

In the shift register 11, for example, so-called predictive coding, discrete cosine transform (DC)
T), data obtained by performing data compression processing such as Huffman coding is supplied. The shift register 11 shifts the supplied data in units of 2 bits and supplies the data to the encoding processing circuit 12.

The encoding processing circuit 12 determines the constraint length i of data supplied in units of 2 bits. Specifically, the encoding processing circuit 12, the data supplied by the 2-bit unit, whether present in the data portion of the 2-3 conversion table shown in FIG. 4 (a conversion table 14 ₁₎ (left column) Is determined. That is, data "11", "10", "0"
When the value is "1", the constraint length i is determined to be 1, and when the data is "00", the next two bits are added to make the four bits (turn to the next rank).

Next, the encoding processing circuit 12 determines whether or not the data having a total of 4 bits corresponds to the data portion of the 4-6 conversion table (conversion table 14 ₂ ) shown in FIG. That is, data “0011”, “001”
When it is 0 "or" 0001 ", the constraint length i is determined to be 2, and when it is data" 0000 ", it is passed to the next rank.

In the same manner, the encoding processing circuit 12
Determines whether the data supplied in 2-bit units from the shift register 11 exists in the data portion of the 6-9 conversion table (conversion table 14 ₃ ) shown in FIG. It is determined whether or not there is.

Next, the selector 13 selects a conversion table 14 _i based on the constraint length i supplied from the encoding processing circuit 12, and the selected conversion table 14 _i
X i bits of data are supplied.

To be more specific, the selector 13 has, for example, i =
When the value is 1, the conversion table 14 _i is selected, and the selected conversion table 14 _i contains 2-bit data “11”, “2”.
10 "and" 01 "are supplied.

Further, for example when the i = 2 selects the conversion table 14 _2, the conversion table 14 ₂ that this selection, 4
Bit data “0011”, “0010”, “000”
1 "supplies. Furthermore, i = 3 when the select conversion table 14 _3, there 6-bit data" 00001
1 "," 0000010 "," 000001 "," 000
000 ".

The conversion table 14 ₁ to 14 _3, as described above, FIG. 4, respectively 2-3 conversion table, 4-6 conversion table has a 6-9 conversion table, the selector 13
For example, a code stored in the storage unit as a read address is read out from the data supplied via.

As a result, for example, if the data is "11", "1"
0 "," 01 ", the from the conversion table 14 _1, the sign of the binary coded ternary representation" 01 00 00 "," 10 00
00 or an indefinite code “00 00 11”, for example, if the data is “0011”, “001”
0 "," when 0001 ", from the conversion table 14 _2,
Code of binary ternary representation “00 01 00 00 0”
0 ”,“ 00 10 00 00 00 ”or“ 00 ”
00 00 00 00. Further, for example, the data is “000011”, “000010”, “0”.
00001 "," 000000 ", the from the conversion table 14 _3, 2 Evolution 3 binary representation of the code" 0001 00
00 00 01 00 00 "," 00 01 00
0000 10 00 00 "," 00 10 00
00 00 01 00 00 "," 00 10 0
0 00 00 10 00 00 "is output.

That is, these conversion tables 14 _{1 to} 1
From 4 _3, variable length code of binary coded ternary representation is output,
This variable length code is supplied from the buffer memory 17 to the level converter 18. When detecting the uncertain bit “11” from the output of the multiplexer 15, the uncertain level processing circuit 16 supplies a detection signal to the level converter 18.

The level converter 18 receives the input binary 3
The ternary representation data is converted to ternary representation (ternary) data. For this reason, the level converter 18 also has a built-in conversion table (ROM) (for converting binary-coded ternary data into ternary data) similar to the case shown in FIGS.

Therefore, for example, in this case, the data "01 00 00", "10" of the binary-coded ternary representation shown in FIG.
When "00 00" is input, the ternary data "10
0 "and" 200 "are output.

Further, the data "00 0" of the binary-coded ternary representation.
When "0 11" is input, the uncertain level processing circuit 1
From 6, an uncertain bit detection signal is input to the level converter 18. At this time, the level converter 18 detects the next 2-bit data, and outputs the ternary data "001" when the 2-bit data is "00". When "01", ternary data "
000 "is output.

Further, data "00" of binary-coded ternary representation
01 00 00 00 "," 0010 00 00
00 "," 00 00 10 00 00 "," 00
01 00 00 00 01 01 00 00 "," 00
01 00 00 0010 00 00 "," 0
0 10 00 00 00 01 00 00 ","
00 10 00 00 00 10 00 00 ”is input, the corresponding ternary data“ 01000 ”is input.
0 "," 020000 "," 002000 "," 010
001000 "," 0100002000 "," 0200 "
01000 "and" 020002000 "are output.

As described above, the code output from the level converter 18 is output as a modulation code at a predetermined transfer rate.

The modulation code is added with, for example, an error correction code, a synchronization signal, and the like in a so-called ECC circuit (not shown), and is recorded on a recording medium such as a magnetic disk, a magnetic tape, an optical disk, or transmitted. Sent over the road.

Next, referring to FIG. 5 and FIG.
) And the level of the recording signal (transmission signal).

As shown in FIG. 5, the binary NRZI signal has a logic assigned to a change in level. That is,
When the signal level does not change at 1 or 0, NRZI
The sign of the signal is set to 0. On the other hand, when the level changes from level 1 to level 0, or conversely, from level 0 to level 1, the sign of the NRZI signal is 1.

The ternary data 0 and the assignment to the level are such that the ternary data 0 corresponds to a state in which the level does not change so that the basic concept is the same as in the case of the ternary data. Of these, 1 and 2 correspond to level changes. Then, a change to a higher level is defined as a first priority, and a change to a closer level is defined as a second priority.

That is, level 1, level 2, or level 0
In, when the level does not change, the logic is set to 0. In contrast, a logic 1 is assigned to a change from level 1 to a higher level, level 2, and a logic 1 is assigned to a change from level 1 to a lower level, level 0. 2 is assigned.

A change in level from level 2 to a lower level, ie, level 1 which is a closer level
To a change to level 0, a logic 1 is assigned, and to a farther level, level 0, a logic 2 is assigned. In addition, a logic 1 is assigned to a change from level 0 to a higher level, that is, a closer level 1, and a logic 2 is assigned to a change to a farther level, level 2. Is assigned.

By allocating the ternary logic in this way, it is possible to perform processing using the same concept as in the case of binary.

Next, an embodiment of the demodulation device will be described with reference to FIG. As shown in FIGS. 2 to 4, this demodulation device has a level conversion table having a conversion table for converting ternary data into data of a binary-coded ternary representation (an inverse conversion table for converting data in the reverse of the case of FIG. 1). The container 31 is provided. The data converted to the binary-coded ternary representation by the level converter 31 is supplied to the constraint length determination circuit 32 and the PLL circuit 37, respectively.

The constraint length determination circuit 32 includes a level converter 31
, The constraint length i is determined and output to the selector 33. The selector 33 supplies the data of the binary-coded ternary representation also supplied from the constraint length determining circuit 32 to _one of the conversion tables 34 _{1 to} 34 _r corresponding to the constraint length i from the constraint length determining circuit 32. It has been made to be.

The conversion tables 34 _{1 to} 34 _r store conversion tables for converting the data of the binary-coded ternary representation into binary data, as in the cases shown in FIGS. 2 to 4. .

The multiplexer 35 includes a conversion table 34
_The data supplied from _{1 to} 34 _r are combined and output to the buffer memory 36. The buffer memory 36 is supplied with a clock generated by the PLL circuit 37.

Next, the operation will be further described. First, when ternary data is input, the level converter 31 converts the data into binary-coded ternary data. For example, when ternary data “100” and “200” are input, these are converted into binary ternary representation data “01 00 00” and “10 00 00”. In addition, ternary data “000” or “00”
When "1" is input, it is converted into binary-coded ternary representation data "00 00 11".

Further, the ternary data "01000"
0 "," 020000 "," 002000 "," 010
001000 "," 0100002000 "," 0200 "
When “01000” and “020002000” are input, data “00” of the binary-coded ternary representation is correspondingly input.
01 00 00 00 "," 00 10 00 0
000 "," 00 00 10 00 00 "," 00
01 00 00 0001 00 00 "," 00
01 00 00 00 10 00 "," 00 1
00 00 00 00 01 00 "," 00 10
00 00 0010 00 00 "is output.

The constraint length determination circuit 32 includes a level converter 31
The constraint length i of the binary-coded ternary representation data supplied from is determined.

The selector 33 selects a conversion table 34 _i based on the constraint length i from the constraint length determination circuit 32,
The selected conversion table 34 _i is supplied with a binary-coded ternary representation variable length code.

More specifically, the selector 33 outputs, for example, i =
When 1, select the conversion table 34 _1, the conversion table 34 ₁ that this selection, the 6-bit code "01 00
00 ”,“ 10 00 00 ”or“ 00 00 1 ”
1 ".

For example, when i = 2, the selector 3
3 selects the conversion table 34 _2, the conversion table 34 ₂ that this selection, the 10-bit code "00 01 0
000 00 "," 00 10 00 00 00 "or" 00 00 1000 00 ".

[0073] In the same manner, the selector 33, when the constraint length i is 3, and selects a conversion table 34 _3, the conversion table 34 ₃ selected supplies 16-bit code.

[0074] conversion table 34 _1, 34 _2, 34 _3, as described above, each 6-2 conversion table 10-4
It has a conversion table and a 16-6 conversion table, and reads the data of the data portion shown in FIGS. 2 to 4 using the code supplied via the selector 33 as, for example, a read address.

As a result, for example, the code is “01 00 0”
0 ”,“ 10 00 00 ”or“ 00 00 1 ”
", The data from the conversion table 34 _1" 1 1
1 "," 10 "or" 01 "is output.

Further, for example, the code is “00 01 00”.
00 00 "," 00 10 0000 00 "," 0
0 00 10 00 00 ”, the conversion table 3
4 ₂ from the data "0011", "0010", "000
1 "is output.

For example, the code is “00 01 00 00”.
00 01 00 "," 00 0100 00 00
10 00 "," 00 10 00 00 00 00 01
00 00 "," 00 10 00 00 00 00 10
", The conversion table 34 ₃ from the data" 00 00 000011 "," 000010 "," 00000
1 "," 000000 "is output.

That is, these conversion tables 34 _{1 to} 34 3
From 4 _r , the 3 × i-bit variable-length code is inversely converted into 2 × i-bit data and output, and these data are supplied to the multiplexer 35.

The multiplexer 35 multiplexes the data supplied from the conversion tables 34 _{1 to} 34 _r , respectively.
The data is supplied to the buffer memory 36 as serial data.

On the other hand, the PLL circuit 37 reproduces a clock based on the variable length code and supplies the reproduced clock to the buffer memory 36.

The buffer memory 36 includes the multiplexer 3
5 is stored once, and the PLL circuit 37
The stored data is output as reproduction data at a predetermined rate according to the clock supplied from. The output data is subjected to data processing such as inverse DCT and predictive decoding, and is reproduced as a video signal.

Thus, the demodulation apparatus detects a code including an uncertain bit, determines the constraint length i of the variable length code based on the detection result, and converts the variable length code of n × i bits to m × i bits. By inversely converting the variable-length code into data based on the constraint length i by the inverse conversion table for inversely converting the data into the data, the variable-length code including the uncertain code can be demodulated into the data.

Table 3 shows the detection window width T _W , the minimum inversion interval T _min , and the maximum inversion interval T of the variable length code shown in FIGS.
_max and the product T of the minimum inversion interval T _min and the detection window width T _W
min × T _W.

[0084]

[Table 3]

As shown in Table 3, these values of the variable length code T (0,2; 3,2; 1) shown in FIG. 2 (T in this case represents three values) are as follows: 1.5T, 1.
5T, 4.5T, and 2.25. Further, in the variable length code T (1, ∞; 1,1; 2) shown in FIG. 3, they are 1.0T, 2.0T, ∞, 2.0. Further, the variable length code T (3,8; 2,3;
In 3), 0.67T, 2.66T, 6.0T,
It is 1.78. Any product T _min × T _W also the minimum inversion interval T _{mi n} and the detection window width T _W is seen to have a large value of 1 or more.

FIG. 8 shows the flow of processing when data is transmitted (recorded / reproduced) in this embodiment. As shown in the figure, the binary data is encoded into a variable length code according to the conversion tables shown in FIGS.
This variable length code is represented by a binary-coded ternary representation. As a result, a normal ROM or the like can be used as the conversion table. Then, the binary-coded ternary representation data is further converted to ternary data (ternary representation data). Then, the ternary data is recorded on a recording medium or transmitted to a transmission path.

The data reproduced from the recording medium or the data received from the transmission line is ternary data. This ternary data is converted to binary ternary data. Then, the data in the binary-coded ternary representation is decoded and converted into the original binary data.

In the above embodiment, the binary data is
Although the data is converted to value data, it is also possible to convert the data to quaternary data.

FIG. 9 shows an example of the correspondence between four values from 0 to 3 and a change in signal level. Also in this example, of the four-valued logic of 0 to 3, logic 0 is assigned to a state where the level does not change, and logics 1 to 3 are assigned to level change. Also in this case, a level change in a larger direction is set as a first priority, and a change to a closer level is set as a second priority, and logics 1 to 3 are sequentially assigned.

Therefore, for example, if there is no change at level 2, the logic is set to 0, and a change from level 2 to level 3, which is a larger level, is assigned a logic 1. Then, for a change from level 2 to a smaller level, level 1 or level 0, a change to level 1 which is a closer level, logic 2
Is assigned, and a logic 3 is assigned to a change to the farther level, level 0.

In the state where the level does not change at the level 3, the logic 0 is assigned, and when the level changes to the level 2, the level 1 or the level 0 which is smaller than the level 3, the logic 1 to the level 1 are arranged in the order of the closer level. Logic 3 is assigned. That is, logic 1 is assigned to a change from level 3 to level 2, logic 2 is assigned to a change to level 1, and logic 3 is assigned to a change to level 0.

A logic 0 is assigned to a state that does not change at level 1. For a change from level 1 to a higher level, level 2 or level 3, a logic 1 for a change to a closer level, level 2, and for a change to a farther level, level 3, Logic 2 is assigned. Then, logic 3 is assigned to a change to level 0, which is a level smaller than level 1.

For a state that does not change at level 0, a logic 0 is assigned. For a change to level 1, level 2 or level 3 larger than level 0, a level closer to level 0 is assigned in order from the level closer to level 0. Logic 1 is assigned to changes to level 1, logic 2 to changes to level 2, and logic 3 to changes to level 3.

FIG. 10 shows the relationship between the minimum inversion interval T _min of the multilevel variable length code and the detection window width T _W. The ternary variable length code obtains a larger product of the minimum inversion interval and the detection window width than the binary variable length code, and the quaternary variable length code obtains a larger value than the ternary variable length code. You can see that it can be done.

However, as the value N of the variable length code of the N value is increased, the influence of the characteristics on the recording medium or the transmission path becomes more prominent, and the use of a multi-level code having a value suitable for the recording medium or the transmission path is required. is necessary.

The recording medium or transmission path is, for example, as shown in FIG.
As shown in (1), it is possible to transmit (record and reproduce) only a signal having a cutoff frequency fc and a frequency lower than the cutoff frequency fc. For this reason, by using three or more variable length codes, higher density recording / reproduction (transmission) can be performed on the same recording medium (transmission path).

[0097]

As described above, in the present invention, the code word
Are represented by N value data (N is 3 or more), and the same symbol
At least one of the maximum continuous number or minimum continuous number of files
, And the maximum constraint length r is set , so that higher density recording / reproduction or transmission is possible.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an embodiment of a data modulation device according to the present invention.

2 is a diagram representing an example of the conversion table 14 _i of FIG.

FIG. 3 is a diagram showing another embodiment of the conversion table _14i of FIG.

Is a diagram showing still another embodiment of the conversion table 14 _i of FIG. 1;

FIG. 5 is a diagram illustrating binary NRZI.

FIG. 6 is a diagram illustrating ternary NRZI.

FIG. 7 is a block diagram showing a configuration of one embodiment of a data demodulation device of the present invention.

FIG. 8 is a diagram illustrating a procedure for recording and reproducing data according to the present invention.

FIG. 9 is a diagram illustrating quaternary NRZI.

FIG. 10 is a diagram illustrating a relationship between a minimum inversion interval of a multilevel variable length code and a detection window width.

FIG. 11 is a diagram illustrating frequency characteristics of a recording medium.

FIG. 12 is a diagram illustrating a conventional recording / reproducing procedure.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 Shift register 12 Encoding processing circuit 13 Selector 14 _i conversion table 15 Multiplexer 16 Uncertain level processing circuit 17 Buffer memory 18 Level converter 19 Clock generation circuit 31 Level converter 32 Constraint length judgment circuit 33 Selector 34 _{1 to} 34 _r Conversion table 35 multiplexer 36 buffer memory 37 PLL circuit

Claims (9)

(57) [Claims] 1. A data having a basic data length of m bits and a constraint length of i.
Variable-length code is converted into a code word with basic code length n bits and constraint length i
In the data modulation method, the codeword is represented by N-valued data (N is 3 or more), and the number of the maximum consecutive number or the minimum consecutive number of the same symbol is small.
A data modulation method having a restriction on at least one of them and setting a maximum constraint length r . 2. The variable length coding according to claim 1 , wherein said constraint length i is determined.
To the conversion table selected according to the judgment result.
2. The data modulation method according to claim 1, wherein the method is performed based on the data modulation. 3. The codeword according to claim 1, wherein said codeword has an indeterminate bit.
2. The data modulation method according to claim 1 , further comprising a definite code . 4. The method of claim 1, wherein the variable length encoding comprises:
Once converted to binary N-ary representation,
2. The data modulation method according to claim 1, wherein the data modulation is performed. 5. The code word according to claim 1, wherein the signal level does not change when the logic level is 0,
.., N, the larger signal level
Direction change as the first priority, closer signal level
To the predetermined signal level sequentially as the second priority.
2. A method according to claim 1, characterized in that it is represented as a signal, which is assigned to the change of the signal . 6. A data having a basic data length of m bits and a constraint length of i.
Variable-length code is converted into a code word with basic code length n bits and constraint length i
The codeword is represented by N-value data (N is 3 or more), and the maximum number of consecutive same symbols or the minimum number of consecutive consecutive symbols is small.
A data modulation device having a restriction on at least one of them and setting a maximum constraint length r . 7. A data having a basic data length of m bits and a constraint length of i.
Basic code length n bits generated by variable length coding from words
A code word having a constraint length i, wherein the code word is represented by N-valued data (N is 3 or more), and the number of maximum or minimum consecutive symbols of the same symbol is small.
A recording medium having a restriction on at least one of them and a maximum constraint length r is set . 8. A basic code generated by variable length coding
A code word with a constraint length i of n bits
A data demodulation method for demodulating a data word having a bundle length i, wherein the code word is represented by N-valued data (N is 3 or more), and the number of maximum or minimum consecutive symbols of the same symbol is small.
A data demodulation method characterized in that at least one of them has a limit and a maximum constraint length r is set . 9. A basic code generated by variable length coding
A code word with a constraint length i of n bits
A data demodulator for demodulating a data word having a bundle length i, wherein the code word is represented by N-valued data (N is 3 or more), and the maximum number of the same symbols or the minimum number of minimum
A data demodulator having a restriction on at least one of them and a maximum constraint length r being set .