JPH07202709A - Data modulation method, demodulation method, modulator, demodulator, recording and reproduction method - Google Patents

Abstract

PURPOSE:To attain higher density recording by recording and reproducing data through a specific code being a run length limit code limiting the same consecutive codes as a variable length code. CONSTITUTION:A conversion table 141 (i=1-r) of the modulator is a table used to convert binary data whose basic data length is m-bits into an N-value variable length code (N>=3) being a run length limit code limiting the same consecutive codes whose basic data length is n-bits. A multiplexer 15 multiplexes codes from the conversion table 141, stores the result once to a buffer memory 17, and a level converter 18 converts binary ternary expression data fed from the buffer memory 17 into N-value data and provides an output of the data. An uncertainty level processing circuit 16 detects an uncertainty bit from an output of the multiplexer 15 and provides an output of a detection signal to the level converter 18.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data modulating method, a demodulating method, a modulating device, a demodulating device, a recording method and a reproducing method, and in particular modulates data so as to be suitable for data transmission and recording on a recording medium, The present invention relates to a method and an apparatus suitable for use when demodulating a modulation code obtained by this modulation to reproduce data.

[0002]

2. Description of the Related Art When transmitting data or recording data on a recording medium such as a magnetic disk or an optical disk,
The data is modulated so as to be suitable for transmission and recording. A block code is known as one of such modulation codes. This block code is to block a data string into units of m × i bits (hereinafter referred to as data words) and convert the data words into code words of n × i bits according to an appropriate coding rule. . This code is
When i = 1, it becomes a fixed length code, and when i can select a plurality, that is, when i ≧ 1, it becomes a variable length code. This block-encoded code is a variable-length code (d, k;
m, n; r).

Here, i is referred to as a constraint length, and the maximum constraint length i _max is r (hereinafter referred to as maximum constraint length r). Further, d represents the minimum consecutive number of the same symbols, that is, the so-called minimum run of 0, for example, and k represents the maximum consecutive number of the same symbols, that is, the maximum run of 0, for example.

By the way, when the variable length code obtained as described above is recorded on, for example, an optical disk, the variable length code is further added to a so-called NRZI (Non Return to Zero Inv).
erted) modulation and NRZI-modulated variable length code (hereinafter referred to as a recording waveform sequence) is used for recording. The data recorded on the recording medium is N
RZI demodulation is performed, and the variable length code is decoded to restore the original data.

That is, the procedure of recording data on a recording medium and reproducing it is performed sequentially as shown in FIG.

By the way, the minimum inversion interval of the recording waveform train is T
From the viewpoint of recording density, it is preferable that the minimum inversion interval T _min is long, that is, the minimum run d is large, where _min is the maximum inversion interval and T _max is the maximum inversion interval. In terms of clock reproduction and so-called jitter, the maximum inversion interval T _{max is}
Is preferably short, that is, the maximum run k is small. Further, the detection window width T _W (=
It is preferable that (m / n) × T) is also large (T is a bit interval). That is, it is preferable that the conversion rate (m / n) is large.

In order to evaluate various modulation methods, the product of the minimum inversion interval T _min and the detection window width T _W (= T _min × T _W ) is used. It can be said that the larger this value is, the more preferable modulation method.

Table 1 shows the (1,7) RLL used in the magnetic disk and the modulation method of the (2,7) RLL.
EF used for optical recording such as compact discs
It represents the characteristics of the M (Eight to Fourteen Modulation) modulation method.

[0009]

[Table 1]

As shown in Table 1, the minimum inversion interval T
The value of the product of _min and the detection window width T _W is (1,7) RLL is 0.
89 is the largest, followed by (2,7) RLL is 0.75, and EFM is the smallest, 0.66.

As described above, even in the case of (1,7) RLL having the largest T _min × T _W , the value is 0.9 or less, which is close to the theoretical limit value 1.0 of the NRZI system. is there. Further, there is a limit to making a high-efficiency conversion table, and it is difficult to expect a large increase in recording density and recording speed by this method.

[0012]

As described above, in order to record a large amount of data on the recording medium by the modulation method in which the recording density cannot be increased in principle, the recording medium itself such as a disc or a cassette tape is enlarged, The recording speed needs to be faster. However, if the recording medium is made larger, the recording / reproducing apparatus also becomes larger. Further, there is a physical or mechanical limit in increasing the relative speed between the recording medium and the head.

The present invention has been made in view of such a situation and enables higher density recording.

[0014]

According to the data modulation method of the present invention, binary data having a basic data length of m bits is converted into a variable length code (d, k; m, n; r) having a basic code length of n bits. In the data modulation method for converting to, the variable-length code is a run-length limited code that limits the succession of the same code, and an N-valued code (N ≧ 3) is used.

The binary data can be converted into a binary N-ary representation and then converted into an N-ary code. Further, this N value can be three values.

The data demodulating method of the present invention is a data demodulating method for converting a variable length code (d, k; m, n; r) having a basic code length of n bits into binary data having a basic data length of m bits. Is a run-length limited code that limits the succession of the same code as a variable-length code, and has an N value (N ≧ 3)
It is characterized by using the sign of.

The N-ary code can be converted into binary N-ary representation and then converted into binary data.

The data recording method of the present invention is a data recording method for recording data on a recording medium, wherein binary data having a basic data length of m bits has a basic code length of n bits and the same code continues. Which is a run-length limited code that limits N, and is a variable length code (d, k;
It is characterized in that it is converted into m, n; r) and recorded on a recording medium.

A change in the level of the recording signal to the recording medium can be assigned to the code of the N value. In this case, the level of the recording signal to the recording medium is not changed when the code of the N value is 0, and when the code of the N value is 1, 2, ... Change is the first priority, change to a closer level is the second priority,
It is possible to sequentially set the predetermined levels.

The data reproducing method of the present invention is a data reproducing method for reproducing data recorded on a recording medium, the method corresponding to the level of a signal reproduced from the recording medium.
The basic code length is n bits, and it is a run-length limited code that limits the continuation of the same code, and has an N value (N ≧
3) The variable length code (d, k; m, n; r) of 3) is generated, and the variable length code is converted into binary data having a basic data length of m bits.

The N-valued code can be converted into binary N-ary representation and then converted into binary data. Also, the sign of the N value is assigned to the change in the level of the reproduced signal from the recording medium, and is set to 0 when the level of the reproduced signal from the recording medium does not change, and the change in the direction of larger level is given the first priority The rank is set as a priority, and the change to the closer level is set as the second priority.
Can be sequentially assigned.

The data modulator of the present invention is a run length limited code for limiting binary data having a basic data length of m bits to a succession of the same code, and a variable length code of N value (N ≧ 3) ( d, k; m, n; r) corresponding to the first and second conversion means (for example, the conversion table 14 _{i in} FIG. 1) for converting the binary-coded N-ary representation data into N-coded data.
Second conversion means (for example, the level converter 18 in FIG. 1) for converting into value data is provided.

The conversion table 14 _i stores binary data,
It is possible to record a conversion table for converting the data to the binary N-ary representation.

The data demodulating device of the present invention is a demodulating device for demodulating N-valued data corresponding to a variable length code (d, k; m, n; r) having a basic code length of n bits.
First conversion of value data into binary N-ary data
Conversion means (for example, the level converter 31 in FIG. 7) and second conversion means (for example, the table 34 in FIG. 7) for converting the binary-coded N-ary representation data into binary data having a basic data length of m bits. _i ) and are provided.

This table 34 _i can store a conversion table for converting the binary N-ary representation data into binary data.

[0026]

In the data modulating method, demodulating method, modulating device, demodulating device, recording method and reproducing method having the above-mentioned configurations, the variable length code is a run-length limited code for limiting the continuation of the same code, and an N value ( The code of N ≧ 3) is used. Therefore, higher density can be achieved.

[0027]

Embodiments of the present invention will be described below with reference to the drawings. In this embodiment, the present invention is applied to a modulation device for converting data into variable length codes (d, k; m, n; r) and a demodulation device for performing the reverse conversion.
FIG. 3 is a block diagram showing a specific circuit configuration of this modulator.

As shown in FIG. 1, the modulator uses input binary data in units of m bits (in the case of the embodiment shown in FIG.
= 3, m = 1 in the case of the embodiment of FIG. 3, m = 2 in the case of the embodiment of FIG. 4, and the constraint length of the data supplied from the shift register 11 in units of m bits. It has an encoding processing circuit 12 for determining i (i = 1 to r) and detecting data to be converted into a code including an indeterminate bit (hereinafter referred to as an indeterminate code). The conversion table (ROM) 14 _i converts binary data having a basic data length of m bits into variable length codes (d, k; m, n; r) of N values (N ≧ 3) having a basic code length of n bits. A conversion table for converting to (to be described later with reference to FIGS. 2 to 4, a conversion table for converting binary data into binary ternary representation data in these examples) I remember.

The multiplexer 15 includes a conversion table 14
The code from _i is combined and supplied to the buffer memory 17. The buffer memory 17 temporarily stores the variable length code from the multiplexer 15. The level converter 18 converts the binary-coded ternary representation data supplied from the buffer memory 17 into N-value (in the embodiment, ternary) data and outputs it. The uncertain level processing circuit 16 includes a multiplexer 15
The indeterminate bit (“11” in FIG. 4) is detected from the output of the above (1) and the detection signal is output to the level converter 18. The clock generation circuit 19 supplies a clock to the buffer memory 18 and the like.

In the present embodiment, binary data is converted into ternary data and output, but in the conversion table 14 _i , binary data is converted into binary ternary representation data. To be done. 2 to 4 show examples of tables stored in the conversion table 14 _i .

In the embodiment of FIG. 2, the variable length code (d, k; m, n; r) is (0,2; 3,2; 1). Then, the 3-bit binary data “000” to “111” is converted into the ternary (ternary) data. The binary data “001” to “111” is
The three-valued data "01" to "21" are sequentially associated. However, in order not to use "00" as the ternary data, "22" is used as the ternary data corresponding to the binary data "000".

Further, since it is difficult to store the ternary data in the memory, the ternary data is converted into the binary coded ternary representation according to the principle shown in Table 2.

[0033]

[Table 2]

That is, ternary data "0", "1", "
2 ”is the binary coded ternary expression, and is“ 00 ”and“ 0 ”.
The uncertain bit "*" of the ternary data is "11" in the binary coded ternary representation.

Therefore, as shown in FIG. 2, ternary (ternary)
The data “01” to “21” of are represented by “00 01” to “1001” in binary coded ternary representation. Also, the ternary data "22" is a binary ternary representation of "1".
It is set to 0 10 ".

In the embodiment of FIG. 3, the variable length code (d, k; m, n; r) is (1, ∞; 1,1; 2). In this embodiment, 2-bit binary data “11”, “10”, “01” correspond to ternary data “10”, “20”, “00”, respectively.
The 3-bit binary data “001” and “000” correspond to the ternary data “010” and “020”, respectively. In addition, according to the principle of Table 2, ternary data is 2
It is designed to be expressed in an evolutionary ternary expression.

Furthermore, in the embodiment of FIG. 4, the variable length codes (d, k; m, n; r) are (3, 8; 2,
3; 3). 2-bit binary data “11”
And "10" are ternary data "100" and "2", respectively.
00 ". The 2-bit binary data" 01 "corresponds to the ternary data" 00 * ". The" * "indicates an indeterminate bit. ing.

Further, 4-bit binary data "001"
1 ”,“ 0010 ”and“ 0001 ”are ternary data
010000 "," 020,000 "," 002000 "
, Each of which corresponds to 6-bit binary data "
000011 ”,“ 000010 ”,“ 00000
1 ”and“ 000000 ”are ternary data“ 01000 ”
1000 "," 010002000 "," 020001
000 "and" 020002000 ", respectively, and these ternary data are represented in binary ternary representation according to the principle of Table 2 as in the case described above. Thus, the indeterminate bit “*” is
In the binary coded ternary expression, it is set to "11".

For example, in the table of the embodiment shown in FIG.
The conversion table corresponding to i = 1 is the conversion table 14 ₁
The conversion table corresponding to i = 2 is stored in the conversion table 14 ₂ , and the conversion table corresponding to i = ₃ is stored in the conversion table 14 ₃ .

Next, the operation will be described. Now
It is assumed that the conversion table shown in FIG. 4 is stored in the conversion table 14 _i .

The shift register 11 converts, for example, so-called predictive coding and discrete cosine transform (DC) into a video signal.
T), data obtained by performing data compression processing such as Huffman coding is supplied. The shift register 11 shifts the supplied data in units of 2 bits and supplies the data to the encoding processing circuit 12.

The encoding processing circuit 12 determines the constraint length i of the data supplied in units of 2 bits. Specifically, the encoding processing circuit 12, the data supplied by the 2-bit unit, whether present in the data portion of the 2-3 conversion table shown in FIG. 4 (a conversion table 14 ₁₎ (left column) To judge. That is, the data “11”, “10”, “0”
When it is 1 ", the constraint length i is determined to be 1. When the data is" 00 ", the next 2 bits are added to make 4 bits (turn to the next rank).

Next, the encoding processing circuit 12 determines whether or not the data having a total of 4 bits corresponds to the data portion of the 4-6 conversion table (conversion table 14 ₂ ) shown in FIG. That is, the data “0011”, “001”
When it is 0 "or" 0001 ", the constraint length i is determined to be 2. When the data is" 0000 ", it is turned to the next rank.

Similarly, the encoding processing circuit 12
Determines whether the data supplied from the shift register 11 in units of 2 bits exists in the data portion of the 6-9 conversion table (conversion table 14 ₃ ) shown in FIG. 4, and the constraint length i = 3. Determine if there is.

Next, the selector 13 selects the conversion table 14 _i based on the constraint length i supplied from the encoding processing circuit 12, and the selected conversion table 14 _i has m
Supply i bits of data.

Specifically, the selector 13 is, for example, i =
When it is 1, the conversion table 14 _i is selected, and 2-bit data “11”, ”is _added to the selected conversion table 14 _i.
10 "and" 01 "are supplied.

Further, for example, when i = 2, the conversion table 14 ₂ is selected, and 4 is added to the selected conversion table 14 ₂ .
Bit data “0011”, “0010”, “000”
1 "is supplied. Further, when i = 3, the conversion table 14 ₃ is selected, and 6-bit data" 00001 "is stored therein.
1 "," 000010 "," 000001 "," 000
000 "is supplied.

As described above, the conversion tables 14 _{1 to} 14 ₃ have the 2-3 conversion table, the 4-6 conversion table, and the 6-9 conversion table of FIG. 4, respectively.
The code stored in the storage unit is read as the read address of the data supplied via.

As a result, for example, the data is "11", "1".
When it is 0 ”or“ 01 ”, the binary coded three-dimensional representation code“ 01 00 00 ”or“ 10 00 ”is obtained from the conversion table 14 _1.
00 "or indeterminate code" 00 00 11 "is output. Further, for example, the data is" 0011 "," 001 ".
0 "," when 0001 ", from the conversion table 14 _2,
Code of binary coded ternary expression "00 01 00 00 0
0 "," 00 10 00 00 00 00 "or" 00
00 10 00 00 ”is output. Further, for example, the data is“ 000011 ”,“ 000010 ”,“ 0 ”.
In the case of 00001 "and" 000000 ", the code of the binary coded ternary representation is" 0001 00 "from the conversion table 14 _3.
00 00 01 00 00 "," 00 01 00
0000 10 00 00 "," 00 10 00
00 00 01 00 00 "," 00 10 0
0 00 00 10 00 00 "is output.

That is, these conversion tables 14 _{1 to} 1
The variable length code of binary coded ternary representation is output from 4 ₃ .
This variable length code is supplied from the buffer memory 17 to the level converter 18. The uncertain level processing circuit 16 supplies a detection signal to the level converter 18 when detecting the uncertain bit “11” from the output of the multiplexer 15.

The level converter 18 receives the input binary 3
Converts data in radix representation into data in ternary representation (3 values). For this reason, the level converter 18 also has a built-in conversion table (ROM) (for converting binary coded ternary representation data into ternary data) similar to the case shown in FIGS.

Therefore, for example, in the present case, the data "01 00 00", "10" of the binary coded ternary representation shown in FIG.
When "00 00" is input, ternary data "10"
0 "and" 200 "are output.

Data of binary coded ternary expression "00 0"
Uncertainty level processing circuit 1 when 0 11 "is input
An indeterminate bit detection signal from 6 is input to the level converter 18. At this time, the level converter 18 detects the 2-bit data to be input next, and outputs the ternary data “001” when the 2-bit data is “00” and the 2-bit data is When "01", ternary data "
000 "is output.

Further, the data "00" in the binary coded ternary representation
01 00 00 00 "," 0010 00 00
00 "," 00 00 10 00 00 "," 00
01 00 00 00 00 01 00 00 "," 00
01 00 00 0010 00 00 "," 0
0 10 00 00 00 00 01 00 00 ","
When "00 10 00 00 00 00 10 00 00" is input, the corresponding ternary data "01000"
0 "," 020,000 "," 002000 "," 010
001000 "," 010002000 "," 0200
01000 "and" 020002000 "are output.

As described above, the code output from the level converter 18 is output as a modulation code at a predetermined transfer rate.

The modulation code is added to an error correction code, a synchronization signal, etc., in a so-called ECC circuit (not shown), and recorded on a recording medium such as a magnetic disk, a magnetic tape, an optical disk, or transmitted, for example. Sent out through the road.

Next, referring to FIG. 5 and FIG. 6, three values (3
Next, the level of the recording data (transmission signal) and the data of the base) will be described.

As for the binary NRZI signal, as shown in FIG. 5, the logic is assigned to the level change. That is,
When the signal level does not change at 1 or 0, NRZI
The sign of the signal is 0. On the other hand, when the level 1 changes to the level 0 or vice versa, the sign of the NRZI signal is 1.

As for the ternary data and the allocation to the level, the ternary data 0 corresponds to the state in which the level does not change so that the basic concept is the same as in the case of the binary value. Of these, 1 and 2 correspond to changes in level. Then, with the change to the higher level as the first priority and the change to the closer level as the second priority, either logic 1 or logic 2 corresponds to the level change.

That is, level 1, level 2 or level 0
At, when the level does not change, the logic is set to 0. On the other hand, a logic 1 is assigned to a change from level 1 to a higher level, level 2, and a logic 1 is assigned to a change from level 1 to a lower level, level 0. 2 is assigned.

Level 1 is a level change from level 2 to a lower level, which is a closer level.
A logic 1 is assigned to the change to, and a logic 2 is assigned to the change to the farther level, level 0. Also, a logic 1 is assigned to a change from level 0 to a higher level, which is a closer level, and a logic 2 is assigned to a change to a farther level, level 2. Is assigned.

By allocating the ternary logic in this way, it is possible to perform processing with the same concept as in the case of the binary.

Next, an embodiment of the demodulator will be described with reference to FIG. As shown in FIGS. 2 to 4, this demodulator has a level conversion having a conversion table for converting ternary data into binary ternary representation data (inverse conversion table for reverse conversion to that in FIG. 1). The container 31 is provided. The data converted into the binary coded ternary representation by the level converter 31 are supplied to the constraint length determination circuit 32 and the PLL circuit 37, respectively.

The constraint length judgment circuit 32 is composed of the level converter 31.
The constraint length i is determined from the output of the above, and is output to the selector 33. The selector 33 supplies the binary-coded ternary representation data, which is also supplied from the constraint length determination circuit 32, to any of the conversion tables 34 _{1 to} 34 _r in correspondence with the constraint length i from the constraint length determination circuit 32. It is designed to do.

The conversion tables 34 _{1 to} 34 _r store conversion tables for converting the binary-coded ternary representation data into binary data, as in the case shown in FIGS. 2 to 4. .

The multiplexer 35 includes a conversion table 34.
_The data supplied from _{1 to} 34 _r are combined and output to the buffer memory 36. The clock generated by the PLL circuit 37 is supplied to the buffer memory 36.

Next, the operation will be further described. First, when the ternary data is input, the level converter 31 converts the data into binary ternary representation data. For example, when ternary data "100" and "200" are input, these are converted into binary ternary representation data "01 00 00" and "10 00 00". Also, ternary data "000" or "00"
When "1" is input, it is converted to binary coded ternary representation data "00 00 11".

Further, ternary data "01000"
0 "," 020,000 "," 002000 "," 010
001000 "," 010002000 "," 0200
When 01000 ”and“ 020002000 ”are input, binary evolution ternary representation data“ 00 ”is correspondingly input.
01 00 00 00 "," 00 10 00 0
000 "," 00 00 10 00 00 "," 00
01 00 00 0001 00 00 "," 00
01 00 00 00 10 10 00 "," 00 1
0 00 00 00 00 01 00 "," 00 10
"00 00 0010 00 00 00" is output.

The constraint length determination circuit 32 includes a level converter 31.
Determine the constraint length i of the binary-coded ternary representation data supplied from.

The selector 33 selects the conversion table 34 _i based on the constraint length i from the constraint length determination circuit 32,
The binary coded variable length code is supplied to the selected conversion table 34 _i .

Specifically, the selector 33, for example, i =
When it is 1, the conversion table 34 ₁ is selected, and the 6-bit code “01 00” is added to the selected conversion table 34 _1.
00 "," 10 00 00 "or" 00 00 1 "
Supply 1 ".

For example, when i = 2, the selector 3
3 selects the conversion table 34 _2, the conversion table 34 ₂ that this selection, the 10-bit code "00 01 0
000 "", "00 10 00 00 00" or "00 00 1000 00" is supplied.

[0073] In the same manner, the selector 33, when the constraint length i is 3, and selects a conversion table 34 _3, the conversion table 34 ₃ selected supplies 16-bit code.

The conversion tables 34 ₁ , 34 ₂ , and 34 ₃ are, as described above, 6-2 conversion tables and 10-4, respectively.
The conversion table and the 16-6 conversion table are provided, and the data supplied from the selector 33 is used as the read address to read the data in the data section shown in FIGS.

As a result, for example, the code is "01 00 0".
0 "," 10 00 00 "or" 00 00 1 "
", The data from the conversion table 34 _1" 1 1
1 "," 10 "or" 01 "is output.

Further, for example, the code is "00 01 00".
00 00 "," 00 10 0000 00 "," 0
0 00 10 00 00 ", the conversion table 3
4 ₂ data from "0011", "0010", "000
1 "is output.

For example, the code is "00 01 00 00
00 01 00 "," 00 0100 00 00 00
10 00 "," 00 10 00 00 00 00 01
00 00 "," 00 10 00 00 00 00 10
When it is “00 00”, data “000011”, “000010”, “00000” from the conversion table 34 ₃
1 "and" 000000 "are output.

That is, these conversion tables 34 _{1 to} 34 3
From 4 _r , a 3 × i-bit variable length code is inversely converted into 2 × i-bit data and output, and these data are supplied to a multiplexer 35.

The multiplexer 35 multiplexes the data supplied from the conversion tables 34 _{1 to} 34 _r , respectively,
It is supplied to the buffer memory 36 as serial data.

On the other hand, the PLL circuit 37 reproduces a clock based on the variable length code and supplies the reproduced clock to the buffer memory 36.

The buffer memory 36 includes the multiplexer 3
5 temporarily stores the data supplied from the PLL circuit 37.
The stored data is output as reproduction data at a predetermined rate according to the clock supplied from. The output data is subjected to data processing such as inverse DCT and predictive decoding, and reproduced as a video signal.

Thus, in this demodulator, the code including the indeterminate bit is detected, the constraint length i of the variable length code is judged based on the detection result, and the variable length code of n × i bits is converted into m × i bits. By the inverse conversion table for inverse conversion into data, the variable length code including the indeterminate code can be demodulated into data by inversely converting the variable length code into data based on the constraint length i.

Table 3 shows the detection window width T _W of the variable-length code shown in FIGS. 2 to 4, the minimum inversion interval T _min , and the maximum inversion interval T.
_max and the product T of the minimum inversion interval T _min and the detection window width T _W
It represents _min × T _W.

[0084]

[Table 3]

As shown in Table 3, these values of the variable length code T (0,2; 3,2; 1) shown in FIG. 2 (T in this case represents three values) are as follows. 1.5T, 1.
It is 5T, 4.5T and 2.25. In the variable length code T (1, ∞; 1,1; 2) shown in FIG. 3, the values are 1.0T, 2.0T, ∞, 2.0. Furthermore, the variable length code T (3,8; 2,3;
In 3), 0.67T, 2.66T, 6.0T,
It is 1.78. Any product T _min × T _W also the minimum inversion interval T _{mi n} and the detection window width T _W is seen to have a large value of 1 or more.

FIG. 8 shows the flow of processing for transmitting (recording / reproducing) data in this embodiment. As shown in the figure, the binary data is encoded into a variable length code according to the conversion table as shown in FIGS.
The variable length code is represented by binary coded ternary representation. As a result, a normal ROM or the like can be used as the conversion table. Then, the binary-coded ternary representation data is further converted into ternary data (ternary representation data). Then, this ternary data is recorded on a recording medium or transmitted to a transmission line.

The data reproduced from the recording medium or the data received from the transmission path is the data in the ternary representation. This ternary representation data is converted into binary ternary representation data. Then, the binary-coded ternary representation data is decoded and converted into the original binary data.

In the above embodiment, binary data is converted to 3
Although it is converted into the value data, it may be converted into the four-value data.

FIG. 9 shows an example of a correspondence relationship between four values 0 to 3 and a signal level change. Also in this example, among the four-valued logic of 0 to 3, logic 0 is assigned to the state where the level does not change, and logic 1 to 3 is assigned to the level change. Also in this case, the level change in the larger direction is the first priority, the change to the closer level is the second priority, and the logic 1 to logic 3 are sequentially assigned.

Therefore, for example, when there is no change at the level 2, the logic 0 is set, and the logic 1 is assigned to the change from the level 2 to the level 3 which is a larger level. Then, for a change from level 2 to a smaller level, level 1 or level 0, a logic 2 for a change to a closer level, level 1.
Is assigned, and a logic 3 is assigned to changes to the farther level, level 0.

A logic 0 is assigned in the state of not changing at the level 3, and a change from the level 1 to the level 2 which is a level smaller than the level 3 to the level 1 or the level 0 is performed in the order of the closer levels. Logic 3 is assigned. That is, a logic 1 is assigned to a change from level 3 to a level 2, a logic 2 is assigned to a change to level 1, and a logic 3 is assigned to a change to level 0.

A logic 0 is assigned to the state that does not change at level 1. For a change from level 1 to a higher level, level 2 or level 3, a logic 1 for a change to a closer level, level 2, to a change to a farther level, level 3. Logic 2 is assigned. Then, a logic 3 is assigned to a change to level 0, which is a level smaller than level 1.

A logic 0 is assigned to a state that does not change at level 0, and a change to level 1, level 2 or level 3 which is higher than level 0 is performed in order from a level close to level 0, respectively. A logic 1 is assigned to changes to level 1, a logic 2 is assigned to changes to level 2, and a logic 3 is assigned to changes to level 3.

FIG. 10 shows the relationship between the minimum inversion interval T _min of the multilevel variable length code and the detection window width T _W. To obtain a larger product of the minimum inversion interval and the detection window width for a ternary variable-length code than for a binary variable-length code, and for a quaternary variable-length code than a ternary variable-length code. You can see that

However, if the value N of the variable length code of N value is increased, it becomes more susceptible to the characteristics of the recording medium or the transmission path, and a multi-value code having a value suitable for the recording medium or the transmission path should be used. is necessary.

The recording medium or transmission line is, for example, as shown in FIG.
As shown in, it is possible to transmit (record / reproduce) only a signal having a cutoff frequency fc and a frequency lower than this cutoff frequency fc. Therefore, by using a ternary or more variable length code, higher density recording / reproducing (transmission) can be performed on the same recording medium (transmission path).

[0097]

As described above, according to the present invention, data is recorded / reproduced or transmitted by using a variable length code of three or more values, so that higher density recording / reproduction or transmission can be performed.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a data modulator of the present invention.

FIG. 2 is a diagram showing an example of a conversion table 14 _i in FIG.

FIG. 3 is a diagram showing another example of the conversion table 14 _i in FIG.

FIG. 4 is a diagram showing still another embodiment of the conversion table 14 _i of FIG.

FIG. 5 is a diagram illustrating binary NRZI.

FIG. 6 is a diagram illustrating ternary NRZI.

FIG. 7 is a block diagram showing a configuration of an embodiment of a data demodulating device of the present invention.

FIG. 8 is a diagram illustrating a procedure of recording and reproducing data according to the present invention.

FIG. 9 is a diagram illustrating four-valued NRZI.

FIG. 10 is a diagram illustrating a relationship between a minimum inversion interval of a multi-valued variable length code and a detection window width.

FIG. 11 is a diagram illustrating frequency characteristics of a recording medium.

FIG. 12 is a diagram illustrating a conventional recording / reproducing procedure.

[Explanation of symbols]

11 shift register 12 encoding processing circuit 13 selector 14 _i conversion table 15 multiplexer 16 indeterminate level processing circuit 17 buffer memory 18 level converter 19 clock generation circuit 31 level converter 32 constraint length determination circuit 33 selector 34 _{1 to} 34 _r conversion table 35 multiplexer 36 buffer memory 37 PLL circuit

Claims (16)

[Claims] 1. A binary data having a basic data length of m bits and a variable length code (d, k; m, having a basic code length of n bits).
In the data modulation method for converting into n; r), the variable-length code is a run-length limited code that limits the succession of the same code, and an N-valued (N ≧ 3) code is used. Modulation method. 2. The data modulation method according to claim 1, wherein the binary data is first converted into a binary N-ary representation and then converted into an N-ary code. 3. The data modulation method according to claim 1, wherein the N-valued code is a ternary code. 4. A data demodulating method for converting a variable length code (d, k; m, n; r) having a basic code length of n bits into binary data having a basic data length of m bits, wherein the variable length code is The data demodulating method is characterized in that a run-length limited code for limiting the continuity of the same code is used, and an N-valued code (N ≧ 3) is used. 5. The data demodulating method according to claim 4, wherein the N-valued code is once converted into a binary N-ary representation and then converted into binary data. 6. A data recording method for recording data on a recording medium, wherein binary data having a basic data length of m bits has a basic code length of n bits and a run length limitation for limiting continuation of the same code. A data recording method, wherein the data is converted into a variable length code (d, k; m, n; r) of N value (N ≧ 3) and recorded on the recording medium. 7. The data recording method according to claim 6, wherein the sign of the N value is assigned to a change in the level of a recording signal to the recording medium. 8. The level of a recording signal to the recording medium is
When the sign of the N value is 0, it is not changed. When the sign of the N value is 1, 2, ... 8. The data recording method according to claim 7, wherein the change to the level is set as the second priority and the levels are sequentially set to a predetermined level. 9. A data reproducing method for reproducing data recorded on a recording medium, comprising: corresponding to a level of a signal reproduced from the recording medium,
The basic code length is n bits, and it is a run-length limited code that limits the continuation of the same code, and has an N value (N ≧
3) A variable length code (d, k; m, n; r) of 3) is generated, and the variable length code is converted into binary data having a basic data length of m bits. 10. The data reproducing method according to claim 9, wherein the code of the N value is once converted into a binary N-ary representation and then converted into binary data. 11. The data reproducing method according to claim 9, wherein the code of the N value is assigned to a change in level of a reproduced signal from the recording medium. 12. The sign of the N value is assigned to 0 when there is no change in the level of the reproduction signal from the recording medium, and the change in the direction of larger level is set as the first priority, and the level is closer. Is the second priority,
The data reproducing method according to claim 9, 10 or 11, wherein the data is sequentially allocated to 1, 2, ..., N-1. 13. A variable length code (d, k; m, N-value (N ≧ 3), which is a run-length limited code for limiting binary data having a basic data length of m bits to prevent continuation of the same code.
n; r), and first conversion means for converting the binary-coded N-ary representation data into data, and second conversion means for converting the binary-coded N-ary representation data into the N-valued data. A data modulator characterized by the above. 14. The data modulation apparatus according to claim 13, wherein the first conversion unit has a conversion table for converting the binary data into the binary N-ary representation data. . 15. A demodulator for demodulating N-value (N ≧ 3) data corresponding to a variable-length code (d, k; m, n; r) having a basic code length of n bits, wherein the N-value data Is converted into binary N-ary representation data, and second conversion N-ary representation data is converted to binary data having a basic data length of m bits. A data demodulating device comprising. 16. The binary conversion N is the second conversion means.
16. The data demodulating device according to claim 15, further comprising a conversion table for converting the data represented by a binary number into the binary data.