JPH01268233A - Method for parallely transmitting light - Google Patents

Abstract

PURPOSE:To reduce the scale of a logic circuit by performing encoding for generating error detectable codes from original data at every plural bits and optically transmitting the error detectable codes in parallel with each other, and then, simultaneously performing reproduction of the original data by decoding and erroneous bit position designation. CONSTITUTION:An encoder 1 encodes data by using error detectable codes at every plural bits and optically transmits the encoded data in parallel with the error detectable codes and a decoder 7 decodes the original data and designates erroneous bit positions. Therefore, optical parallel transmission can be realized with a small circuit scale, because optical parallel transmission which can be monitored for fault can be performed and the data rate can be made the same as the transmission rate. Moreover, since the fault processing can be performed easily to the parallel transmission lines when the erroneous bit position designating information is utilized, the reliability of the parallel transmission can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information transmission method using an optical fiber, and particularly to a highly reliable parallel transmission method.

[Conventional technology]

As the amount of information to be processed increases, transmission using optical fibers that are resistant to noise and capable of large-capacity transmission are increasingly being used. In particular, in the past, serial data transmission by time division was the main method for achieving high speed and large capacity, but on the other hand, there is a demand for optical transmission using parallel data transmission (this is called optical parallel transmission).

In parallel optical transmission, in order to send data in parallel, it is necessary that the reliability of the optical transmission equipment including the laser is particularly high, and fault monitoring of the transmission line is essential.

Conventionally, as an optical parallel transmission method, there is a method announced in lecture number 2408 at the national convention commemorating the 70th anniversary of the founding of the Institute of Electronics, Information and Communication Engineers. This is a system in which a plurality of bits that should be sent sequentially for each data line that transmits each parallel bit are combined into serial data, and this serial data is sent in parallel using a plurality of data lines.

The advantage of this conventional example is that the number of data lines can be easily expanded, and by providing redundancy to each serial data, the codes of the transmission line corresponding to the data line are equal to O and 1. It has the advantage that it is easy to code, that is, it is easy to maintain DC balance of the transmission code, and that fault monitoring of the transmission path corresponding to the data line can be easily performed by code error detection using redundancy.

On the other hand, this conventional example has the following drawbacks, and there are problems that need to be solved.

[Problem to be solved by the invention]

In the conventional example described above, it is necessary to encode and decode each data line, and the data rate of the serial data must be increased because the serial data is transmitted serially with redundancy for code error detection. is smaller than the transmission speed,
A large number of clocks are required. Also, in serial data transmission, it is necessary to use a special code called a channel header to separate the data to be sent at one time, but there is also a need to synchronize the codes using this channel header, making the logic circuit complex and large. There were drawbacks such as.

The present invention enables failure monitoring in high-capacity, short-distance transmission of questions and answers between, for example, the main storage device and arithmetic unit in a computer, and the multiplexing device and switching device of an exchange, has the same data rate and transmission speed, and has a small logic circuit. The purpose is to provide a parallel transmission method.

[Means to solve the problem]

In order to achieve the above object, the present invention takes the following method.

1. Encoding is performed to generate an error detectable code for each of a plurality of bits from the original data, the error detectable codes are optically transmitted in parallel, and the original data is reproduced by decoding and an error bit device is designated.

2. Perform encoding to generate an error-detectable code for each plurality of bits from the original data, optically transmit the error-detectable code in parallel, and further reproduce the original data by decoding and specify the error bit position; And fault handling is performed based on the error bit position designation information.

3. In the above item 2, fault processing based on the error bit position verification information is performed by determining that a fault has occurred in the transmission path corresponding to the bit position where errors have occurred a predetermined number of times or more within a certain period of time.

4. In the above items 1 to 3, when data is not being transmitted, dummy data is transmitted on the transmission path corresponding to all code bits so that the bits are not fixed at O or fixed at 1.

[Effect]

FIG. 1 shows the basic configuration of a device to which the present invention is applied. Consists of a coding device 1 that generates an error-detectable code of n bits (k<n) for every plural bits (k bits) from data to be sent in parallel (hereinafter referred to as parallel data), and n optical transmitters. A transmitting device 3, a transmission line '4, a receiving device 5 consisting of n pre-receiving signals, a decoding device 7 having a function of detecting errors from the received code, and if necessary, a signal from the decoding device 7. It is comprised of a control device 20 that monitors information on transmission paths where errors have occurred and issues necessary fault handling instructions.

It has been said that error detection is difficult because parallel data consists of arbitrary combinations of O's and 1's, but in the present invention,
As described above, by performing n-bit error detectable encoding for each bit in parallel and decoding it through a transmission path, it is possible to specify the bit position where an error occurs and to perform error correction.

Specifying the bit position where the error occurs specifies the transmission path where the error occurs, which facilitates troubleshooting.

Determining that a failure has occurred in the transmission path corresponding to a bit position where errors have occurred a predetermined number of times or more within a certain time is as follows:
This distinguishes between failures in the transmission path and failures due to deterioration of other parts. The predetermined number of times is determined statistically.

When data is not being transmitted, dummy data can be transmitted on the transmission path corresponding to all code bits so that it is not fixed at O or 1 even when no data is being transmitted. This makes it possible to detect failures in the transmission line and improves the reliability of the transmission line.

Note that data that is not fixed to 0 or 1 is transmitted as the dummy data in order to make it possible to detect specific failures that correspond to fixed O or 1.

Furthermore, by performing k-bit n-bit conversion in parallel and transmitting data using n transmitters and receivers, the data rate and transmission rate can be made equal. This makes it unnecessary to increase the clock. Furthermore, since serial data transmission is not performed, code synchronization using a channel header is not required. Further, it is sufficient to provide an encoding and decoding device for each bit, and there is no need to provide one for all parallel bits. Therefore, the circuit scale of the device to which the present invention is applied is reduced.

The disadvantage of the present invention is that it is only expandable in k-bit units or in bit units limited by error-detectable codes, but computer data and the like can be expanded in word units without causing any problems. In addition, although it is not possible to maintain DC balance for serial data, in optical fiber communication, insulation between the transmitting device and receiving device is automatically taken, and because the input signal level is high over relatively short distances, direct current connection or direct current connection or DC balance is not an essential condition because the transmitter and receiver can be configured with close circuits.

〔Example〕

An embodiment to which the present invention is applied will be described below with reference to FIGS. 2 to 8.

In this embodiment, 4-bit parallel data 30A, 30B.

30G and 30D are transmitted using fiber 4 and reproduced into 4-bit parallel data 40A, 40B, 40C, and 40D. Also, the data rate is synchronized to the source clock,
Transmit clock line 30Q, and receive clock line 4 on the receiving side.
Play at 0Q.

In this embodiment, a 1-bit error detection function is used as a transmission code.
A Hamming code was used as an example of a correctable code.

The transmission section includes a parallel code section 1 that converts 4-bit data on the transmission data line 30 into a 7-bit Hamming code; a data optical signal sending section 3 consisting of eight optical transmitters 3A to 3H including one spare; A switch unit 2 that selects a protection line when there is a failure in the transmitter, a transmitter control circuit unit 10 that controls the switch unit 2 based on instructions from the receiver, and two optical transmitters 103A and 103B that send out transmission clock lines. The optical clock signal transmitting section 103 consists of a clock optical signal transmitting section 103 consisting of: The optical output of the transmitting section is input to the receiving section through the fiber 4.

The reception section includes a data optical signal reception section 5 consisting of eight optical receivers 5A to 5H, a switch section 6 that switches to a protection line in the event of a failure, and an error detection/correction function that reproduces 4-bit original data from the received 7-bit data. A clock optical signal receiving section 105 consisting of two optical receivers 105A and 105B that receive the clock, and a clock switching section 106 that selects a clock from 105A and 105B as necessary.
, receives input of error detection information from the parallel decoding section 7, outputs a line switching instruction line 60 to the switch section 6 and a line switching instruction line 43 to the transmitting section control circuit section as necessary, and outputs the line switching instruction line 43 to the transmitting section control circuit section. The receiving unit control circuit unit 20 receives a clock disconnection detection signal 142 from the receiver, outputs a clock switching instruction line 62 as necessary, displays a failure as necessary, and notifies another system of the failure. be done.

In this embodiment, 4-bit data is transferred every 4 nanoseconds. Therefore, the bit rate of the optical transceivers 3A to 3H is every 4 nanoseconds, that is, 250 megabits/second. Also, the clock will be 250 MHz.

In this embodiment, 4-bit data is transmitted using a 7-bit Hamming code, and such a transmission code is described, for example, in Miyayo et al.'s ``Coding Theory'' (Computer Course 18), published by Shokodo, pages 42-43. It is. In other words, in a Hamming code of 4-bit data and 7-bit code, the so-called (7.4) code, if data (dt...d4) is made into a Hamming code of (X...X7), then , the encoding rule is given by equation (1).

FIG. 3 shows a circuit diagram of the parallel code section 1 in FIG. 2, and is a circuit representation of equation (1).

30A, 30B, 30G, 30D in Figure 3
are respectively d x +d2. d3. 31X on d4,
31Y, 31Z, 31A, 31B.

31C and 31D are respectively xl, xl, x4. x
3. X5tx6. x.

In this code, error checking is performed as follows.

That is, if we use the check matrix (H) as the check matrix and the matrix (e) that gives the error positions, it is given by: That is, all 829'e3 is set as the third bit, second bit, and first bit, respectively, and the values give the error bit position. For example, “118ZT e3
When each is 0, it indicates that there is no error. el, e
2. If e3 is O, 0, 1, the 1st bit is 0, 1 .
The error bit position is indicated by a binary code such that O means that the second bit is incorrect, and 0°1.1 means that the third bit is incorrect.

Decoded data when there is no error (f□...f4)
Then, the required data is given by equation (5).

When an error occurs, since the error bit position is known as described above, the bit corresponding to the error bit position can be inverted and corrected.

FIG. 4 shows five circuit diagrams of the parallel decoding section 7 in FIG. 2, and is a circuit representation of equations (4) and (5). That is, 41X, 41 corresponding to the symbols in FIG.
Y, 41Z,, 41A, 41B, 41C,
Error bit position information signals 42A, 42B, 42G given by equation (4) from the code of 41D and data outputs 40A, 40B, 40G, given by equation (5).
40D is obtained. .

FIG. 5 shows a block diagram of the receiver control circuit section 20 in FIG. 2. The error pit position information signal 42 detected by the parallel decoding section 7 is latched into a 3-bit register RO. Whether this latched signal is O (if O, there is no error, 0
(If not, it indicates a likely error) is determined by the determination circuit 23. If it's not O-12-.

If so, the contents of register RO are latched into register R1 after one time slot (4 nanoseconds). The register R1 has an initial value of O, and the previous incorrect bit position information is latched therein. Every time, the error bit position information register RO is compared with the contents of the previous error bit position information register R1 by a comparator CMP. If the error bit position information is not O but equal, the value of the counter CNT is incremented by 1.

If it is not 0 and not equal, set the value of CNT to 0.

In this way, consecutive errors at the bit error positions indicated in register R1 are counted in CNT.

(It is circled, and the value of CNT is the number of errors - 1.

) Further, the CNT is reset at fixed time intervals by the timer TIM. In this way, the number of consecutive errors within a certain period of time can be determined.

In this embodiment, it is determined that a failure has occurred in the transmission line when an error occurs three times in a row at the same bit position within 120 milliseconds (corresponding to a bit error rate of 10-7). For this purpose, the timer TIM outputs a reset signal at 120 millisecond intervals, and when the value of the counter CNT becomes 2 or more, it is assumed that a failure has occurred in the transmission path, and the bit error position is stored in the register R2 from the register R1. Latch. The register R2 has an initial value of O, and outputs the pin 1-error position signal latched from R1 to the line switching instruction line 60 to the switch section 6 and the line switching instruction line 43 to the transmitting section.

FIG. 6 shows a circuit diagram of the switch section 2 in FIG. 2, and FIG. 7 shows a circuit diagram of the switch section 6 in FIG. 2.

Line switching instruction line 61 (3 bits 6), A, 61B
, 61C. ) and line switching instruction line 60 (3
Consists of bits 60A, 60B, and 60C.

) to avoid transmission lines that are thought to be in trouble. In the figure, 161 and 162 are decoder circuits.

61A, 61B, 61C in Figure 6 and 60A in Figure 7
, 60B, and 60C, line switching can be performed.

FIG. 8 shows the logic of the switch sections 2 and 6 when no error occurs in the transmission path. Circled 1 out of 8
7-bit data is transmitted avoiding the main transmission path. Since the initial value of the instruction lines 60 and 61 (in a situation where no failure has occurred) is 0, the transmission line (2) from the transmission line 32H to 42H is the backup line. When a failure occurs,
The generated transmission line is avoided by the instruction lines 60 and 61, and the protection line is used. For example, if the error bit position signal becomes 001, the transmission line (Φ) (transmission line from 32G to 42G) is avoided, and the transmission line (■), which had been a backup line until then, is avoided. It will be used as a closure.

Regarding the clock, two systems are used for transmission, normal and backup, and when the signal is cut off on the normal line, the clock switching unit 1
At 06, switch to the backup line.

As described above, it becomes possible to detect a data line failure and switch to a protection line using an error detectable code, and to detect a clock failure and switch to a protection line.

Also, when data is not being transmitted, dummy data'
By transmitting ``oooo'' and ``1111'' alternately, the code for the data ``o o o o'' is ``o''.
o o o o o o' and data 11111
Since the code for ' is '1111111', '0' and 11' are transmitted alternately on all transmission paths, making it possible to detect failures including specific failures such as O fixed or 1 fixed. Since faults are constantly detected, faults can be easily discovered.

In the above embodiment, it is obvious that the data line is expanded every 4 bits.

In the above embodiment, a 7-bit Hamming code is transmitted, but the code is not limited to the Hamming code, and various types of error-detectable codes of 1 or more bits can be applied. In this case, a code that can be detected not necessarily for each bit but for each block of two or more bits is applied, so that failures can be avoided for each block.

In the above embodiment, one fiber is assigned to each transmitter, but it is also possible to reduce the number of fibers by spatial multiplexing such as wavelength multiplexing or frequency multiplexing.

In the above example, when three consecutive errors occur at the same bit position within 20 milliseconds, it is determined that there is a fault in the corresponding transmission path, but the time and number of fault determination methods can be changed by the system. can.

Further, in the embodiment, errors at the same three bit positions are monitored in succession, but the monitoring method can be changed depending on the system, such as counting errors at all bit positions.

Furthermore, there may be various types of failure handling other than those shown in the embodiment.

[Effects of the Invention] The present invention provides optical parallel transmission in which faults can be monitored by encoding multiple bits of data using an error-detectable code, transmitting the data in parallel optically, decoding it, and specifying the error bit position. Moreover, the data rate and transmission rate can be made the same, and optical parallel transmission can be realized with a small circuit scale.

Furthermore, by performing fault processing based on error bit position specification information, fault processing on parallel transmission paths can be easily performed.
It is possible to improve the reliability of parallel transmission.

By determining that a fault has occurred in the transmission line corresponding to the pin I/position where a predetermined number of errors or more have occurred within a certain period of time, and processing the fault, the fault in the transmission line is distinguished from component deterioration, and processing is performed. can definitely be done.

Even when data is not being transmitted, by transmitting data so that it is not fixed at O or fixed at 1, faults can be constantly monitored and the reliability of the parallel transmission path can be improved.

[Brief explanation of the drawing]

FIG. 1 is a basic diagram of a device configuration to which the present invention is applied, FIG. 2 is a block diagram of an embodiment to which the present invention is applied, and FIG.
4 is a circuit diagram of the decoding section in FIG. 2, FIG. 5 is a block diagram of the receiving section control circuit in FIG. 2, and FIG. 6 is a transmission diagram in FIG. 2. FIG. 7 is a circuit diagram of the receiving section switch section of FIG. 2, and FIG. 8 is a switching logic circuit diagram of the protection line. 1... Encoding device or parallel encoding section 3... Transmitting device or data optical signal sending section 4... Transmission line or fiber 5... Receiving device 7... Decoding device or parallel decoding section 20. ...control device or receiving section control circuit section 30...
Transmitting data line 40...Receiving data line Representative patent attorney Junnosuke Nakamura - ↑\? (talented

Claims (1)

[Claims] 1. In optical parallel transmission, in which constituent bits of data are encoded in a required form, this code is optically transmitted in parallel via an optical fiber transmission path, and data is reproduced by decoding, the original The feature is that the data is encoded to generate an error detectable code for each of a plurality of bits, the error detectable codes are optically transmitted in parallel, and the original data is reproduced by decoding and the error bit position is specified. Optical parallel transmission method. 2. In optical parallel transmission, in which the constituent bits of data are encoded into the required form, this code is optically transmitted in parallel via an optical fiber transmission path, and the data is recovered by decoding, each multiple bits are encoded from the original data. Encoding is performed to generate an error-detectable code, the error-detectable code is optically transmitted in parallel, and further decoding is performed to reproduce the original data, specifying the error bit position, and detecting the fault from the error bit position specification information. An optical parallel transmission method characterized by processing. 3. A patent claim characterized in that the failure processing based on the error bit position designation information is performed by determining that a failure has occurred in the transmission path corresponding to the bit position where errors have occurred a predetermined number of times or more within a certain time. The optical parallel transmission method according to item 2. 4. When data is not being transmitted, dummy data is transmitted on the transmission path corresponding to all code bits so that the bits are not fixed to 0 or 1. The optical parallel transmission method described.