JPS61145934A - Decoder for run length limited code - Google Patents

Abstract

PURPOSE:To attain miniaturization by dividing an n bits into plural blocks, decoding each divided block tentatively and decoding a data word based on the combination of results to decrease the capacity of a ROM. CONSTITUTION:The code word unit is kept for a recovered code word by a serial/parallel converter 1 and a 12-bit D flip-flop 2(DFF) at first. Then the head bit of the code word stored in the DFF2 is fed to one input of an exclusive OR gate 4 via an inverter 3 and an output of the DFF2 is given as it is to the other input. Then the high-order and low-order 6 bits in the code word of a table pattern appearing at the output terminal of the gate 4 are given respectively to the address terminal of ROMs 5, 6. Finally, a 2-bit value R1 being an output of the ROM5 and a 4-bit value R2 being an output of the ROM6 are given to a ROM7, then a data word corresponding to the inputs R1 and R2 appears and it is an output of the decoder.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a run length limited device used for transmitting and recording digital signals.
It relates to a code decoding device.

2. Description of the Related Art When high-density recording of digital data on magnetic tapes, disks, etc., run-length limited codes (hereinafter referred to as RLL codes) are usually used.

An RLL code is a code that limits the number of consecutive bits of the same binary value to d or more and less than d.
The LL code is obtained by converting an m-bit data word (pit length T) into an n-bit code word larger than m.

In the RLL code obtained in this way, the length required to identify one pit is the detection window width) 7, , = -'r
, the minimum inversion interval "ylin = d" Tas.

Generally, in a recording/reproducing system, waveform interference occurs because high frequency components are blocked. In order to suppress this waveform interference, it is desirable that the Tylin is large.

Further, in order to suppress the influence of time axis fluctuations such as waveform interference and jitter, it is better that the above T(I) be large, and in addition, it is desirable that the above T(I) be small in order to obtain a self-clock function. .

Conventionally, various RLL codes have been developed from the above viewpoint.

On the other hand, when using an RLL code, a decoding device that restores an n-bit code word to an m-bit data word is essential on the receiving or reproducing side.

In a conventional decoding device that directly restores an n-bit code word to an m-bit data word, the memory capacity v1 when a ROM is used for decoding is v,=2n-m. However, the memory capacity V′ essentially required for decoding is v′=2m
-m, so if the memory usage efficiency E is defined by equation (1), the difference between n and m IC: v2/V, = 2m
−” −・−−−−−− As (1) becomes larger, the memory usage efficiency deteriorates exponentially.

For example, as shown in Table 1, d=3. ni=7, m=5.1
m=:12. In the case of an RLL code where TtIJ=0.417T, the following equation is obtained.

First, it is shown that the RLL code in Table 1 satisfies the nearness at d:3. As is clear from Table 1, there are 32 12-bit code words satisfying d=3 and =y, which can have a one-to-one correspondence with 32 (:25) data words each consisting of 6 bits.

In addition, Table 1 shows the code words of the table pattern starting with Fil,
A back pattern in which all 1's in the front pattern are replaced with 0's and all 0's are replaced with 1's is also shown, and the correspondence between these code words and data words is as follows.
correspond to the word. The front pattern and back pattern are selected as follows.

The number E of consecutive bits of the same binary value at the left end of the code word is 2.
Then, F=Q, if 3 or more, F=1. If the value F and the number r of consecutive bits of the same binary value at the right end of the code word are 2 or less, then ==0.3 or more, then z=1. Using the value E, which indicates the last bit of the code word, and the value LB, which indicates the last bit of the code word, set Y20 to make the code word a front pattern, and Y20 to make a back pattern.
Let Y be the value that makes =1.

Chapter 1 Table Here, E of the code word sent out one time ago is E.

Assuming that L and B are LB, and F of the code word to be sent from now is F2, front-back patterns are switched using the following equation (2) for the code word to be sent from now.

Y-LB,■(K,・F2)・・・・・・・・・
- (2) However, "■" represents exclusive OR, ゛・" represents logical product, and "-" represents negation.

For example, &1 in Table 1 is used as the previous code word sent.
Assume the codeword of the table pattern. At this time, E = 1.
LB,=1. Next, if the code word to be sent is the code word &2 in Table 1, then F221. Therefore, the code word to be sent from now on will be the back pattern 0
and As a result, as shown in FIG. 3, even if code words are connected, the number of consecutive bits of the same binary value will be 3 or more and 7 or less even at the underlined connection portion.

Similarly, for the connection between code words in Table 1, 1
As long as Equation (2) is followed, it can be seen that the connection part also always satisfies the restrictions of d==3 and d=7.

d shown in Table 1 above: 3, near, m=6+
When decoding an RLL code with n=12, according to the conventional general method, the capacity of the FIOM for decoding, V, is required to be v,=2.5::20480 bits.

Note that the value columns in Table 1 will be explained in Examples.

Problems to be solved by the invention As mentioned above, d=3, ni=7, m=5, n:
In a decoding device for an RLL code of =12, at most 32
All 12 bits are used to identify codewords of only one type. This causes the capacity of the ROM in the decoding device to become unnecessarily large.

Generally, when the codeword length n is increased, the above d.

It is known that either k or Tω can be improved.

However, due to the capacity of the ROM of the device, it is virtually impossible to use an RLL code where n is a dog.

Means for Solving the Problems In order to solve the above-mentioned problems, the present invention aims to reduce the capacity of the ROM in the decoding device. It is characterized by performing a two-step decoding operation: decoding and then decoding the data word based on the combination of the tentative decoding results.

Operation According to the above configuration, for example, an n-bit code word is divided into two blocks of n1 bits and n2 bits, as shown in FIG. Also, the number of bit patterns occurring in this block of n bits k p, (2''''''<
p, < 2Q1), n2 The number of bit patterns occurring in the human flow pattern is expressed as P2(2Q2-'<P2<
2Q2).

At this time, Pl appearing in a block of n1 bits
The 22 bit patterns appearing in a block of n2 bits can be distinguished from each other using the 92 bits.

Therefore, in this case, the n-bit codeword is Q, +Q2
They can be distinguished from each other by bits. At this time.

If the means for provisionally decoding the bit pattern of a block of n bits into Q, bits and the means for provisionally decoding the bit pattern of a block of n2 bits into 92 bits are both based on ROM, the total capacity of the ROM required for decoding v2 is given by the following equation (3).

V2:Q, -2' +Q2-2 town+m'',!Q++9
2) ,,, (3゜Generally, an n-bit code word is L
The town is divided into small blocks (1kui<h
・,Σn11=1=n) If the number of bit patterns appearing in the focused block is P, (2(Qi)-'< p, <2''), these 21 bit patterns can be distinguished from each other by Q, bits. , Therefore, the total capacity of the ROM in the decoding device is expressed by equation (4).

Therefore, when Vb<m·2n, the capacity of the ROM in the decoding device becomes smaller than in the conventional case. The first term in equation (4) is the capacity of the ROM required for temporary decoding.

This is because the second term in equation (4) is the capacity of the ROM required for final decoding.

The effect of reduction is small.

On the other hand, Pl bit patterns appearing in a block of ni bits can be distinguished from each other by Qt bits, but
In order to make the information of Q and bits more effective, it is desirable that Pi be a value as close to a power of 2 as possible.

To summarize, the following m, (fil is a guideline for dividing an n-bit code word.

(iD Pi z2'' Example) Next, using an example, it will be shown in detail that the present invention can reduce the total capacity of the ROM required for a decoding device compared to the conventional one, and can also be done easily.

The RLL code used in this example is d:3 shown in Table 1.
, near , m=5 and n=12, RLL in brackets
The code word length of the code is n=12, in this example n=1
2 into two blocks, n,=6 and n2=6.

At this time, the bit pattern appearing in the first block of n=6 bits and the bit pattern appearing in the second block of n226 bits are as shown in Table 2.

(Leaving space below) Table 2 As is clear from Table 2, the number of bit patterns in the first block, P, is 4, and the number of bit patterns in the second block, P2, is 13, so Q1=2eQ2=4. Therefore, each bit pattern in Table 2 is expressed as Qi (i = 1
, 2) Value expressed using bits (hexadecimal notation)
are R, , R2 in Table 2.

Therefore, the total capacity of ROM required for the decoding device is expressed by the formula (3
) Twist V2: 2-2'+ 4-2' + 5-2' near 04 Hit. This is approximately 1% compared to the ROM capacity V, = 20480 bits required for a conventional decoding device.
/29.

Note that for a back pattern input, since the first bit of the code word is 0, it can be easily detected that it is a back pattern. Therefore, in the case of a back pattern, it is changed back to a front pattern before being sent to the decoding device of the present invention.

Next, the circuit configuration of the decoding device of the present invention will be explained in detail using the block diagram shown in FIG.

First, the reproduced code words are held in units of code words by a serial-parallel converter 1 ('S/P) and a 12-bit D flip-flop 2 (DFF). And D
The first bit of the 12-bit code word held in the flip-flop 2 is sent through an inverter 3 to one input terminal of 12 two-man exclusive OR gels 4.
The output of the D flip-flop 2 is directly sent to the other input terminal of the two two-man exclusive OR gates 4.

By doing this, 12 two-man exclusive OR gates 4
The codeword of the table pattern always appears in the output.

Then, among the code words of the table pattern appearing at the output terminals of the twelve two-man exclusive OR gates 4.

The upper 6 bits, ie, the first block of the code word, are sent to the address terminal of ROM 6, while the lower 6 bits, ie, the second block of the code word, are sent to the address terminal of iROMe.

As a result, a 2-bit value R1 corresponding to the 6 bits of the input appears at the output of the ROM 6, and a 4-bit value R2 corresponding to the 6 bits of the input appears at the output of the ROM 6.

Finally, FT and R2 are R2, which is 6 bits in total.
When sent to OM7, its output is shown in the Values section of Table 1.

A data word corresponding to inputs R1 and R2 appears, which becomes the output of the decoding device.

As shown above, the circuit configuration of this embodiment is extremely simple, and has the advantage that the ROM capacity is significantly smaller than that of the conventional circuit, making it extremely useful in practice.

Note that the present invention is effective not only for the RLL code used in this embodiment but also for all RLL codes, and the code word block division is not limited to two blocks, but can be divided into three or more blocks to reduce the total ROM capacity. Not only can the reduction effect be maintained, but for RLL codes with long codeword lengths, dividing into three or more has an unprecedented effect of reducing the total ROM capacity.

Effects of the Invention As described in detail above, the present invention provides an RLL code decoding device that divides an n-bit code word into a plurality of blocks, temporarily decodes each divided block, and uses the result of the temporary decoding. By performing a two-step decoding operation in which the final decoded value is obtained using a simple circuit configuration, the total ROM capacity required for decoding can be significantly reduced compared to the conventional method1.
for example.

RLL with d=3, ni=7, m=5, n=12
For codes, the total ROM capacity is reduced to about 1/1 compared to the conventional one.
It can be reduced to 29.

In this way, by using the run-length limited code decoding device according to the present invention, not only can the decoding device be made smaller than before, but also RLL codes with long code word lengths that are more suitable for high-density recording can be made smaller. It has extremely great practical effects, such as making it possible to use

In this specification, the effects of the present invention have been shown using the ROM capacity as one guideline, but in the decoding device, the ROM'f!
It goes without saying that the same effect can be obtained even when decoding is performed only with logic circuits without using this method.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a code word divided into two parts, FIG. 2 is a block diagram of a decoding circuit in an embodiment of the present invention, and FIG. 3 is an explanatory diagram of connections between code words. 1... Serial-parallel converter, 2...
...D flip-flop, 3...inverter,
4...Exclusive OR gate...5,6...
・ROM, 7...ROM.

Claims (8)

[Claims] (1) Convert an m-bit data word to an n-bit code word, and increase the number of consecutive bits of the same binary value in the bit string resulting from the connection of the converted n-bit code words to d or more k
In a run-length limited code decoding device that inversely converts an n-bit run-length limited code limited to the following into an m-bit data word, Σ^L_i_=_1n_i A dividing means divides into L blocks each having n_i bits that satisfies the relationship =n, a temporary decoding means temporarily decodes each divided block of n_i bits, and a final decoder uses the result of the temporary decoding. A decoding device for a run-length limited code, comprising: final decoding means for obtaining a decoding result. (2) A patent claim characterized in that when a code word starting with 1 is called a front pattern and a code word starting with 0 is called a back pattern, the dividing means also includes means for converting the code word to be decoded into a front pattern. A decoding device for a run-length limited code according to item 1. (3) The number of bit patterns P_i appearing in a block of n_i bits is 2^(Q
_i) When the value is greater than ^-^1 and less than or equal to 2^(Q_i), the temporary decoding means performs Q_ for input of n_i bits.
3. A run-length limited code decoding device according to claim 2, characterized in that the decoding device is means for generating an i-bit output. (4) The final decoding means takes all of the Q_i-bit provisional decoding outputs generated in each of the L blocks by the provisional decoding means as its input, and based on this input, the n-bits that are the decoding device input. 4. A run-length limited code decoding device according to claim 3, characterized in that the decoding device is means for generating a decoded value corresponding to a code word. (5) For i, n_i, Q_i and m, Q_i・2
^(n_i)<m・2^(Σ^L_i_=_1)^(Q
5. The run-length limited code decoding apparatus according to claim 4, wherein the n_i and i are selected so that the n_i and the P_i have a value close to a power of 2. (6) The dividing means consists of a serial-in/parallel-out shift register and a D flip-flop, the temporary decoding means is the n_i bit input Q_i bit output memory, and the final decoding means is Σ^L_i_=_1Q_
6. The run-length limited code decoding device according to claim 5, wherein the decoding device is a memory with i-bit input and m-bit output. (7) The run-length limited code decoding device according to claim 6, wherein the memory is a ReadOnlyMemory. (8) Regarding the run-length limited code of d=3, k=7, m=5 and n=12, the above L=2, n_1=
6. The run-length limited code decoding device according to claim 7, wherein n_2=6.