JPS6229330A - Decoding circuit - Google Patents

Abstract

PURPOSE:To eliminate the need for addition of a word synchronizing signal by providing a counter circuit sending a phase shift control pulse to a serial/ parallel conversion phase control pulse generating circuit caused when the rate of generation of violation pulses reaches a set threshold value or over. CONSTITUTION:A violation detection circuit 16 detects the presence of violation of a 5B6B code parallel signal 2f. When the violation exists, a violation pulse 2g is generated and sent to a violation pulse counter circuit 17 to count the pulse 2g and when the rate of generation reaches the set threshold value or over, a phase shift control pulse 2h is generated and sent to a serial/parallel conversion phase control pulse generating circuit 15. When the phase shift control pulse 2h is sent, the phase of a parallel expansion phase control pulse 2i is subject to 1 bit delay shift, and the operation above is repeated to take word synchronization. Thus, no addition of a word synchronization signal is required.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention applies a word synchronization method that does not require the addition of a word synchronization signal in digital transmission using an nBmB code as a transmission path code. This relates to a decoding circuit.

[Conventional technology]

A conventional decoding circuit is shown in FIG. 3, and an encoding circuit corresponding to the decoding circuit is shown in FIG. Note that the transmission line code used in these circuits is a 586B code.

First, the encoding circuit shown in FIG. 4 will be explained. Original signal 1a
is developed into a 4-bit parallel signal 1b by the serial/parallel conversion circuit 1, and the word synchronization signal 1c from the synchronization pattern generation circuit 2 is added to the signal 1b to make it into a 5-bit parallel signal, and then the 5B/6B code is generated. It is converted into a 586'B code parallel signal 1d by the conversion circuit 3, and then the parallel/serial conversion circuit 4
The signal is converted into a 586B code serial signal 1e as a transmission line code.

Next, a conventional decoding circuit will be explained using FIG. 3.

The 586B code serial signal 1f is converted into a parallel expansion phase control pulse (pulse divided by 1/6 of the basic clock frequency of the 586B code serial signal) from the serial/parallel conversion phase control pulse generation circuit 6 in the serial/parallel conversion circuit 5. , control pulse for 6-bit parallel expansion) Ig, the signal is expanded into a 586B code parallel signal 1h, which is converted into a 5-bit parallel signal 11 by the 6B/5B code conversion circuit 7, of which 4 bits are converted into a 5-bit parallel signal 11 by the parallel/serial conversion circuit 8. and is converted into the original signal 1j. At this time, the synchronization pattern detection circuit 9 compares the synchronization pattern with the word synchronization signal 1, and if they do not match, it is considered that the word synchronization has been lost, and the phase shift control pulse 11 is sent to the serial/parallel conversion phase control pulse generation circuit 6. send. When the serial/parallel conversion phase control pulse generation circuit 6 receives the parallel development phase shift control pulse 11, it delays the phase of the phase control pulse 1g by 1 bit.

Word synchronization is achieved by repeating such operations.

[Problem that the invention seeks to solve]

As described above, in the conventional word synchronization method, it is necessary to add a word synchronization signal to the encoding circuit. Also,
As a result, there was a drawback that the speed of the transmission line signal (5B 6 B code serial signal) was 1.5 times (6/4) that of the original signal.

[Means for solving problems]

In order to eliminate such drawbacks, the present invention provides a serial/parallel conversion circuit that expands an nBmB code serial signal into an nBmB code parallel signal, and a parallel expansion phase control pulse that is sent to the serial/parallel conversion circuit for this expansion. A serial/parallel conversion phase control pulse generation circuit that generates a violation pulse, a violation detection circuit that generates a violation pulse when there is a violation of the n B m B code parallel signal, and a violation detection circuit that generates a violation pulse when the violation pulse generation rate exceeds a set threshold. A violation pulse counting circuit is provided which sends a phase shift control pulse generated when the vibration occurs to a serial/parallel conversion phase control pulse generation circuit.

[Effect]

In the present invention, the addition of a word synchronization signal is unnecessary by detecting the presence or absence of a violation.

〔Example〕

An embodiment of a decoding circuit according to the present invention is shown in FIG. 1, and an encoding circuit corresponding to the decoding circuit is shown in FIG. Note that the transmission line code used in these circuits is a 586B code.

First, the code circuit shown in FIG. 2 will be explained. This encoding circuit is composed of a serial/parallel conversion circuit 11.5B/6B code conversion circuit 12 and a parallel/serial conversion circuit 13.

This encoding circuit differs from conventional ones in that it does not require the addition of a word synchronization signal.

Next, the decoding circuit shown in FIG. 1 will be explained. This decoding circuit is a serial/parallel conversion circuit 14. Series/parallel conversion phase control pulse generation circuit 15. Violation detection time i16.
The violation pulse counting circuit 17 is composed of a 6B/5B code conversion circuit 18 and a parallel/serial conversion circuit 19.

The decoding method from the 586B code serial signal 2e to the original signal 2 via the 5-bit parallel signal 2j is the same as the conventional one, but the word synchronization operation is different and is as follows. That is, the violation detection circuit 16 detects the presence or absence of a violation (violation of coding rules) in the 586B code parallel signal 2f.

If there is a violation (word synchronization may have occurred), a violation pulse 2g is generated and the violation pulse counting circuit 17
send to Violation pulse meter 111 line 17 counts violation pulses 2g, and the occurrence rate is determined by a set threshold value (this threshold value should be determined by considering the probability of violation occurrence when word synchronization is lost and the quality of the transmission path. -2), a phase shift control pulse 2h is generated and sent to the serial/parallel conversion phase control pulse generation circuit 15. In the serial/parallel conversion phase control pulse generation circuit 15, when the phase shift control pulse 2h is sent, the parallel expansion phase control pulse 21
The phase of is shifted by 1 bit delay. Word synchronization is achieved by repeating such operations.

Next, the 5B6B code will be explained. The nBmB code is intended for transparent transmission, and one type of it is the 586B code. The 586B code has the following characteristics.

■WD S (Word Digital Sum) is in the range of -2 to +2. WDS is a binary code “0”
When weighted as '-IJ and rlJ as "+1", 5
This is the sum of each bit code that makes up a B6B word (6 bits).

■Word terminal DSV (Digital Sum)
Variation-n) ranges from -2 to +2.

DSV means binary code ``0'' as 'IJ, rlJ as ``
It refers to the fluctuation range of the sum of code strings when +IJ is set.

■The DSV in bit units is in the range of -3 to +3.

When the 0 to 0 terms are disturbed for some reason (for example, a transmission path error), it is said that a coding rule violation has occurred. This violation is easily detectable.

〔Effect of the invention〕

As explained above, the present invention includes a serial/parallel conversion circuit that expands an nBmB code serial signal into an nBmB code parallel signal, and a serial/parallel conversion circuit that sends a parallel expansion phase control pulse to the serial/parallel conversion circuit for this expansion. A conversion phase control pulse generation circuit, a violation output circuit that generates a violation pulse when there is a violation of the nBmB code parallel signal, and a violation pulse generation circuit that generates a violation pulse when the violation pulse generation rate exceeds a set threshold. By providing a violation pulse counting circuit that sends phase shift control pulses to a serial/parallel conversion phase control pulse generation circuit, the presence or absence of a violation can be detected, making it unnecessary to add a word synchronization signal. ,Also,
There is an effect that the transmission line signal speed can be made 1.2 times (=615) the original signal speed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a decoding circuit according to the present invention, FIG. 2 is a circuit diagram showing an encoding circuit corresponding to this decoding circuit, and FIG. 3 is a circuit diagram showing a conventional decoding circuit. FIG. 4 is an encoding circuit diagram corresponding to this conventional decoding circuit. 14...Series/parallel conversion circuit, 15...Series/
Parallel conversion phase control pulse generation circuit, 16...Violation detection circuit, 17...Violation pulse counting circuit, 18...6B/5B code conversion circuit,
19...Parallel/serial conversion circuit.

Claims (1)

[Claims] In a decoding circuit for digital transmission using an nBmB code as a transmission path code, a serial/parallel conversion circuit expands an nBmB code serial signal into an nBmB code parallel signal, and a serial/parallel converter converts a parallel expanded phase control pulse for said expansion. a serial/parallel conversion phase control pulse generation circuit that sends out to the circuit; a violation detection circuit that detects the presence or absence of a violation of the nBmB code parallel signal and generates a violation pulse if there is a violation;
a violation pulse counting circuit that counts violation pulses and sends a generated phase shift control pulse to the serial/parallel conversion phase control pulse generation circuit when the incidence of violation pulses exceeds a set threshold; A decoding circuit characterized in that synchronization is established by delay-shifting the phase of a parallel expansion phase control pulse by one bit using a shift control pulse.