JPH0362641A - Auxiliary signal superimposing system - Google Patents

Abstract

PURPOSE:To limit a pulse width distortion of a decoded auxiliary signal within one bit of a main signal by converting information representing a change in the auxiliary signal into violation occurrence interval and sending the result. CONSTITUTION:A main signal input (a) inputted to a transmission section 1 is converted into a CMI code string by a CMI code conversion circuit 3. On the other hand, the leading of an auxiliary signal input (b) inputted to the transmission section 1 is detected by a leading detection circuit 4 and the trailing is detected by a trailing detection circuit 5. All n-bit, violation designation circuit 6 designates violation of n-bit interval with an auxiliary signal leading detection signal (e) of the circuit 4 and an m-bit violation designation circuit 7 designates the violation of m-bit of interval by using all auxiliary signal trailing detection signal (d) from the circuit 5 to form a violation designation pulse (e). The pulse (e) is inputted to the circuit 3 and violation is applied to the CMI code string of the main signal for the time slot of the pulse (e). Thus, a signal (f) subjected to violation corresponding to the change point of the input (b) is sent to the reception section 2.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention uses CMI (Code Mark) as a transmission code.
This is related to the auxiliary signal superimposition method in which line switching control signals, monitoring signals, and meeting or meeting signals are superimposed on the main signal when using Inversion) codes, especially when the r of the auxiliary signal is transmitted.
This invention relates to an auxiliary signal superimposition method that transmits lJ and rOJ in accordance with the violation occurrence interval of the CMI coding rule.

[Conventional technology]

Regarding the CMI code used as a transmission code, CMI
A general explanation will be provided with reference to FIG. 3, which is an explanatory diagram showing the general operation of the code.

Usually, binary codes are converted to CMI codes according to the following rules. In other words, the normal binary code (Fig. 3, 1(b)) is
0", the CMI code (Fig. 3 (C)) is "01", and when the normal binary code (Fig. 3 (b)) is "l", the CM
The I code (FIG. 3(C)) is converted into an alternating code of "OO" and "11". FIG. 3(&) is a clock pulse of a normal binary code (FIG. 3(b)).

In this CMI code (FIG. 3(C)), the method of causing a violation (CMI code rule violation) 't- is performed according to the following rule. In other words, the normal binary code (Fig. 3(b)) of the time slot in which all violations are performed is "0".
In this case, change “01” of CMI code (Figure 3 (C)) to “1”
0", and the binary code (Figure 3 1(b)) is "1".
In this case, the r00J& and "11" alternations are prohibited for that time, and the CMI code with violation (see Figure 3) is prohibited.
d)). The * mark in FIG. 3 indicates violation position a.

Conventionally, when superimposing and transmitting an auxiliary signal using the violation occurrence interval, the transmitting side samples all the auxiliary signals, and when the sampling output is "1", the violation specified position is set at the sampling time. slot position and n time slots (n) an integer of 1)
and when the sampling output is "O", the sampling time slot position and n time slot (m+
n, an integer of m≧1) is sent as the violation specified position, and on the receiving side, the CMI with an (n-1) bit interval is transmitted.
A common method has been to detect a code rule violation signal and a CMI code rule violation signal with an (m-1) bit interval, and to decode an auxiliary signal based on the detection results.

An example of a conventional auxiliary signal superimposition method is shown in FIG. 4 and will be described.

In the figure, 21 is a transmitting section, and this transmitting section 21 is a main signal (usually a binary code) that converts the input into a tiCMI code.
A code conversion circuit 23, a sampling circuit 24 that samples the auxiliary signal p, and this sampling circuit 24
When the sampled auxiliary signal q, which is the output of When the sampled auxiliary signal q is "1", a violation designation pulse is generated to perform a violation designation in the time slot after m (m is an integer of 1 or more other than n) bits after this time slot number. The circuit 25 is comprised of a circuit 25. Further, r indicates a violation designation pulse, and y indicates a clock pulse.

22 is a receiving section, and this receiving section 22 includes a CMI decoding circuit 26 which obtains a main signal (usually a binary code) output v from a transmission line signal (CMI code) U sent through the transmission line, and C
Detects violations at (n-1) bit intervals and (m-1) k'7 bit interval violations in the MI code string, and sends the violation detection output wt to the auxiliary signal decoding circuit 28. A detection circuit 2T,
It is comprised of an auxiliary signal decoding circuit 28 that decodes auxiliary signals. And, X indicates the auxiliary signal output, and y indicates the clock pulse f.

An auxiliary signal superimposing circuit constructed in this manner is described, for example, in Japanese Patent Application No. 164309/1982.

Figure 5 is a time chart of each part in Figure 4, (a
) shows the clock pulse y, (b) shows the auxiliary signal p, and (c) the sampled auxiliary signal q.
, (d) Hahaioration designated Hals r1 (,)
is the transmission line signal U, (f) is the violation detection output W
This is what is shown.

In FIG. 5, (a) to (b) represent the following meanings.

0) is rOJ when the sign Sn of the auxiliary signal human power p is "O"
, rlJ when rlJ.

(b) The sign of the sampled auxiliary signal q is "O"
When rllOJ, rloIJ when r I J.

←When the violation designation pulse r is rllOJ, there is a violation, and there is a violation at rloIJ.

) is "0" when a violation appears consecutively in the code of the transmission path signal (CMI code) U, and rlJ when a violation appears every other bit.

[Problem to be solved by the invention]

In the conventional auxiliary signal superimposition method described above, the auxiliary signal is sampled and a violation is specified based on the sampling result. Therefore, if the auxiliary signal is asynchronous with the main signal, the decoded auxiliary signal The frequency deviation of the signal output is determined by the sampling period, and if the sampling period is made smaller, the balance button of the transmission line signal, which is a feature of the CMI code, and the block synchronization when performing CMI decoding become difficult to pull in. Since the sampling period cannot be lower than a certain value, there is a problem in that the pulse width distortion of the auxiliary signal becomes large.

[Means to solve the problem]

The auxiliary signal superimposition method of the present invention uses CMI as a transmission path code.
A CMI code conversion circuit for converting a main signal into a t-cMI code on a transmitting side in a method of superimposing and transmitting an auxiliary signal on a main signal by performing a violation of the CMI code rule corresponding to an auxiliary signal using a code; A rising edge detection circuit that detects the rising edge of the auxiliary signal, a falling edge detection circuit that detects the falling edge of the auxiliary signal, and an output of the rising edge detection circuit that indicates the rising edge b' of the auxiliary signal. 9m (m ≧0.m'y
The receiving side consists of an m-bit violation specification circuit that specifies violation of the CMI code rule at bit intervals (n integers).

a CMI decoding circuit that obtains the original main signal from a received CMI code string; an n-bit violation detection circuit that detects a violation of the CMI code rule at n-bit intervals;
an m-bit violation detection circuit that detects a violation of the CMI code rule at bit intervals, and a CM at n-bit intervals in the n-bit violation detection circuit
The output is set to "1" by a signal indicating that a violation of the I code rule has been detected, and this indicates that the m-bit violation detection circuit has detected a violation of the CMI code rule with an m-bit interval. It is composed of an auxiliary signal decoding circuit that sets the output to "0" depending on the signal.

[Effect]

According to the present invention, information on changes in the auxiliary signal is converted into violation occurrence intervals and transmitted.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 is a block diagram of one embodiment of the auxiliary signal superimposition method according to the present invention. In the figure, 1 is a transmitting section and 2 is a receiving section.

3 is a CMI code conversion circuit that converts the main signal into a CMI code; 4 is a rising edge detection circuit that detects the rising edge D't of the auxiliary signal; 5 is a falling edge detection circuit that detects the falling edge of the auxiliary signal; 6 is the output of the rising edge detection circuit 4 which indicates the rising edge of the auxiliary signal! 7 is an n-bit violation designation circuit that performs all violation designations of the CMI code rule at bit intervals of (an integer of , ≥ O), and 7 is an output of the falling detection circuit 5 indicating the falling edge of the auxiliary signal, so that m<m≧0 ．． This is an m-bit violation designation circuit that designates a violation of the CMI coding rule at a bit interval (m"=an integer of n), and these circuits constitute the transmitting side.

8 is a CMI that obtains the original main signal from the received CMI code string
1 is a decoding circuit; 9 is an n-bit violation detection circuit that detects a violation of the CMI code rule with an n-bit interval; 10 is an m-bit violation detection circuit that detects a violation of the CMI code rule with an m-bit interval;
1 is set to the multi-output t-rlJ as a signal indicating that the n-bit violation detection circuit 9 has detected a violation of the CMI code rule with an n-bit interval, and the m-bit violation detection circuit 10 is set to the m-bit violation detection circuit 10. This is an auxiliary signal decoding circuit that sets the output to "0" in response to a signal indicating that a violation of the interval CMI coding rule has been detected, and these constitute the receiving side.

And, a indicates the main signal (usually binary code) input, b is the auxiliary signal input, C is the detection signal for the rising of the auxiliary signal, d is the detection signal for the falling of the auxiliary signal, e is the violation designation pulse, and f is the violation designation pulse. Transmission line signal (CMI code), g is main signal output, h
is an n-bit interval violation detection signal, t is an m-bit interval violation detection signal, j is an auxiliary signal output,
k indicates a clock pulse.

FIG. 2 is a time chart for the case of n=l and m=O to provide an explanation of the operation of FIG. is the auxiliary signal rising detection signal C1 (d) is the auxiliary signal falling detection signal d, (e) is the violation designation pulse e, (f
) indicates the transmission line signal f%(g) indicates the auxiliary signal output j.

Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIG. 2.

! First, the main signal (usually a binary code) input a input to the transmitter 1 is converted into a CMT code string by the CMI code conversion circuit 3.

On the other hand, the auxiliary signal inputted to the transmitter 1 (see Fig. 2)
(b)), the rising edge is detected by the rising edge detection circuit 4, and at the same time, the falling edge is detected by the falling edge detection circuit 5. Then, based on the auxiliary signal rising edge detection signal C (see FIG. 2(, )) of the rising edge detection circuit 4, the n-bit violation designation circuit 6 specifies violations at n-bit intervals, and the falling edge detection circuit The m-bit violation designation circuit 7 specifies a violation at m-bit intervals using the auxiliary signal fall detection signal d (see FIG. 2(d)) of 5, thereby generating the violation designation pulse e (FIG. 2<e >g light). This violation designation pulse e is input to the CMI code conversion circuit 3,
Violation is performed on the CMI code string of the main signal only in the time slot of the violation designation pulse e.

In this way, the transmission line signal (CMI code) f (see FIG. 2(f)) that has undergone a violation corresponding to the change point of the auxiliary signal is sent to the receiving section 2.

Next, in the receiving section 2, the transmission path signal (CMI code) f sent from the transmitting section 1 is sent to the CMI decoding circuit 8 and returned to the original main signal g (main signal output). At the same time, a transmission line signal (CMI code) f is sent to the n-bit violation detection circuit 9 and the m-bit violation detection circuit 10.

The n-bit violation detection circuit 9 detects violations at n-bit intervals in the transmission path signal (CMI code) f, and the m-bit violation detection circuit 10 detects violations at m-bit intervals. Perform detection. The auxiliary signal decoding circuit 11 sets the auxiliary signal output code (see FIG. 2 (g)) to erlJ based on the n-bit interval violation detection signal output from the n-bit violation detection circuit 9, and also sets the m-bit bio The auxiliary signal output jtr is generated by the m-bit interval violation detection signal 1 which is the output of the ration detection circuit 10.
By setting OJ, the original auxiliary signal is restored.

In Figure 2, (e), (he), and (g) represent the following meanings.

(E) indicates the violation position in the transmission path signal (CMI code) f.

(to) rlolJ at the rising point of the auxiliary signal input.

At the falling point, rllOJ.

(G) is set to rOJ when violations appear continuously in the code of the transmission path signal (CMI code) f;
When the presence of a violation appears in one bit, “l
”.

〔Effect of the invention〕

As explained above, the present invention converts the information in which the auxiliary signal has changed into the violation occurrence interval and transmits it, thereby eliminating the need for a sampling circuit and transmitting the asynchronous auxiliary signal by superimposing it on the main signal. Even when attempting to do so, the pulse width of the decoded auxiliary signal is distorted by
This has the effect that it can be reduced to less than one bit.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the auxiliary signal superimposition method according to the present invention, FIG. 2 is a time chart for explaining the operation of FIG. 1, and FIG. 3 is an explanatory diagram showing the general operation of the CMI code. , FIG. 4 is a block diagram showing an example of a conventional auxiliary signal superimposition method, and FIG. 5 is a time chart of each part applied to FIG. 4. 1... Transmitting section, 2... Receiving section, 3... CM
I code conversion circuit, 4... rise detection circuit, 5...
・Fall detection circuit, 6...n-bit violation designation circuit, T...m-bit violation designation circuit, 8...CMI decoding circuit, 9.e...n-bit violation detection circuit , 1G... m-bit violation detection circuit, 11... auxiliary signal decoding circuit.

Claims (1)

[Claims] In a method in which a CMI code is used as a transmission line code, a violation of the CMI code rule is performed in response to an auxiliary signal, and the auxiliary signal is superimposed on the main signal and transmitted, the transmitting side converts the main signal into a CMI code. A CMI code conversion circuit, a rise detection circuit that detects the rise of the auxiliary signal, a fall detection circuit that detects the fall of the auxiliary signal, and the output of the rise detection circuit that indicates the rise of the auxiliary signal m (m
≧0, m≠n (an integer of n) is configured with an m-bit violation specification circuit that specifies violation of CMI code rules at bit intervals, and the receiving side is a CMI that obtains the original main signal from the received CMI code string. a decoding circuit; an n-bit violation detection circuit that detects a violation of a CMI code rule with an n-bit interval; and an m-bit violation detection circuit that detects a violation of a CMI code rule with an m-bit interval; The output is set to "1" by a signal indicating that the n-bit violation detection circuit detects a violation of the CMI code rule with an n-bit interval, and the m-bit violation detection circuit detects a violation with an m-bit interval. An auxiliary signal superimposition method comprising an auxiliary signal decoding circuit that sets an output to "0" based on a signal indicating that a violation of a CMI coding rule has been detected.