GB1417325A - Method of indicating slippage during data transmission - Google Patents
Method of indicating slippage during data transmissionInfo
- Publication number
- GB1417325A GB1417325A GB718673A GB718673A GB1417325A GB 1417325 A GB1417325 A GB 1417325A GB 718673 A GB718673 A GB 718673A GB 718673 A GB718673 A GB 718673A GB 1417325 A GB1417325 A GB 1417325A
- Authority
- GB
- United Kingdom
- Prior art keywords
- signal
- check
- slippage
- signals
- sequence
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
- H04J3/073—Bit stuffing, e.g. PDH
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L1/00—Arrangements for detecting or preventing errors in the information received
Abstract
1417325 Digital transmission; synchronizing INTERNATIONAL STANDARD ELECTRIC CORP 14 Feb 1973 [14 Feb 1972] 7186/73 Heading H4P In a method of determining 'slippage' along a transmission line, a check signal is transmitted either along the same or different channel to the data, signal values differing in adjacent intervals in a determined manner which provides check on reception that the sequence is correct, any departure being indicative of slippage. A series of alternate 0 and 1 check signals are transmitted as additional bits parallel or serial to data items, i.e. bit, word, or block, the signals on reception being fed through a terminal E to flip-flop FF and one input of exclusive OR gate EO, also to a clock generator TG. The state of FF is changed by clock signals T which are synchronized with and have double frequency of check signals and may be derived from check signals. Output K<SP>1</SP> is shifted relative to input Ke by one clock unit and inverted. A slippage signal S appears only if a received signal is not in agreement with the inverted previous check signal. In an alternative arrangement, a cyclic sequence of +1, 0, -1 is used which are represented by 3 pairs of binary values developed by a circuit, Fig. 4 (not shown), the fourth pair not being used in the arrangement, but may be used for other purposes, not particularly disclosed. In Fig. 5, the check signal is applied to comparators V1, V2 also to clock generator TG whch generates signals for the expected period of slippage, and controls a counter Z; this delivers a sequence of signal elements RKS which correspond to, are synchronized, but may be out-of-phase with received check signals. Modulator M develops outputs n + 1, n - 1 which are compared in V1, V2 and in the event of no slippage, outputs do not appear at A, W. However, if there is erroneous repetition V1, V2 will have different values from the modulator output hence a slippage signal will appear on A, W.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE19722206968 DE2206968C3 (en) | 1972-02-14 | 1972-02-14 | Method for displaying a slip in data transmission |
Publications (1)
Publication Number | Publication Date |
---|---|
GB1417325A true GB1417325A (en) | 1975-12-10 |
Family
ID=5835953
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
GB718673A Expired GB1417325A (en) | 1972-02-14 | 1973-02-14 | Method of indicating slippage during data transmission |
Country Status (3)
Country | Link |
---|---|
DE (1) | DE2206968C3 (en) |
ES (1) | ES411569A1 (en) |
GB (1) | GB1417325A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985003181A1 (en) * | 1984-01-13 | 1985-07-18 | Telefonaktiebolaget Lm Ericsson | Apparatus for sychronizing pulse trains in a digital telephone system |
US5497377A (en) * | 1993-03-31 | 1996-03-05 | Mitsubishi Denki Kabushiki Kaisha | Communication system and method of detecting transmission faults therein |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5933468A (en) * | 1997-03-06 | 1999-08-03 | Telefonaktiebolaget L M Ericsson (Publ) | Continuous synchronization adjustment in a telecommunications system |
-
1972
- 1972-02-14 DE DE19722206968 patent/DE2206968C3/en not_active Expired
-
1973
- 1973-02-13 ES ES411569A patent/ES411569A1/en not_active Expired
- 1973-02-14 GB GB718673A patent/GB1417325A/en not_active Expired
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO1985003181A1 (en) * | 1984-01-13 | 1985-07-18 | Telefonaktiebolaget Lm Ericsson | Apparatus for sychronizing pulse trains in a digital telephone system |
GB2163028A (en) * | 1984-01-13 | 1986-02-12 | Ericsson Telefon Ab L M | Apparatus for sychronizing pulse trains in a digital telephone system |
US5497377A (en) * | 1993-03-31 | 1996-03-05 | Mitsubishi Denki Kabushiki Kaisha | Communication system and method of detecting transmission faults therein |
GB2277237B (en) * | 1993-03-31 | 1998-01-21 | Mitsubishi Electric Corp | Communication system and method of detecting transmission faults therein |
Also Published As
Publication number | Publication date |
---|---|
DE2206968C3 (en) | 1978-10-05 |
DE2206968A1 (en) | 1973-08-23 |
DE2206968B2 (en) | 1976-01-08 |
ES411569A1 (en) | 1976-01-01 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PS | Patent sealed | ||
435 | Patent endorsed 'licences of right' on the date specified (sect. 35/1949) | ||
PCNP | Patent ceased through non-payment of renewal fee |