JP2861533B2 - In-device transmission system for digital data - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an in-device transmission system for digital data, and more particularly to a data transmission system in a digital device which receives digital input signals having different signal formats, converts them into a predetermined format, and performs digital signal processing. .

[0002]

2. Description of the Related Art Conventionally, this type of digital signal transmission method in a device, particularly in a digital signal transmission device, collectively processes digital signals of different speeds (formats are naturally different) input from an interface unit with the outside of the device. Used for transmission to the signal processing unit.

FIG. 3 is a system block diagram showing an example of such a digital signal transmission system, and FIG. 4 shows an example of the signal format. In both figures, (A),
3B correspond to each other. In the system configuration of FIG. 3A, the signal format of FIG. 4A is used, and in the system configuration of FIG. 3B, the signal format of FIG. 4B is used. Shall be.

3 (A) and 3 (B), an external signal is received by an interface section 1A or 1B and is format-converted.
6a to 16c. The digital signal is input to the digital signal processing unit 2 via the connector 17, and the two types of interface units 1A corresponding to the two types of digital signals are supplied to the common digital processing unit 2.
And 1B, and converts these into format signals that match the signal lines 16a to 16c of the connectors 15 and 17 of the common digital signal processing unit 2, respectively.

First, the case of FIGS. 3A and 4A will be described. The interface unit 1A is provided with three identical interface boards 13a to 13c. Each of these interface boards 13a to 13c receives 8-bit parallel digital signals 27a to 27c at a certain speed from outside the apparatus, and receives these 8-bit parallel digital signals 28a to 28c.
Respectively, to the conversion lines 14a to 14c. (Note that FIG. 4
In the example of (A), the input is output as it is without performing format conversion, but speed conversion may be performed. In this case, the input time slot T10 is converted to T10 ',
The speed after this conversion is Fbps).

[0006] The three sets of converted 8-bit parallel digital signals 28a to 28c are transmitted to the digital signal processing unit 2 via a 24-pin connector 15 and signal lines 16a to 16c, respectively.

In the processing section 2, three sets of 8-bit parallel signals of speed F input via the connector 17 are multiplexed by the multiplexing section 18 to form an 8-bit parallel signal 29 of 3 Fbps. Then, the input A is selected by the selector 19 and processed by the processing unit 9.

Next, if the input digital signal is an 8-bit parallel digital signal as shown by a signal 30 in FIG. 4B, the interface section 1A in FIG. Is used and inserted into the connector 15.

In this case, FIGS. 3B and 4B
Will be described with reference to FIG. The interface section 1B has one interface board 20, and the input signal 27a shown in FIG.
An input signal 30 having a speed three times as high as .about.27c is input.

The input signal 30 is transmitted to the interface board 20
The line 14c is converted by the
(In this case, one 8-bit line may be used.) In this case, the speed of the 8-bit parallel signal is 3
Fbps.

The 3 Fbps 8-bit parallel signal 31 on the line 14 c is input to the digital signal processor 2 via the connector 15, the line 16 c and the connector 17.

In this processing unit 2, the input B
Is selected, the processing is directly performed by the signal processing unit 9.

In such a conventional system, 8 × 3 = 24 output terminals of the interface units 1A and 1B are required.
Therefore, when signals are input to the digital signal processing unit 2 from the N interface units, the number of pins of the connector 7 of the processing unit 2 is required to be 24 × N, resulting in an increase in the number of pins. There is.

[0014]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a digital data in-device transmission system capable of preventing an increase in the number of connector pins in a digital signal processing section and enabling the transmission of different format digital signals within the device with a small number of pins. To provide.

[0015]

The digital data transmission system according to the present invention receives a b-bit (b is an integer of 2 or more) parallel signal of a predetermined speed as an input, and outputs the first to m-th bits of the b-bit parallel signal. m is b / n (n is 2 or less)
The natural number obtained by rounding up the above natural number) is set as the first time slot of the m-bit parallel signal, the (m + 1) th bit to the second mth bit are set as the second time slot of the m-bit parallel signal, and the (m (n−1) ) +1) bit to b-th
The bits are the n-th time slot of the m-bit parallel signal, and when there is a remainder in these time slots, n first time slots for performing format conversion for inserting empty bits are used.
Interface means, and a digital signal having a speed n times the predetermined speed and having a b-bit parallel signal inserted in each of the first to n-th time slots is input to each of these b-bit parallel signals. Second interface means for performing the same conversion as the format conversion of the first interface means, and the first interface means or the outputs of the n first interface means or the first interface means To n-th time slots each include format conversion means for performing format reverse conversion for inserting the corresponding b-bit parallel signal, respectively.

[0016]

Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a system block diagram of an embodiment of the present invention, and FIG. 2 shows an example of the signal format. Also in this case, both figures (A) and (B) correspond respectively.

1A and 2A, the interface unit 1A is provided with three identical interface boards 3a to 3c. These interface boards 3a ~
3c receives 8-bit parallel digital signals 21a to 21c at a certain speed from outside the apparatus, converts them into 3-bit parallel signals 22 having a speed three times as high as 3 bits, respectively.
The signals are output to the signal lines 4a to 4c formed of bits, respectively.

Regarding the interface board 3a,
Bit 1 of 8-bit parallel signals 1-1 to 1-8
1 to 1-3 are assigned to the first time slot T1, bits 1-4
To 1-6 in the second time slot T2, bits 1-7 to
1-8 are inserted into the third time slot T3, respectively.
It performs speed conversion.

Incidentally, the portions shown empty can be used arbitrarily, and the same applies to the other interface boards 3b and 3c.

If the speed of the input digital signal is the same as that of the conventional example, the converted 3-bit parallel signal speed is 3F.
bps, and these three 3-bit signals 22 which are 4
4c are signal lines 6a to 6c via a 9-pin connector 5.
Are applied to the connector 7 of the digital signal processing unit 2 through

In the processing unit 2, each 3-bit parallel signal input from the connector 7 is format-converted by the format conversion unit 8. The signal rate in this case does not change, empty bits are removed and each time slot T1
To T3 are 8-bit parallel signals 1-1 to 1-8,
2-1 to 2-8, 3-1 to 3-8 are inserted, and the signal 23
Is obtained.

The signal 23 is input to the signal processing section 9 to perform signal processing.

Next, the case of FIGS. 1B and 2B will be described. In this case, the interface unit 1B has one interface board 10, and its digital input signal 24 has three times the speed of the previous input signals 21a to 21c.

The digital input signal 24 has eight bits of bits 1 to 8 in the first time slot T1, eight bits of bits 9 to 16 in the second time slot T2, and bits 17 to 24 in the third time slot T3. This is a format in which 8 bits are inserted.

The input signal 24 is transmitted to the interface board 10
Is converted into a 9-bit parallel signal 25 having a speed of 3 Fbps, each of which is a 3-bit line 4a.
To 4c.

The conversion processing in the interface board 10 is the same as that in the interface boards 3a to 3c in FIG.

The 9-bit parallel signal 25 thus obtained is transmitted through the connector 5 to the signal lines 6a to 6
The signal is input to the connector 7 via the terminal c and applied to the digital signal processing unit 2.

The processing section 2 performs exactly the same processing as in FIGS. 1A and 2A.

With this arrangement, digital signals having different formats can be transmitted in the apparatus using the conventional 24-pin to 9-pin connectors 5 and 7, and the same processing can be performed in the digital signal processor 2. Can be performed.

In the above embodiment, the case where the number of parallel bits of the input signal is b = 8 and the number of converted time slots is n = 3 is shown, but the description can be generally made as follows.

The interface boards (3a to 3c) receive a b-bit parallel signal as input, and receive the first parallel signal.
Bit to the m-th bit (m is a natural number obtained by rounding up b / n (n is a natural number of 2 or more )) as the first bit of the m-bit parallel signal.
(M + 1) -th to (m) -th bits are used as the second time slots of the m-bit parallel signal,
Further, the (m (n-1) +1) th to b-th bits are used as the n-th time slot of the m-bit parallel signal, and when there is a remainder in each of these time slots, format conversion for inserting an empty bit is performed. is there.

The interface board (10) has n times the speed of the input signals of the interface boards 3a to 3c, performs the same format conversion as those of the interface boards 3a to 3c, and further converts the first mn bits after the conversion. Data of mn
The first to m-th bits of the bit parallel data, the second mn-bit data are the (m + 1) th to the second m-th bits of the mn-bit parallel data, and the n-th mn-bit data is the mn-bit parallel data ( m (n-
The conversion from 1) +1) bits to the mn-th bit is performed.

Then, the same output as the interface boards 3a to 3c or the output of one interface board 10 is input to the digital signal processor 2.

[0034]

As described above, according to the present invention, there is an effect that digital signals of different formats can be transmitted in a device with a small number of pins and signal lines.

[Brief description of the drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a format diagram of each signal according to the embodiment of the present invention.

FIG. 3 is a block diagram of a conventional in-device transmission system.

FIG. 4 is a format diagram of each conventional signal.

[Explanation of symbols]

 1A, 1B interface unit 2 digital signal processing unit 3a-3c, 10 interface panel 4a-4c, 6a-6c signal line 5,7 connector 8 format conversion unit 9 signal processing unit

Claims (1)

(57) [Claims] 1. A b-bit (b is an integer of 2 or more) parallel signal of a predetermined speed is input, and a first bit to an m-th bit (m is b / n (n is 2 or more) of the b-bit parallel signal is input.
The natural number obtained by rounding up the above natural number) is set as the first time slot of the m-bit parallel signal, the (m + 1) th bit to the second mth bit are set as the second time slot of the m-bit parallel signal, and the (m (n−1) ) +1) bit to b-th
The bits are the n-th time slot of the m-bit parallel signal, and when there is a remainder in these time slots, n first time slots for performing format conversion for inserting empty bits are used.
Interface means, and a digital signal having a speed n times the predetermined speed and having a b-bit parallel signal inserted in each of the first to n-th time slots is input to each of these b-bit parallel signals. Second interface means for performing the same conversion as the format conversion of the first interface means, and the first interface means or the outputs of the n first interface means or the first interface means A digital data in-device transmission system, comprising format conversion means for performing format reverse conversion for inserting the corresponding b-bit parallel signal into each of the time slots from the first to the nth time slot.