JPH0583234A - In-equipment transmission system for digital data - Google Patents

Abstract

PURPOSE:To reduce the number of connector pins in a signal processing section and to send signals of different kind in the equipment by allowing an interface section to convert a signal in parallel bit number (b) into a signal of time slot number (n). CONSTITUTION:Interface panels 3a-3c of the same configuration in an interface section IA receive an 8-bit parallel digital signal at a prescribed speed from the outside of the equipment, convert the signal into a 3-bit parallel signal having a speed three times the speed of the 8-bit parallel digital signal and sends the result to lines 6a-6c. The signal speed after the conversion is 3Fbps and the signal is fed to a connector 7 of a digital signal processing section 2 through signal lines 6a-6c via a 9-pin connector 5. The processing section 2 applies format conversion 8 to the input signal. In this case, the signal speed is unchanged and an idle bit is eliminated and an 8-bit parallel signal is inserted respectively to three time slots and the signal is processed by a signal processing section 9. An interface panel 10 of an interface section 1B implements format conversion to obtain a 9-bit signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system for transmitting digital data in a device, and more particularly to a data transmission system in a digital device for receiving digital input signals having different signal formats and converting them into a predetermined format for digital signal processing. ..

[0002]

2. Description of the Related Art Conventionally, this type of in-device transmission system for digital signals collectively processes digital signals of different speeds (formats are naturally different) input from an interface section with the outside of the device in a digital signal transmission device. It is used for the purpose of transmitting to the signal processing unit.

FIG. 3 is a system block diagram showing an example of such a digital signal transmission system, and FIG. 4 shows an example of its signal format. In both figures, (A),
3B corresponds to each other, and the signal format of FIG. 4A is used in the system configuration of FIG. 3A and the signal format of FIG. 4B is used in the system configuration of FIG. 3B. I shall.

In FIGS. 3A and 3B, a signal from the outside is received by the interface unit 1A or 1B and is converted in format, and this is converted through the connector 15 into the signal line 1.
6a to 16c. Then, it is adapted to be inputted to the digital signal processing section 2 via the connector 17, and two kinds of interface sections 1A corresponding respectively to two kinds of digital signals with respect to the common digital processing section 2.
And 1B, and these are converted into format signals that match the signal lines 16a to 16c of the connectors 15 and 17 of the common digital signal processing unit 2, respectively.

First, the case of FIGS. 3A and 4A will be described. The interface unit 1A is provided with three identical interface boards 13a to 13c. These interface boards 13a to 13c respectively receive 8-bit parallel digital signals 27a to 27c of a certain speed from the outside of the apparatus, and receive these 8-bit parallel signal 28a to 28c.
To the conversion lines 14a to 14c, respectively. (Note that FIG.
In the example of (A), the format conversion is not performed and the input is output as it is, but the speed conversion may be performed. In this case, convert the input time slot T10 to T10 ',
The speed after this conversion is Fbps).

The three sets of 8-bit parallel digital signals 28a to 28c after conversion are transmitted to the digital signal processing section 2 via the 24-pin connector 15 and the signal lines 16a to 16c, respectively.

In the processing unit 2, three sets of 8-bit parallel signals of speed F input through the connector 17 are multiplexed by the multiplexing unit 18 to form an 8-bit parallel signal 29 of 3 Fbps. Then, the selector 19 selects the input A and the processing unit 9 processes it.

Next, if the input digital signal is an 8-bit parallel digital signal as shown by the signal 30 in FIG. 4B, the interface section 1A in FIG. The interface unit 1B of is used and is inserted into the connector 15.

In this case, FIG. 3 (B) and FIG. 4 (B)
Will be described with reference to. The interface unit 1B has one interface board 20, and the input signal 27a of FIG.
An input signal 30 having a speed three times higher than .about.27c is input.

This input signal 30 is transmitted to the interface board 20.
Is converted by the line 14c in the format of the signal 31
(In this case, one 8-bit line may be used). In this case, the speed of the 8-bit parallel signal is 3
It is Fbps.

The 3 Fbps 8-bit parallel signal 31 on the line 14c is input to the digital signal processing unit 2 via the connector 15, the line 16c, and the connector 17.

In the processing section 2, the input B is input to the selector 19.
By selecting, the processing is directly performed by the signal processing unit 9.

In such a conventional system, 8 × 3 = 24 output terminals are required for the interface units 1A and 1B.
Therefore, when signals are input to the digital signal processing unit 2 from N interface units, the number of pins of the connector 7 of the processing unit 2 needs to be 24 × N, which causes an increase in the number of pins. There is.

[0014]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an in-device transmission system for digital data which prevents an increase in the number of connector pins in a digital signal processing unit and enables in-device transmission of different format digital signals with a small number of pins. Is to provide.

[0015]

The digital data transmission system in a device according to the present invention receives a b-bit (b is an integer of 2 or more) parallel signal of a predetermined speed as an input, and the first bit to the m-th bit (b-bit parallel signal). m is a natural number obtained by rounding up b / n (n is a natural number) as the first of the m-bit parallel signals.
A time slot, the (m + 1) th bit to the 2nd mth bit are the second time slot of the m-bit parallel signal, and the (m (n-1) +1) th bit to the bth bit are the nth time of the m-bit parallel signal. Slots, and n first interface means each performing format conversion for inserting a null bit when there is a remainder in these timeslots, and the first to nth speeds which are n times the predetermined speed. A digital signal in which a b-bit parallel signal is inserted is input to each of the time slots of the second slot, and the same format conversion of the first interface means is performed on each of these b-bit parallel signals. An interface means and an output of the n first interface means or an output of the second interface means, Characterized in that to each of the al n-th time slot and a format converting means for performing said corresponding b-bit parallel signals respectively insertion format inverse transform to.

[0016]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a system block diagram of an embodiment of the present invention, and FIG. 2 shows an example of its signal format. Also in this case, both figures (A) and (B) correspond to each other.

In FIGS. 1A and 2A, the interface section 1A is provided with three identical interface boards 3a to 3c. These interface boards 3a-
3c receives 8-bit parallel digital signals 21a to 21c of a certain speed from the outside of the device, converts them into a 3-bit parallel signal 22 having a triple speed, and outputs 3
It outputs to each of the signal lines 4a to 4c composed of bits.

The interface board 3a will be described.
Bit 1 of 8-bit parallel signals 1-1 to 1-8
1 to 1-3 in the first time slot T1 and bits 1 to 4
~ 1-6 in the second time slot T2, bits 1-7 ~
Insert 1-8 into the third time slot T3,
The speed conversion is performed.

It should be noted that the portions shown as empty can be arbitrarily used, and the same applies to the other interface boards 3b and 3c.

If the speed of the input digital signal is the same as that of the conventional example, the converted 3-bit parallel signal speed is 3F.
bps, and these three 3-bit signals 22 are 4a-
4c is a signal line 6a to 6c via the 9-pin connector 5
Are applied to the connector 7 of the digital signal processing unit 2 through the respective.

In the processing section 2, each 3-bit parallel signal input from the connector 7 is format-converted by the format conversion section 8. The signal rate in this case does not change, empty bits are removed and each time slot T1
To T3, 8-bit parallel signals 1-1 to 1-8,
2-1 to 2-8 and 3-1 to 3-8 are inserted, and signals 23
Is obtained.

This signal 23 is input to the signal processing unit 9 and signal processing is performed.

Next, the case of FIGS. 1B and 2B will be described. In this case, it is assumed that the number of interface boards 10 of the interface section 1B is one, and that the digital input signal 24 has a speed three times that of the previous input signals 21a to 21c.

The digital input signal 24 has 8 bits of bits 1-8 in the first time slot T1, 8 bits of bits 9 to 16 in the second time slot T2, and bits 17 to 24 in the third time slot T3. This is a format in which 8 bits are inserted.

This input signal 24 is the interface board 10
The format is converted into a 9-bit parallel signal 25 with a speed of 3 Fbps, and each is a 3-bit line 4a.
To 4c.

The conversion processing in this interface board 10 is the same as that of the interface boards 3a to 3c in FIG.

The 9-bit parallel signal 25 thus obtained is provided on the signal lines 6a to 6 through the connector 5 in units of 3 bits.
It is input to the connector 7 via c and applied to the digital signal processing unit 2.

This processing unit 2 performs the same processing as that shown in FIGS. 1 (A) and 2 (A).

By doing so, it becomes possible to transmit digital signals having different formats in the apparatus by using the conventional 24-pin to 9-pin connectors 5 and 7, and also in the digital signal processor 2 to perform the same processing. Will be able to do.

In the above embodiment, the number of parallel bits of the input signal is set to b = 8, and the number of converted time slots is set to n = 3. However, it can be generally described as follows.

The interface boards (3a to 3c) receive the b-bit parallel signal as an input, and receive the first parallel signal.
The bit to the m-th bit (m is a natural number obtained by rounding up b / n (n is a natural number)) is set as the first time slot of the m-bit parallel signal, and the (m + 1) th bit to the 2m-th bit are the second time of the m-bit parallel signal. Time slot, and then (m
The (n-1) +1) th bit to the bth bit are used as the nth time slot of the m-bit parallel signal, and when there is a surplus in each of these time slots, format conversion is performed to insert an empty bit.

The interface board (10) has n times the speed of the input signals of the interface boards 3a to 3c, performs the same format conversion as those of the interface boards 3a to 3c, and further converts the first mn bit. Data of mn
The first to m-th bits of the bit parallel data, the second mn-bit data of the mn-bit parallel data to the (m + 1) -th to the 2m-th bit, and the n-th mn-bit data of the mn-bit parallel data to the ( m (n-
Conversion from the 1) +1) th bit to the mnth bit is performed.

Then, n outputs which are the same as the interface boards 3a to 3c or one output from the interface board 10 are input to the digital signal processing section 2.

[0034]

As described above, according to the present invention, there is an effect that digital signals of different formats can be transmitted within a device with a small number of pins and signal lines.

[Brief description of drawings]

FIG. 1 is a system block diagram of an embodiment of the present invention.

FIG. 2 is a format diagram of each signal according to the embodiment of the present invention.

FIG. 3 is a block diagram of a conventional in-device transmission system.

FIG. 4 is a format diagram of each conventional signal.

[Explanation of symbols]

 1A, 1B interface unit 2 digital signal processing unit 3a to 3c, 10 interface board 4a to 4c, 6a to 6c signal line 5, 7 connector 8 format conversion unit 9 signal processing unit

Claims (1)

[Claims] 1. A b-bit (b is an integer of 2 or more) parallel signal having a predetermined speed is input, and the first bit to the m-th bit (m is b / n (n is a natural number) are rounded up. Natural number) is the first of the m-bit parallel signals
A time slot is used, the (m + 1) th bit to the 2nd mth bit are the second time slot of the m-bit parallel signal, and the (m (n-1) +1) th bit to the bth bit are the nth time of the m-bit parallel signal. Slots, and n first interface means each performing format conversion for inserting a null bit when there is a remainder in these timeslots, and the first to nth speeds which are n times the predetermined speed. A digital signal in which a b-bit parallel signal is inserted is input to each of the time slots of the second slot, and the same format conversion of the first interface means is performed on each of these b-bit parallel signals. An interface means and an output of the n first interface means or an output of the second interface means, Apparatus transmission system digital data, which comprises a format converting means to each of the al n-th time slot carries out a corresponding said b-bit parallel signals respectively insertion format inverse transform to.