JPS62145316A - Series transfer interface circuit - Google Patents

Abstract

PURPOSE:To simplify a transmission line by performing series transfer between devices in synchronism with a clock. CONSTITUTION:Parallel interface circuits 1 and 5 of two devices are connected to printed boards to output or input parallel data and operates with the clock CLKB. The parallel data is latched by a latch circuit 11 and converted into series data by a parallel/series converting circuit 12 with CLKA when transmitted. The series-converted data is passed through a connector 13 and a transmission line 14 and converted into parallel data by the other connector 15 and a series/parallel converting circuit 16; and the data is latched by a latch circuit 17 and supplied to the device through the parallel interface circuit 5. Consequently, the transmission line only needs to be consist of a single line 14 and two clock lines, i.e. three lines in total, so that constitution is simplified greatly, the crosstalk of the transmission line is small, and the influence of noises is eliminated.

Description

[Detailed Description of the Invention] [Summary] When transferring a plurality of parallel data between respective interfaces of two devices, the present invention transmits partial/serial data to both interfaces when transmitting, and transmits serial data to both interfaces when receiving. Means for serial/parallel conversion is provided, and serial data is transferred over the transmission line using a high-speed clock that is at least several times as high as the number of parallel data as the processing clock. This allows the transmission line to be significantly simplified without reducing the transmission speed.

[Industrial application field]

The present invention relates to a serial transfer interface circuit that simplifies transmission lines when transferring a plurality of parallel data between two device interfaces.

[Conventional technology]

In conventional electronic devices, control signals are set using multiple control printed boards, and when connecting to the control printed boards of other electronic devices, the number of connector pins is determined by the number of interface signals of both devices. are connected by flat cables or bundled cables.

FIG. 3 is an explanatory diagram of a conventional example. A multicore cable 6 is provided between parallel interface circuits 1 and 5 for inputting and outputting parallel data belonging to an electronic device (not shown) and connectors 2 and 4 of printed circuit boards connected thereto. By operating the parallel interface circuits 1 and 5 using the same processing timing clock, the parallel data can be received and transferred between both parallel interface circuits in two clocks.

[Problem that the invention seeks to solve]

The number of connector cores on the printed circuit boards mentioned above has increased rapidly due to the recent increase in the amount of information processed, and the amount of work and cost for mounting the cables inside the equipment has increased9, and the cables themselves are also susceptible to external noise. It is easily influenced by υ, which causes a decrease in the reliability of the device.

Therefore, the inventor of the present invention focused on using only the transmission line for serial transfer.

An object of the present invention is to provide a serial transfer interface circuit that simplifies the transmission line, does not reduce the transfer speed, and is not affected by external noise.

[Means for solving problems]

In order to achieve the above object, in the present invention, when a plurality of parallel data is transferred between the interfaces of two devices, means for performing parallel/serial conversion when transmitting and serial/parallel conversion when receiving is provided on both interfaces. The parallel data is transmitted serially on the transmission line using a high-speed clock that is at least the number of parallel data times as high as the processing clock.

0 action] By providing the interface with a means to perform serial/serial conversion of the transmission time difference and serial/parallel conversion of the reception time, only one transmission line is required, and the transmission speed is processed using a high-speed clock that is several times the number of parallel data. Therefore, the parallel-to-serial or series-to-parallel conversion and transfer ends at the same time as the data transfer time between conventional parallel interface circuits, and all parallel data transfer processing is completed.

〔Example〕

FIG. 1 is an explanatory diagram of the configuration of an embodiment of the present invention.

In the figure, parallel interface circuits 1 and 5 of two devices output or input a plurality of parallel data connected to a printed board, and operate with a processing clock of 0LKB. At the time of transmission, parallel data is latched in a latch circuit 11, and is serially converted in a parallel/serial conversion circuit 12 using, for example, a high speed clock (OLKA) that is twice as high as the number of parallel data.

The serially converted data is passed through one transmission line 14 via the connector 13 to the other connector 15 and converted to parallel data by the serial/parallel converter circuit 16, latched into the latch circuit 17, and sent to the device via the parallel interface circuit 5. supply parallel data.

In this case, the transmission line consists of a single single wire and a total of three timing lines 2' for the processing timing clock 0LKB and the high-speed parallel-to-serial conversion clock 0LKA, which is much simpler than the conventional method. This eliminates the influence of noise without reducing the signal speed and with less crosstalk in the transmission line.

FIG. 2 (α) is an explanatory diagram of the configuration of an application example of the present invention.
(&) in the same figure are operation waveform diagrams.

FIG. 1(α) shows the configuration of an applied example in which the embodiment of FIG. 1 is applied to transfer between the input/output device Cl10) 21 and another device 26. The l1021 includes a parallel interface circuit 1 and a latch circuit 11, and inputs the eight parallel data latched here in parallel to a shift register (SR) 22 corresponding to the parallel/serial conversion circuit 12, and shifts and serializes the data. As an output, the entire transmission M14 is passed through the connector 15, inputted to the connector 15 of another device 26, shifted by the serial input by the shift register (8R) 25 corresponding to the serial/parallel conversion circuit 16, and outputted in parallel to the latch circuit. and outputs Qo=Qy to other devices. On the other hand, a clock 0LKA is externally supplied to 5R22 and 5R25, and this shift clock 0LKA is supplied to the output 0LKB t-Ilo 21 and the latch circuit in the device 26 through the ⅛ frequency division counter 23. Therefore, the transmission line between the interfaces of both devices is a data serial transmission line 14.
It consists of six timing transmission lines for dormitory conspiracy B.

(b) ■ to ■ in the same figure are operation waveform diagrams of the main parts of the same figure (α).

(b) in the same figure is 0LKA (high speed clock for transfer), (b) in the same figure is 0LKB (conventionally used transfer lock), and CLKB is a 1/8 frequency divided clock of OLKA.

Of the two 0LKB clocks, the first clock converts parallel data into serial data, and the next clock converts the serial data into fully parallel data, and outputs lug data Qo = Q7. This relationship is the same as in the conventional example shown in FIG.

〔Effect of the invention〕

As explained above, according to the present invention, when a plurality of parallel data is transferred between the respective interfaces of two devices, parallel/serial conversion is performed when transmitting to both interfaces, and serial/parallel conversion is performed when receiving. Means is provided to serially transfer the data on the transmission line using a high-speed clock that is at least the number of parallel data times as high as the processing clock. This conversion circuit can be realized very easily and at low cost, and the transmission line is a single line for transmitting serial signals and a timing signal 2.
Since it consists of 9 parts, it is greatly simplified and can be freed from the influence of noise, and as shown in FIG.

Further, in order to increase the amount of parallel data, it is also possible to connect a plurality of the present invention in parallel.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of the configuration of an embodiment of the present invention, and FIG. 2 (α>*
(b) is a configuration diagram (α) and an operation explanatory diagram (b) of an application example of the present invention, FIG. 3 is an explanatory diagram of a conventional example, 1.5 is a parallel interface circuit, and 11.17 is a latch circuit. ,1
Reference numeral 2 indicates a parallel/serial conversion circuit, 13.15 a connector, 14 a transmission line, and 16 a serial/parallel conversion circuit.

Claims (1)

[Claims] In a system for transferring a plurality of parallel data from one to the other through a transmission line provided between respective interfaces of two devices in accordance with a predetermined processing clock, each A serial transfer interface circuit, characterized in that it is provided with means for serial conversion and serial/parallel conversion at the time of reception, and is configured to perform serial transfer on a transmission line at a high speed clock that is at least several times as high as the number of parallel data of the processing clock.