JPH0750877B2 - Channel access method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Overview] Regarding a channel access method for a PCM transmission device, a channel access method for reducing the size and cost of the device by reducing the number of signal lines between the multiplexing unit and the channel unit is proposed. For the purpose of providing, each n units are mounted on m units, each of which converts an analog input signal into digital data and outputs the data by the control signal from the multiplexing unit, and the output of the channel unit. In a data transmission device having a multiplexing unit for sequentially inputting and multiplexing signals, the unit designating signal sending unit outputting a signal for sequentially designating one unit out of m units to the multiplexing unit. Is provided, and a signal for sequentially designating one unit from the multiplexing unit is input to each of the m units, and in the designated unit, the n units mounted on the unit are input. The channel identification unit for outputting a signal for sequentially specifying the Yaneru unit provided, constituting the digital data from the specified channel unit by a signal for designating the output of the channel identification unit to output to the multiplexing unit.

[Industrial application field]

The present invention relates to an improvement of a channel access system of a CEPT primary group PCM transmission device.

At this time, there is a demand for a channel access method that can reduce the size and cost of the device by reducing the number of signal lines between the multiplexing unit (hereinafter referred to as MUX unit) and the channel unit (hereinafter referred to as CH unit). ing.

[Conventional technology]

FIG. 6 is a block diagram showing the configuration of an example PCM transmission device.

FIG. 7 is a diagram showing a conventional channel pulse transmission / reception system.

FIG. 6 shows, for example, the configuration of a CEPT primary group PCM transmission device. In FIG. 6, the analog signals input to each CH section 1-1 to 1-30 are digital in each CH section 1-1 to 1-30. Is converted to data. Then, a channel pulse for sequentially designating each CH section transmitted from the MUX section 2 to each CH section is supplied to each CH.
When the CH section receives and identifies that the CH section is designated in each CH section, the data for multiplexing from the designated CH section is sent to the MUX section 2. The MUX unit 2 sequentially receives the data from each CH unit and performs time division multiplexing at a frequency of 2 MHz, for example. Then, the multiplexed PCM data is sent to the transmission path.

Next, a method of transmitting / receiving the channel pulse transmitted from the above MUX2 to each CH unit will be described.

In FIG. 7, a logic circuit 4 made of LSI in the MUX unit 2
5 signal lines called A lines, 3 signal lines called B lines, and 2 signal lines called C lines are connected to the output of. Then, each of the signal lines of the A line, the B line, and the C line is configured such that at least one of the three signal lines is different between the CH units, and the logical product circuit (for each CH unit is provided. Hereinafter referred to as an AND circuit) 3-1 to 3-30. In the present case, the number of CH is 30, (A signal line) ×
(B line signal line) x (C line signal line) = 5 x 3 x 2 = 30
Therefore, each CH section can identify the designation signal from the MUX section 2 to its own CH section.

In this way, channel access is performed in the PCM transmission device.

[Problems to be Solved by the Invention]

However, in the above channel access method,
A total of 10 signal lines from the MUX section and 3 signal lines to each CH section are required, and the number doubles when considering bidirectionality.
There is a problem in that the number of signal lines between the parts is large, the unit is large and the cost is high.

Therefore, it is an object of the present invention to provide a channel access method that reduces the number of signal lines between the MUX section and the CH section to realize the downsizing and cost reduction of the device.

[Means for Solving the Problems]

The above problems are solved by the structure of the apparatus shown in FIG.

That is, in FIG. 1, m units 500-1 to 500-m
Channel units 100-1 to 100-n, which convert n analog input signals into digital data and output data according to a control signal from the multiplexing unit 200, and channel units 100-1 to 100. In a data transmission apparatus having a multiplexing unit 200 that sequentially receives the output of −n and performs multiplexing, 700 is provided in the multiplexing unit 200 and m units 500-1
It is a unit designation signal transmission unit that outputs a signal for sequentially designating one unit of the ~ 500-m.

600 is provided in each of the m units 500-1 to 500-m, and a signal for sequentially designating one unit is input from the multiplexing unit 200. In the designated unit, n units mounted in the unit are input. Is a channel identification unit that outputs signals that sequentially specify the channel units 100-1 to 100-n.

Then, the digital data is output from the channel section designated by the signal designated by the output of the channel identification section 600 to the multiplexing section 200.

[Work]

In FIG. 1, in the unit designation signal transmitting section 700 provided in the multiplexing section 200, m units 500-1 to 500-
A signal for sequentially designating one unit of m is output. Then, in the channel identification section 600 provided in each unit 500-1 to 500-m, a signal for sequentially designating one unit is input from the above-mentioned multiplexing section 200, and the designated unit is mounted on the unit. A signal for sequentially designating the n channel units 100-1 to 100-n is output.

Then, digital data is output from the channel section designated by the signal designated by the output of the channel identification section 600 to the multiplexing section 200.

As a result, between the unit designation signal transmission unit 700 provided in the multiplexing unit 200 and the m units 500-1 to 500-m,
It is sufficient to prepare only the signal lines for designating the unit, the number of signal lines can be reduced, and the size and cost of the device can be reduced.

〔Example〕

FIG. 2 is a block diagram showing the configuration of the apparatus of the embodiment of the present invention.

FIG. 3 is a block diagram showing the configuration of the channel pulse sending section of the embodiment.

FIG. 4 is a block diagram showing the configuration of the channel pulse identifying section of the embodiment.

FIG. 5 is a time chart explaining the operation of the embodiment.

The same reference numerals denote the same objects throughout the drawings.

In FIG. 2, a channel pulse sending unit 70 is provided in the MUX unit 20 to send a clock (CLK), serial data and a latch pulse to a unit having each CH unit. Each of the units 50-1 to 50-5 has, for example, six CH sections, and the channel pulse identifying section 60 uses the clock (C) from the MUX section 20.
LK), serial data and latch pulse. Then, the channel pulse identifying unit 60 identifies the channel pulse designating each CH.

The details will be described below.

Logic circuit provided in the channel pulse transmitter 70 shown in FIG.
At 72, parallel signal data consisting of, for example, 8 bits for sequentially designating each CH section is sent to a parallel / serial conversion section (hereinafter referred to as P / S) 71. The P / S71 synchronizes the input parallel signal data with the clock (CLK) input to the other terminals, and divides it into 8 bits indicating one CH part by the LOAD pulse to obtain serial data. Convert and output. As shown in FIG. 5, the LOAD pulse is also applied to the D of flip-flop circuit (hereinafter referred to as FF) 73.
It is also input to the terminal and held for the first time, and Q is generated by the clock pulse.
Output as a latch pulse from the pin.

The clock (CLK), the serial data and the latch pulse are received by the serial / parallel converter (hereinafter referred to as S / P) 61 in the channel pulse identification unit 60 shown in FIG. 4 and converted into parallel data. Then, for example, the lower 3 bits of data are output and applied to one of the input terminals of the exclusive OR circuits (hereinafter referred to as EX-OR circuits) 62-1 to 62-3.
For example, in the case of signal data designating the unit 50-1 to the other input terminal, as shown in FIG. 4, the EX-OR circuits 62-1 and 62-2 are connected to the ground potential (earth potential, "L"). + 5V (“H” level) is applied to the level) and 62-3 as shown in the figure. In other words, the combination of "00
Set to 1 "and EX-OR circuits 621 to 62-
When both match in 3, the EX-OR circuits 62-1 to 62-2
-3 outputs an "L" level ("0") signal.

These “L” level output signals are connected to a NOR circuit (hereinafter NO
R circuit) 63. The NOR circuit 63 outputs signal data of "H" level ("1") when all inputs are "L" level ("0"). This output is added to the counter 64. When this signal data (“1”) is input to the counter 64, the CH
A signal designating the section 10-1 is output to the CH section 10-1. CH section
In 10-1, the designation signal is received and the digital main signal data is output to the MUX unit 20.

Next, the counter 64 starts counting in synchronization with the input clock and when it reaches the 8th bit, the next CH section, that is, the CH section 10-
A signal designating 2 is output to the CH section 10-2. Then, the counter 64 continues counting and outputs a signal designating the next CH section to the corresponding CH section every 8th bit. 6th CH section 10-
When the output of the designated signal to 6 is completed, CH section 10-1 to 10-
Since the signal designating the unit 50-1 having 6 is not sent from the channel pulse sending unit 70 of the MUX unit 20, NOR
The output of the circuit 63 becomes "L" level ("0"), and the counter 64 is reset and initialized.

Next, a signal designating the unit 50-2 is sent from the channel pulse sending unit 70 of the MUX unit 20, and the unit 50-2 identifies that it is a signal to its own unit 50-2, and the NOR circuit 6
The "H" level ("1") is output from the counter 3 to the counter 64, and the same operation as described above is performed to identify the CH units 10-7 to 10-12. The other units 50-3 to 50-5 are also identified in the same manner as above.

In this way, the number of signal lines between the MUX section and the CH section can be reduced from, for example, 10 to 3, so that the device can be downsized and the number of connector pins can be reduced. Furthermore, simplification of the circuit configuration can be realized. As a result, it is possible to reduce the price and improve the reliability.

〔The invention's effect〕

As described above, according to the present invention, it is possible to reduce the number of signal lines between the MUX section and the CH section from, for example, 10 to 3, so that the device can be downsized and the number of connector pins can be reduced. Furthermore, simplification of the circuit configuration can be realized. As a result,
It is possible to realize low price and improved reliability.

[Brief description of drawings]

FIG. 1 is a principle diagram of the present invention, FIG. 2 is a block diagram showing a configuration of an apparatus of an embodiment of the present invention, FIG. 3 is a block diagram showing a configuration of a channel pulse sending unit of the embodiment, and FIG. FIG. 5 is a block diagram showing the configuration of the channel pulse identification unit of the embodiment, FIG. 5 is a time chart explaining the operation of the embodiment, FIG. 6 is a block diagram showing the configuration of an example PCM transmission device, and FIG. 7 is a conventional example. 3 is a diagram showing a channel pulse transmission / reception system of FIG. In the figure, 600 indicates a channel identification section, and 700 indicates a unit designation signal transmission section.

Claims (1)

[Claims] 1. m units (500-1 to 500-m), each of which is mounted n units, converts an analog input signal into digital data, and outputs the data by a control signal from a multiplexing unit (200). Channel section that outputs (100-1 to 100-n)
And a multiplexing unit (200) that sequentially inputs and multiplexes the outputs of the channel units (100-1 to 100-n), the multiplexing unit (200) including the m Units (500-1 to 50
0-m), a unit designation signal transmission section (700) for outputting a signal for sequentially designating one unit is provided, and each of the m units (500-1 to 500-m) is provided with
A signal for sequentially designating one unit is input from the multiplexing unit (200), and in the designated unit, n channel units (100-1 to 100-n) mounted on the unit are input.
Channel identification unit (600) that outputs signals that sequentially specify
And a digital signal is output from the channel section designated by the signal designated by the output of the channel identification section (600) to the multiplexing section (200).