JPS6119255A - Host computer accommodating system - Google Patents

Host computer accommodating system

Info

Publication number
JPS6119255A
JPS6119255A JP59139610A JP13961084A JPS6119255A JP S6119255 A JPS6119255 A JP S6119255A JP 59139610 A JP59139610 A JP 59139610A JP 13961084 A JP13961084 A JP 13961084A JP S6119255 A JPS6119255 A JP S6119255A
Authority
JP
Japan
Prior art keywords
exchange
host computer
interface
circuit
accommodated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59139610A
Other languages
Japanese (ja)
Inventor
Hiroo Iijima
飯島 裕雄
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59139610A priority Critical patent/JPS6119255A/en
Publication of JPS6119255A publication Critical patent/JPS6119255A/en
Pending legal-status Critical Current

Links

Landscapes

  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

PURPOSE:To simplify the accommodation of an exchange and a host computer and to eliminate the need for a special interface by accommodating plural line interfaces of a host computer to a multiplex interface used in general. CONSTITUTION:A data terminal equipment 3 is accommodated to an exchange 1 and an exchange circuit 4 is connected to the multiplex interface 40 of the exchange 1. The exchange circuit 4 is connected to line channels 20-2n of a host computer 2. Further, protocol converting circuits 50-5n are provided corresponding to the channels 20-2n to the converting circuit 4 and the converting circuits 50-5n convert a signal inputted/outputted to/from the computer 2 to a signal accommodated to the exchange 1. The converted signal is multiplexed by a multiplex circuit 42, the signal is converted by a circuit 41 connected to the interface 40 of the exchange 1 and accommodated in the exchange 1 so as to simplify the accommodation of the exchange 1 and the computer 2.

Description

【発明の詳細な説明】 (技術分野) 本発明はホストコンピュータ収容方式に関する。[Detailed description of the invention] (Technical field) The present invention relates to a host computer accommodation system.

(従来技術) 従来、この種のホストコンピュータ収容方式は第3図の
ように行なわれていた。第3図において、1i[換機、
2はホストコンピュータ、10〜1nは交換機1とホス
トコンピュータ2を接続する変換回路で、ホストコンピ
ュータ20回線チャンネル20〜2rl応に設けられて
いる。このホストコノピユータ2は例えばデータ端末3
からホストコンピュータ収容ポート30〜3nのうちの
どれか空のポート30を交換機1により選択されると、
変換回路10を介してホストコノピユータ2と接続され
、データ端末3がホストコンピュータ2と接続される。
(Prior Art) Conventionally, this type of host computer accommodation system has been implemented as shown in FIG. In FIG. 3, 1i [change machine,
2 is a host computer, and 10 to 1n are conversion circuits for connecting the exchange 1 and the host computer 2, which are provided corresponding to the host computer 20 line channels 20 to 2rl. This host computer computer 2 is, for example, a data terminal 3.
When the exchange 1 selects one of the empty ports 30 from among the host computer accommodation ports 30 to 3n,
It is connected to the host computer 2 via the conversion circuit 10, and the data terminal 3 is connected to the host computer 2.

しかし、一般にホストコンピュータ2の回線チャネルは
複数チャネルあり、各チャネル対応に変換回路を設ける
必要があるため、変換回路と交換機との接続が煩雑とな
り、変換回路の量も増加しイノタフエース回路の簡素化
が要求されている。
However, in general, the host computer 2 has multiple line channels, and it is necessary to provide a conversion circuit for each channel, which makes the connection between the conversion circuit and the exchange complicated, increases the number of conversion circuits, and simplifies the Innotaface circuit. is required.

(発明の目的) 本発明の目的は、従来のもののこのような欠点し を除去交換機とホストコンビュ、−夕の接続を簡単に行
なう変換回路を提供することにある。
(Object of the Invention) An object of the present invention is to provide a conversion circuit which eliminates the above-mentioned drawbacks of the conventional converter and which facilitates connection between an exchange and a host computer.

(発明の構成) 本発明によるとディジタル多重信号が収容可能i交換機
とホストコンピュータを接続する変換回路において、ホ
ストコ/ピータ側には回線チャネル対応に該ホストコノ
ピユータが処理するプロトコルに対応したインタフェー
スを、また、交換機側にはディジタル多重信号が接続可
能なインタフェースを備え、ホストコンピュータから入
出力する複数の回線チャネルの信号を多重化して交換機
に収容することを特徴とするホストコノビーータ収容方
式が得られる。
(Structure of the Invention) According to the present invention, in a conversion circuit that connects an i-exchange capable of accommodating digital multiplexed signals and a host computer, the host copier side has an interface corresponding to the protocol processed by the host copier in correspondence with the line channel. and a host conobeater accommodation system characterized in that the exchange side is equipped with an interface to which digital multiplex signals can be connected, and the signals of multiple line channels input and output from the host computer are multiplexed and accommodated in the exchange. is obtained.

(実施例) 次に本発明の一実施例を図面を参考にして説明する。(Example) Next, one embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例のブロック図を示し、第1図
において1は交換機、2はホストコンビ、−一夕、3は
データ端末で、交換機1に収容されている。4は本発明
の変換回路である。また40は交換機lに設けられてい
る多重化インタフニー2で、この例でIt’x64 K
bps a 1チヤノネルとして24チヤンネルと多重
化したいわゆるT1インタフェースなど標準のインタフ
ェースである。変換回路4はホストコンピュータ2から
の信号を多重化して、交換機1の多重化インタフェース
(例えばT1イ/タフース)へ接続している。
FIG. 1 shows a block diagram of an embodiment of the present invention. In FIG. 1, 1 is an exchange, 2 is a host combination, 3 is a data terminal, and these are housed in the exchange 1. 4 is a conversion circuit of the present invention. Further, 40 is a multiplex interface 2 provided in the exchange 1, and in this example, it'x64K
This is a standard interface such as the so-called T1 interface in which a single bps a channel is multiplexed with 24 channels. The conversion circuit 4 multiplexes the signals from the host computer 2 and connects the signal to a multiplexing interface (for example, T1/TAFUS) of the exchange 1.

第2図は第1図における変換回路4の一実施例のブロッ
ク図で、50〜5nはホストコ/ピユータ2の回線チャ
ネル20〜2n対応に接続されたプロトコル変換回路で
、ホストコ/ピユータ2から入出力される信号を交換機
lに収容できる信号に変換する機能を有する。50〜5
nで変換された信号は多重化回路42で多重化され、交
換機1の多重化インタフェース(例えばT1インタフェ
ース)40に接続できるように回路41で信号変換全行
ない交換機に収容される。
FIG. 2 is a block diagram of an embodiment of the conversion circuit 4 in FIG. It has a function of converting the output signal into a signal that can be accommodated in the exchange l. 50-5
The signals converted by n are multiplexed by a multiplexing circuit 42, and all signal conversion is performed by a circuit 41 so that the signals can be connected to a multiplexing interface (for example, T1 interface) 40 of the exchange 1, and the signals are accommodated in the exchange.

(発明の効果) 本発明によりホストコ7ピーータの複数の回線インタフ
ェースを一般に利用きれている多重化インタフェースに
収容できるので、交、lA機とホストコンピュータの収
容が簡素化され、交換機側インタフェースとしても特殊
なインタフェースを用意する必要もない。
(Effects of the Invention) According to the present invention, multiple line interfaces of a host copier can be accommodated in a commonly used multiplexed interface, which simplifies the accommodation of AC/LA machines and host computers. There is no need to prepare a separate interface.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のブロック図、第2図はその
変換回路部分の一実施例のブロック図、第3図は従来の
もののブロック図である。 1・・・・・・交換L 2・・・・・・ホストコンピュ
ータ、3・・・・・・データ端末、4・・・・・・変換
回路、lO〜1n・・・・・・従来の変換回路、40・
・・・・・多重化インタフェース。 代理人 弁理士  内 原   音 生1拐 「 芽ZV
FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a block diagram of an embodiment of the conversion circuit portion thereof, and FIG. 3 is a block diagram of a conventional one. 1... Exchange L 2... Host computer, 3... Data terminal, 4... Conversion circuit, lO~1n... Conventional Conversion circuit, 40・
...Multiplexing interface. Agent Patent Attorney Uchihara Otoki ``Me ZV''

Claims (1)

【特許請求の範囲】[Claims] ディジタル多重信号が収容可能な交換機とホストコンピ
ュータを接続する変換回路において、ホストコンピュー
タ側には回線チャネル対応に該ホストコンピュータが処
理するプロトコルに対応したインタフェースを、また、
交換機側にはディジタル多重信号が接続可能なインタフ
ェースを備え、ホストコンピュータから入出力する複数
の回線チャネルの信号を多重化して交換機に収容するこ
とを特徴とするホストコンピュータ収容方式。
In a conversion circuit that connects an exchange capable of accommodating digital multiplexed signals and a host computer, the host computer side is provided with an interface compatible with the protocol processed by the host computer in correspondence with the line channel, and
A host computer accommodation method characterized in that the exchange side is equipped with an interface to which digital multiplex signals can be connected, and signals of a plurality of line channels input and output from the host computer are multiplexed and accommodated in the exchange.
JP59139610A 1984-07-05 1984-07-05 Host computer accommodating system Pending JPS6119255A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59139610A JPS6119255A (en) 1984-07-05 1984-07-05 Host computer accommodating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59139610A JPS6119255A (en) 1984-07-05 1984-07-05 Host computer accommodating system

Publications (1)

Publication Number Publication Date
JPS6119255A true JPS6119255A (en) 1986-01-28

Family

ID=15249293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59139610A Pending JPS6119255A (en) 1984-07-05 1984-07-05 Host computer accommodating system

Country Status (1)

Country Link
JP (1) JPS6119255A (en)

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