JPH08307378A - Multiplexing device - Google Patents

Abstract

PURPOSE: To sharply increase the number of digital lines to be stored, to improve packaging efficiency and the time slot application efficiency of a transmission line and to reduce cost per line by using a signaling signal line used when an analog line is connected as a signal line for a main signal at the time of connecting a digital line. CONSTITUTION: Each line terminating units for terminating a digital line or an analog line is connected to a common processing unit 5 capable of connecting plural line terminating units through a signal line for a main signal and a signal line for a signaling signal. Signals from plural lines are multiplexed and sent to a transmission line and signals from the transmission line are separated and sent to respective lines. In the case of connecting a digital line terminating unit 1 for terminating a digital line to the unit 5, a main signal is transmitted/ received through the signal line for a signaling signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer for multiplexing connected analog lines or digital lines.

[0002]

2. Description of the Related Art Conventionally, analog lines (0.3 to 3.4 kH)
z) is composed of an analog line terminating unit that digitally multiplexes up to 96 lines, and a common processing unit that can connect up to 4 analog line terminating units and can mount up to 4 circuits of a transmission line interface unit. There is a known oxidizer. In such a multiplexer, when a digital line terminating unit that terminates a high-speed digital line (communication speed 64 k to 1536 kHz) is connected instead of the analog line terminating unit, the number of lines accommodated by one digital line terminating unit is the unit. Maximum of 4 due to the relationship with the interface (6.312 MHz)
The maximum number of lines that can be accommodated per device is 16 lines.

A detailed description will be given below. FIG. 3 is a block diagram of a multiplexing device configured by connecting four analog line termination units to a common processing unit. In the figure,
The analog line terminating unit 7 includes a maximum of 96 analog channel units (ACH) and a demultiplexing unit (MUX).
A) and contain. The analog channel unit (ACH) converts the analog signal 4WS input from the analog line into the digital signal 2MSD and the signaling signal SS into the digital signal 2MSSD, while the digital signal 2MRD input from the demultiplexing unit into the analog signal 4WR, The demultiplexing unit (MUXA) that converts the digital signal 2MSRD into the signaling signal SR outputs the signals SDI and SSDI obtained by multiplexing 96 channels of the digital signals 2MSD and 2MSSD from the analog channel unit to the common processing unit 5. , A digital signal 2MR obtained by separating the signals RDO and SRDO from the common processing unit 5
D, 2MSRD is output to the analog channel section. Further, the common processing unit 5 connected to the analog line terminating unit via the connection cable 3 accommodates a time slot setting unit (TSW) and a transmission line interface unit (IF). The time slot setting unit (TSW) includes four analog line termination units 7-a to 7-d and four units described later.
64 between two transmission line interface units -a to -d
Time slots are set in units of k. The transmission line interface unit (IF) converts the signals SDO and SSDO from the time slot setting unit into a transmission line side format and outputs signals RDI and SRDI obtained by converting the signal from the transmission line into a line side format to the time slot setting unit. To do.

FIG. 2 shows a line setting example of the time slot setting section.
Will be described with reference to. Upstream time slot setting unit U
Sends the signals TS1-96 of the signals SDI-a-d from the analog line termination units 7-a-d to SDO-a-d.
Each TS1 to 96 of each, and each TS of SSDI-a to -d
Lines 1 to 96 are set for each TS 1 to 96 of SSDO-a to -d and output to the transmission line interface unit. At this time, SDI-n and SSDI-n are set as a pair. The downlink side time slot setting unit D is for each TS1 of the signals RDI-a to -d from the transmission line interface units -a to -d.
-96 to RDO-a to -d, and RDI-a to -d TS1 to 96 for SRDO-a to -d TS1 to 96, respectively.
The line is set to and output to the analog line terminating unit 7. At this time, RDI-n and SRDI-n are set as a pair.

As described above, the analog line termination unit 7
The conventional multiplexer / demultiplexer to which the digital line terminal unit is connected has a structure as shown in FIG. In the figure, the digital line termination unit accommodates a maximum of four high-speed digital channel units 11 (DCH) and a demultiplexing unit.

The high-speed digital channel unit 11 (DCH) converts the high-speed digital signal SDATA from the digital line into a digital signal 1.5MSD and converts the digital signal 1.5MRD from the demultiplexing unit into the high-speed digital signal RDAT.
Convert to A. The demultiplexing unit (MUXB) outputs the digital signal 1.5MSD from the high speed digital channel unit 11 to 4
The common processing unit 5 receives the signal SDI obtained by channel multiplexing.
Signal RD from the common processing unit 5 while being output to
A signal 1.5MRD obtained by separating O is output to the high-speed digital channel unit 11.

Since the high-speed digital line does not require the signaling signals SS and SR as in the analog line, the signaling signal signal lines SSDI and SRDO are not used. An example of the line setting unit of the time slot setting unit at this time will be described with reference to FIG. The upstream time slot setting unit U sets the respective TS1 to 96 of the signals SDI-a to -d from the digital line termination units -a to -d to SDO-a to -d.
A line is set for each TS1 to 96 of the above. At this time SSDI-
a-d and SSDO-a-d are unused. Further, the downlink side time slot setting unit D sets the lines of the TS1 to 96 of the signals RDI-a to -d from the transmission line interface units -a to -d to the TS1 to 96 of the RDO-a to -d. At this time, SRDI-a to -d and SRDO-
a to -d are unused.

However, the conventional multiplexer as described above has the following problems. The SDATA of the high-speed digital line is composed of 24 time slots, but the effective time slot varies from 1 to 24 and depends on the usage of the line. At present, there are many usage methods in which three time slots are valid. If all high-speed digital lines that enable these 3 time slots are mounted on one rack, 3 (time slots / lines) x 16 (lines) = 48
(Time slot), and only half of the time slots are used in the transmission path capable of transmitting up to 96 time slots per line. That is, there is a problem in that the mounting efficiency of the multiplexer and the use efficiency of the time slot of the transmission line are deteriorated, and the cost per high-speed digital line is increased.

[0009]

SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional multiplexer as described above, and it is possible to remarkably increase the number of lines accommodated when digital lines are connected. It is an object of the present invention to provide a multiplexing device capable of improving the mounting efficiency and the time slot use efficiency of a transmission path and reducing the cost per line.

[0010]

SUMMARY OF THE INVENTION In order to achieve the above object, a multiplexer of the present invention comprises a line terminating unit for terminating a digital line or an analog line and a common processing unit capable of connecting a plurality of the line terminating units as main signals. It is a multiplexer that is connected via a signal line for signaling and a signal line for signaling signal, multiplexes signals from a plurality of lines and sends them to a transmission line, and separates signals from the transmission line and sends them to the line. When the digital line terminating unit for terminating the digital line is connected to the common processing unit, the main signal is transmitted and received via the signal line for signaling signal.

A line terminating unit for terminating a digital line or an analog line and a common processing unit capable of connecting a plurality of line terminating units are connected via a main signal signal line and a signaling signal signal line, A multiplexer for multiplexing signals from a plurality of lines and transmitting the multiplexed signals to a transmission line and separating the signals from the transmission line to the line, wherein a digital line termination unit for terminating a digital line is And a high-speed digital channel unit for converting the signal of the above into a predetermined digital signal and outputting the signal from the high-speed digital channel unit to the main signal signal line and the signaling signal signal line, and the main signal signal line and And a demultiplexing unit that separates a signal from a signaling signal signal line and outputs the signal to the digital channel unit,
The common processing unit converts a signal from the line terminating unit side to a transmission line side format and a signal from the transmission line to a line side format, a transmission line interface unit, and the demultiplexing unit. When the digital line termination unit is connected to the common processing unit, the demultiplexing unit and the time slot setting unit are connected to the main signal signal. Line and a signaling signal signal line, and transmits and receives a main signal through the main signal signal line and the signaling signal signal line, and the time slot setting unit is for the signaling signal on the digital line termination unit side. Connect the signal line and the main signal signal line on the side of the transmission path interface to connect the time line. And performing a set of Tsu door.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail based on the embodiments shown in the drawings. FIG. 1 is a block diagram showing an embodiment of a multiplexing device according to the present invention. First, referring to FIG. 1, four digital line termination units 1-a to-
The configuration of the multiplexing device of the present embodiment will be described by taking the case where d is connected to the common processing unit 5 via the connection cable 3 as an example. Incidentally, each of the digital line termination units 1- to -d
Since they have the same configuration, the first digital line terminating unit 1-a will be described as an example, and the others will be omitted. The digital line terminating unit 1-a accommodates a maximum of eight high-speed digital channel units 11 (DCH) and a demultiplexing unit (MUX).

The high-speed digital channel unit 11 (DCH) converts the high-speed digital signal SDATA from the digital line into a digital signal 1.5MSD, and converts the digital signal 1.5MRD from the demultiplexer into a high-speed digital signal RDA.
Convert to TA. The demultiplexing unit (MUX) is a digital signal 1.5 from the high-speed digital channel units 11 (1) to (4).
The MSDs are multiplexed on four channels and output to the common processing unit 5 as a signal SDI, while the signal RDO from the common processing unit 5 is separated and output as a signal 1.5MRD to the high-speed digital channel units 11 (1) to (4). Output circuit part,
The digital signal 1.5MSD from the high-speed digital channel units 11 (5) to (8) is multiplexed on four channels and output to the common processing unit 5 as a signal SSDI, while the signal SRDO from the common processing unit 5 is separated. Signal 1.5 MR
It is composed of a circuit section for outputting D to the high-speed digital channel section 11 (5) to (8).

Further, the common processing unit 5 includes a time slot setting section (TSW) and a transmission line interface section (I
F) and. The time slot setting unit (TSW) sets time slots in units of 64k between the four analog line terminating units 7-a to -d and four transmission line interface units -a to -d described later. . The transmission line interface unit (IF) converts the signals SDO and SSDO from the time slot setting unit into a transmission line side format and converts the signals from the transmission line into a line side format signals RDI and SRDI into a time slot setting unit. Output to.

An example of the line setting section of the time slot setting section at this time will be described with reference to FIG. As in the conventional case, in the upstream time slot setting unit U, the signals SDI-a to -d from the digital line terminating units 1-a to -d are input.
TS1-96 of SDO-a-d of TS1-96 of
In the downlink time slot setting section D, the signal R from the transmission path interface sections -a to -d is set.
The lines of each TS1 to 96 of DI-a to -d are set to each of TS1 to 96 of RDO-a to -d.

Further, in this embodiment, in the time slot setting unit U on the upstream side, the digital line termination unit 1
Each TS1 of the signals SSDI-a to -d from -a to -d
96 are high-speed digital channel units 11 (5)-
The main signal 1.5MSD of (8) is multiplexed, and the time slots are set in units of one time slot for each TS1 to 96 of the signals SDO-a to -d. Further, in the time slot setting section D on the downlink side, the signals RDI-a from the transmission line interface sections -a to -d are transmitted.
Of the TS1 to 96 of -d, the required time slots are set in the TS1 to 96 of the signals SRDO-a to -d to the required time slot in units of one time slot. With the above configuration, it is possible to mount up to 8 high-speed digital channel units in one unit of the digital line terminating unit, so that a maximum of 32 channels can be mounted per rack.

Comparing this with the case of the conventional multiplexer, when all the high-speed digital lines for which 3 time slots are effective are mounted on one rack, 32 lines × 3 time slots / line = 96 time slots, and transmission is performed. Since all 96 time slots of one line are used, the time slot use efficiency of the transmission line is improved. The maximum accommodating time slot per rack is 4 because the transmission path is 4HW.
HW × 96TS / HW = 384TS. Therefore,
In the case of an analog line, a maximum of 96 channels can be accommodated, and 4 units can be mounted per rack, so a maximum of 4 × 96 channels = 384 channels, which enables transmission on all channels.

In the case of a high-speed digital line, a maximum of 4 × 8 channels = 32 channels can be mounted because one unit accommodates 8 channels and 4 units can be mounted per rack. Since the time slots that can be transmitted are 384 TS, the average effective time slot per channel of the high-speed digital line is limited to 12 time slots. There is no limitation in using analog line terminating units and digital line terminating units in a single unit and setting the lines on the same transmission line.

As described above, when the signaling signal line of the inter-unit cable is connected to the high-speed digital line as in the present embodiment, it is used as the main signal signal line, so that the high-speed digital line termination unit 1 The maximum number of high-speed digital channel units that can be accommodated per unit is 8 lines, and the maximum number of units that can be accommodated per unit is 8 x 4 = 32 (lines), which is double the conventional number. Since the space per rack and the common part remain the same as before, the cost per line is 1 /
It becomes 2.

[0020]

As described above, according to the present invention, the signal line for signaling when the analog line is connected is used as the signal line for the main signal when the digital line is connected. By significantly increasing the number of devices accommodated, the mounting efficiency and the time slot use efficiency of the transmission line are improved, and the cost per line is significantly reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of a multiplexing device of the present invention.

FIG. 2 is a diagram showing an example of line setting in a time slot setting section shown in FIG.

FIG. 3 is a block diagram showing a system configuration when four analog line terminating units are connected.

FIG. 4 is a block diagram showing a system configuration when four high-speed digital line terminal units are connected.

[Explanation of symbols]

 1 Digital Line Termination Unit 3 Connection Cable between Units 5 Common Processing Unit 7 Analog Line Termination Unit 11 High Speed Digital Channel Unit (DCH) 13 Demultiplexing Unit (MUX) 51 Time Slot Setting Unit (TSW) 53 Interface (IF) 71 Analog Channel Division (ACH) 73 Demultiplexing Division (MUXA)

Claims (2)

[Claims] 1. A line terminating unit for terminating a digital line or an analog line and a common processing unit capable of connecting a plurality of line terminating units are connected via a main signal signal line and a signaling signal signal line, A common processing unit, which is a multiplexing device that multiplexes signals from a plurality of lines and sends them to a transmission line, separates signals from the transmission line, and sends them to the line. A multiplexer that transmits and receives a main signal via a signal line for signaling signal when connected to. 2. A line terminating unit for terminating a digital line or an analog line and a common processing unit capable of connecting a plurality of the line terminating units are connected via a main signal signal line and a signaling signal signal line, A multiplexing device that multiplexes signals from a plurality of lines and sends them to a transmission line, separates signals from the transmission line and sends them to the line, and a digital line termination unit that terminates a digital line,
A high-speed digital channel unit for converting a signal from a line into a predetermined digital signal, and a signal from the high-speed digital channel unit is multiplexed and output to a main signal signal line and a signaling signal signal line, and the main signal signal And a demultiplexing unit that separates signals from the line and the signal line for signaling signal and outputs the signals to the digital channel unit, wherein the common processing unit converts the signal from the line termination unit side into a transmission line side format. A transmission line interface unit for converting a signal from a transmission line into a line side format; and a time slot setting unit for interposing between the transmission line interface unit and the demultiplexing unit for setting a time slot, When connecting the digital line termination unit to the common processing unit, the demultiplexer and time slot are used. The setting unit is connected via the main signal signal line and the signaling signal signal line, and the main signal is transmitted and received via the main signal signal line and the signaling signal signal line, and the time slot setting unit is the digital signal. A multiplexing device for connecting a signaling signal signal line on the line terminating unit side and a main signal signal line on the transmission line interface section side to set a time slot.