JP2750203B2 - Line setting circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a line setting circuit provided in a digital transmission apparatus for setting a route of a transmission signal.

2. Description of the Related Art In a line setting circuit in many digital transmission apparatuses (for example, a multiplexing apparatus), a unit of a minimum processing (serial / parallel conversion, multiplexing processing, etc.) of a transmission signal to be provided for setting a path is a byte. FIG. 2 shows a conventional line setting circuit for handling such a signal processed in byte units (hereinafter referred to as a byte synchronization signal).

In FIG. 2, for example, each byte synchronization signal from eight highways is provided to the bit rate conversion unit 1. The bit rate conversion unit 1 adjusts the bit rate of each byte synchronization signal to the highest bit rate and provides the same to the signaling separation unit 2. For example, CCITT (International Telegraph and Telephone Consultative Committee) recommends line setting circuits for multiplexing equipment.
There is a possibility that a byte synchronization signal having a bit rate of 1.5 Mb / s, 2 Mb / s, 6.3 Mb / s, or 8 Mb / s is provided. In this case, the bit rate conversion unit 1 The bit rate of the byte synchronization signal is 8 Mb / s.

The signaling separation unit 2 separates each byte synchronization signal into a main signal component (transmission data main body as an information signal) INF and a signaling signal (management signal) component SIG, and multiplexes the main signal component into a multiplex / serial / parallel conversion unit 3. And a signaling signal component to the multiplexing unit 4.

FIG. 3 shows this separation processing. As shown in FIG. 3 (A), the byte synchronization signal includes a main signal (for example, consisting of CH1 to CH6) representing information to be transmitted and a signaling signal as management information of a handling group (highway). 3B), but excluding the signaling signal therefrom to form the main signal component INF shown in FIG. 3 (B).
The signaling signal is arranged at a time position synchronized with the main signal position in the main signal component to form a signaling signal component SIG shown in FIG. 3 (C).

The multiplexing / serial / parallel conversion unit 3 performs a multiplexing process and a serial / parallel conversion process on the main signal component on each highway, converts one serial byte into one parallel byte, and multiplexes each highway. The 8-bit data sequence is provided to a time slot conversion unit (time switch unit) 5. The multiplexing unit 4 multiplexes the signaling signal components for each highway and supplies the multiplexed signaling signal component to the time slot conversion unit 5.

The time slot conversion unit 5 sets a total of 9 bits that arrive at the same time as a time slot, and converts the position of the time slot according to the required line setting content. Although illustration is omitted, the time slot conversion is performed by making the order of writing and reading the time slot to and from the data memory different.

The processing after the time slot conversion is performed is the reverse of the above-described processing.

That is, the main signal component after the time slot conversion is subjected to parallel / serial conversion and demultiplexing processing by the parallel / serial conversion / separation unit 6, returned to a signal corresponding to each output highway, and provided to the signaling multiplexing unit 7. The signaling signal component after the time slot conversion is demultiplexed by the demultiplexing unit 8, returned to a signal corresponding to each output highway, and provided to the signaling multiplexing unit 7. The signaling multiplexing unit 7 multiplexes the signaling signal component on the main signal component, returns to a plurality of byte synchronization signals having a predetermined bit rate, and supplies the byte synchronization signal to the bit rate inverse conversion unit 9. The bit rate of the input byte synchronization signal is converted into a bit rate corresponding to the highway, and the converted bit rate is output to each output highway.

 In this way, a predetermined line setting is made.

[Problems to be Solved by the Invention] By the way, recently, an international standard network interface (NN
I) has been recommended, and the need to convert existing interface signals to NNI signals has arisen.

As a method of converting the NNI signal, there are two methods of byte synchronization in which the information is divided and multiplexed in channel units, and bit synchronization in which all information is transmitted and received in a highway unit without division in channel units.

In this case, it is conceivable to separately configure the line setting circuit according to each method, but in view of the miniaturization and versatility of the circuit, a circuit that can handle both methods in the same manner is desired.

The conventional line setting circuit shown in FIG. 2 is intended for a byte synchronization signal that requires a main signal component and a signaling signal component to be separated and processed on a channel basis.
It cannot be used as a circuit that handles bit synchronization signals (signals to be processed in bit units instead of byte units).

Therefore, conventionally, the bit synchronization signal is not input to the line setting circuit for the byte synchronization signal, and the configuration of the device is large and complicated.

In addition, in practice, there is a byte synchronization signal having a bit rate of 1.5 Mb / s, 2 Mb / s, 6.3 Mb / s, and 8 Mb / s,
There are bit synchronization signals having bit rates of 1.5 Mb / s and 6.3 Mb / s.

The present invention has been made in view of the above points,
An object of the present invention is to provide a line setting circuit capable of handling both a byte synchronization signal and a bit synchronization signal.

[Means for Solving the Problems] In order to solve the problems, the present invention is configured to include the following units, so that line setting for both the byte synchronization signal and the bit synchronization signal can be performed. The circuit was realized.

That is, a channel signal including an information signal and a management signal for managing a transmission state of the information signal is time-division multiplexed on a highway, and the channel signal input through a plurality of the highways connected in parallel. Everything,
A time slot is formed for each channel signal, and all information signals of the channel signal are multiplexed in an information multiplexed signal in a line setting circuit for interconnecting to a predetermined interconnection destination according to the time order of the time slot. A multiplexing circuit for converting, a format conversion circuit for multiplexing all management signals of the channel signal, and format-converting this into a management multiplexed signal having the same time sequence as the information multiplexed signal; Time slot conversion in which a time slot is formed by pairing the information signal and the management information in the same time sequence of the multiplexed signal and corresponding to the predetermined interconnection destination to be output, and the time order is changed. Circuit and the information signal and the management signal converted by the time slot conversion circuit. Conversion, performing a reverse conversion of the format conversion, comprising a separation circuit and a format reverse conversion circuit for converting to an output digital signal, when performing the interconnection of the channel signal unit, the time slot conversion in the time slot conversion circuit When the execution is performed in units of channel signals and the interconnection is performed in units of highways, an input signal input via the highway is virtually separated into a pair of an information signal and a management signal similarly to the channel signals. A time slot, and the time slot conversion circuit rearranges the time order of the time slot in accordance with the predetermined interconnection destination to be output.

[Operation] The present invention virtually introduces a byte concept to the bit synchronization signal so that the bit synchronization signal can be processed by the same components as the byte synchronization signal.

In the present invention, before inputting a signal to the time slot conversion circuit, the multiplexing circuit multiplexes the information signals of all the channels of the input digital signal and converts them into an information multiplexed signal,
A format conversion circuit multiplexes the management signals of all the channels of the input digital signal, and converts this into a management multiplex signal having the same time arrangement as the information multiplex signal.

Then, the time slot conversion circuit switches the time order of the information multiplexed signal and the management multiplexed signal as a pair.

After that, the separation circuit and the format reverse conversion circuit
The information multiplexed signal and the management multiplexed signal converted by the time slot conversion circuit are converted into output digital signals by performing multiplex conversion and inverse conversion of format conversion, respectively.

At the time of such line setting, when interconnection is performed on a channel basis, the conversion in the time slot conversion circuit is performed on a channel basis. When interconnection is performed on a highway basis, a highway signal is virtually transmitted to a plurality of channels. The information signal and the management signal are separately allocated and time-slot conversion is performed in units of channels over a plurality of virtual channels.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the drawings.

Here, FIG. 1 is a block diagram showing the configuration of this embodiment, FIG. 4 is an explanatory diagram showing a signal structure after bit rate conversion of the embodiment, and FIG. 5 is a diagram after multiplexing / serial / parallel conversion of the embodiment. FIG. 6 is an explanatory diagram showing a signal structure, and FIG. 6 is an explanatory diagram showing a signal structure after format conversion.

A byte synchronization signal or a bit synchronization signal (hereinafter, the byte synchronization signal and the bit synchronization signal are collectively referred to as a synchronization signal) are provided to the line setting circuit 10 of this embodiment in a mixed manner from the 24 highways. The line setting circuit 10 receives each synchronization signal at the bit rate conversion unit 11.

The bit rate conversion unit 11 converts the bit rate of each synchronization signal to a predetermined bit rate, and provides the multiplexed / serial / parallel conversion unit 12.

In this embodiment, as shown in FIG. 4, the bit rate is adjusted to 8.64 Mb / s. That is, the data is aligned so that 135 bytes constitute one frame. In the case of the byte synchronization signal, as shown in FIG. 4A, 15 bytes are an area relating to management information, and the remaining 120 bytes are an area relating to a main signal (transmission data main body). This 135 bytes is 5
FIG. 4B shows the byte handling groups separately. The first 5 bytes are, for example, NN
If the signal is an I signal, the pointer value is an area (not inserted at this time) V1. If the NNI signal is used, the next 5 bytes are an area (not inserted at this time) V5 where an overhead is inserted. The next 5 bytes are an area ST in which a signaling signal and other management information are stored. In the case of the bit synchronization signal, since there is no concept of management information and processing is not performed in byte units, the expression as shown in FIG. 4 is not appropriate, but the byte shown in FIG. The concept is virtually introduced (but the bytes have no meaning).

The 24 synchronization signals whose bit rates have been converted as shown in FIG. 4 are supplied to the multiplexing / serial / parallel conversion unit 12. Multiple
The serial-to-parallel converter 12 multiplexes the 24 synchronization signals and performs serial-to-parallel conversion of each synchronization signal in byte units. Accordingly, an 8-bit data string shown in FIG. 5 is output and supplied to the format conversion unit 13.

In FIG. 5, 8 bits in the depth direction are 1-byte data of each synchronization signal converted in the space direction by serial-parallel conversion. The horizontal and vertical directions in FIG. 5 both indicate the passage of time, and this point is the same as in FIG. 4 (B). In FIG. 5, the data of the first, second, third,..., Twenty-fourth synchronization signals appear sequentially and repeatedly.

The format converter 13 has a built-in memory. When 8-bit data of management information in a byte synchronization signal is input, the 8-bit data is temporarily stored in the memory, and the 8-bit data other than the management information is stored in the 8-bit data. Are added to form 6-bit data to form 14-bit data, which is provided to the time slot conversion unit 14. This is pre-processing for time slot conversion without wasting any data in the areas V1, V5, and ST in which management information is stored in the byte synchronization signal. In the case of the byte synchronization signal, management information other than the signaling signal may be lost. However, even if the byte concept is introduced, any bit data should not be lost in the bit synchronization signal. Processing is provided.

FIG. 6 shows a specific example of such conversion. V1 management information (FIG. 6 (A1)), V5 management information (FIG. 6 (A2)) and ST management information (FIG. 6 (A
3)) is temporarily stored as described above when input. In this state, when 8-bit data (FIG. 6 (A4)) other than the management information area is input, it is converted into 14-bit data as shown in FIG. 6 (B). If the input 8-bit data is the data of the first handling group HG1 of the first channel CH1, the V1 management information (FIG. 6 (A
1)), bit data V1 at a predetermined position in V5 management information (FIG. 6 (A2)) and ST management information (FIG. 6 (A3)).
a, V1b, V5a, V5b, STa, STb
14-bit data is formed by adding to the input data as shown in FIG. Although the concept of the management information does not adapt to the bit synchronization signal, it is converted as shown in FIG. 6 similarly to the byte synchronization signal.

Note that, as shown in FIG. 6, the positions of the extracted two bits are not determined in a simple order because the ease of conversion processing and the correspondence between the main signal components and the signaling signal components are considered. For example, according to the recommendation for the NNI signal, at present, data is inserted only in the middle 4-bit position of the ST management information, and other management information is empty, but the bit data of the existing management information is prioritized. FIG. 6 shows the conversion method.

The input 8-bit data is the second to second channels of the first channel.
Similarly, in the case of the data of the fourth handling group HG2 to HG4, the bit data at the predetermined position of the V1 management information, V5 management information and ST management information belonging to the column of FIG. And take out two pieces at a time.
2) to 14-bit data are formed by adding to the input data as shown in FIG. 6 (B4).

The time slot conversion unit 14 converts the position of the time slot consisting of 14-bit data according to the line setting content by making the order of writing and reading the time slot to and from the memory different from the conventional one.

Subsequent configurations are configured to execute reverse processing of the processing described so far.

That is, the 14-bit data after the time slot conversion is converted into 8-bit data by the inverse conversion performed by the format conversion unit 13 by the format inverse conversion unit 15 (from FIG. 6 to FIG. 5). Are multiplexed and demultiplexed into 24 synchronization signals by the parallel / serial conversion / separation unit 16, and are converted in the spatial direction and the time axis direction (from FIG. 5 to FIG. 4). The signal is returned to the original bit rate signal for each synchronization signal by the unit 17 and output to the corresponding output highway.

The features of the line setting circuit 10 of the above embodiment will be summarized and described.

First, between the multiplexing / serial / parallel conversion unit 12 and the parallel / serial conversion / separation unit 16, the bit synchronization signal is processed in units of bytes. Here, the byte has no meaning as information, and this byte is a processing unit for conversion and the like. In this way, the processing system is shared with the byte synchronization signal.

Secondly, even if the meaning of the byte is different between the processing for the bit synchronization signal to which the byte concept is introduced and the processing for the byte synchronization signal, the difference is eliminated.
In this way, the processing systems are completely shared.

Third, with respect to the byte synchronization signal, management information other than the signaling signal is output as a time slot conversion object without wasting. Looking at only the byte synchronization signal, there is management information data that does not cause a problem even if it is lost through this line setting circuit 10.However, with the bit synchronization signal, each bit data cannot be wasted. Must be transmitted without loss, and this principle is applied to the byte synchronization signal flowing on the same path.

FIGS. 7 and 8 show a conversion process for a single bit synchronization signal or byte synchronization signal in the above embodiment. When input to the format converter 13, a plurality of synchronization signals are multiplexed.
In the figure, only a portion related to a certain synchronization signal is extracted and shown. For simplicity of description, the synchronization signals in FIGS. 4 to 6 are shown by simpler conceptual signals.

The first row of FIG. 7A showing the bit synchronization signal after the bit rate conversion is an area of management information data in the byte synchronization signal, and the bit synchronization signal has no meaning in the information and is merely data. The first row is frequently assigned a data number from the following data. Each data of the first row is added to the data of the area of the second row and below where the transmission data body is recorded also in the byte synchronization signal, and the signal after the format conversion as shown in FIG. can get. Since FIG. 7 shows one bit synchronization signal, the notation after time slot conversion is also shown in FIG.
The result is as shown in FIG. The line is set through the time slot conversion. Therefore, as shown in FIG. 7 (D), the data order is returned to the bit synchronization signal maintaining the original order (FIG. 7 (A)) by the format inversion.

The management information data in the byte synchronization signal after the bit rate conversion shown in the first row of FIG. 8A is shown in FIG. 8B.
As shown in (1), it is added to the corresponding main signal component. 8th
Since the figure also shows one byte synchronization signal, the notation after time slot conversion is also as shown in FIG. 8 (C).
The line is set through the time slot conversion. By the format inversion, as shown in FIG. 8 (D), the data order maintains the original order (FIG. 8 (A)). Therefore, the data order is returned to the byte synchronization signal having the management information at a predetermined position. It is.

FIG. 9 shows a state of time slot conversion of a plurality of synchronization signals. The numbers in FIG. 7 and FIG.
While data (or a data string) in a certain synchronization signal is shown, the numbers in FIG. 9 indicate the difference between the synchronization signals. As shown in FIG. 9 (B), each of the synchronization signals after format conversion shown in FIG. 9 (A) is subjected to slot conversion together with the added data portion (notation below the broken line of each area). Done.

Therefore, according to the above-described embodiment, the line setting circuit 10 capable of handling both the bit synchronization signal and the byte synchronization signal.
Thus, the overall configuration of the digital transmission device including the line setting circuit 10 can be reduced in size as compared with the related art.

In the above embodiment, the time slot conversion is variable, but the time slot conversion may be fixed. That is, the present invention can be applied to a line setting circuit for setting a fixed line.

Further, in the above embodiment, the bit rate conversion unit
Although the circuit that can handle synchronization signals of different bit rates by providing the 11 and the bit rate inverse conversion unit 17 has been described, the configuration may be such that only synchronization signals having the same bit rate from the beginning are targeted. . In this case, the bit rate conversion unit 11 and the bit rate inverse conversion unit 17 become unnecessary.

The processing order of the serial-parallel conversion processing and the multiplexing processing performed by the multiplexing / serial-parallel conversion unit 12 and the processing order of the parallel-serial conversion processing and the separation processing performed by the parallel-serial conversion / separation unit 16 are different. It doesn't matter.

Further, the processing order of the processing performed by the multiplex / serial / parallel conversion unit 12 and the processing performed by the format conversion unit 13, and the processing performed by the parallel / serial conversion / separation unit 16 and the format inverse conversion unit
The order of the processing performed by the processing 15 and the processing performed by the processing 15 does not matter.

Furthermore, the multiplicity and the number of additional bits due to format conversion are not limited to those in the above embodiment.

[Effects of the Invention] As described above, according to the present invention, a byte concept is virtually introduced into a bit synchronization signal, conversion processing is performed in the same manner as the byte synchronization signal, and all management information in the byte synchronization signal is processed. Since transmission is performed without omitting (including an empty case), a line setting circuit that can handle both a bit synchronization signal and a byte synchronization signal can be realized, and digital transmission including the line setting circuit can be realized. The overall configuration of the device can be made smaller than before.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a line setting circuit according to the present invention, FIG. 2 is a block diagram showing a conventional circuit,
FIG. 3 is an explanatory diagram of the signaling demultiplexing process of the conventional circuit, FIG. 4 is an explanatory diagram showing a signal structure after processing by the bit rate conversion unit 11 of the above embodiment, and FIG.
Explanatory diagram showing a signal structure after processing by the serial-parallel conversion unit 12,
FIG. 6 is an explanatory diagram showing the signal structure after processing by the format converter 13 of the above embodiment, FIGS. 7 and 8 are explanatory diagrams showing the state of conversion with each synchronization signal, and FIG. FIG. 4 is an explanatory diagram showing a state of time slot conversion between synchronization signals of FIG. 10 …… Line setting circuit, 12 …… Multiplexing / serial / parallel converter, 13…
… Format converter, 14… Time slot converter,
15: Format inverse converter, 16: Parallel / serial converter / separator.

──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Hiromi Ueda Nippon Telegraph and Telephone Corporation, 1-6, Uchisaiwaicho, Chiyoda-ku, Tokyo (58) Field surveyed (Int.Cl. ⁶ , DB name) H04Q 11 / 04

Claims (1)

(57) [Claims] 1. A channel signal comprising an information signal and a management signal for managing a transmission state of the information signal is time-division multiplexed on a highway and inputted through a plurality of highways connected in parallel. All of the channel signals
A line setting circuit for forming a time slot in the channel signal unit and interconnecting with a predetermined interconnection destination according to the time order of the time slot, multiplexing all information signals of the channel signal, and multiplexing the information signal into an information multiplexed signal; A multiplexing circuit for converting; a multiplexing circuit for multiplexing all the management signals of the channel signal; and a format conversion circuit for format-converting the multiplexed signal into a management multiplexed signal having the same time sequence as the information multiplexed signal; Time slot conversion in which a time slot is formed by pairing the information signal and the management information in the same time sequence of the multiplexed signal and corresponding to the predetermined interconnection destination to be output, and the time order is changed. Circuit, for the information signal and the management signal converted by the time slot conversion circuit, respectively, A double conversion, a reverse conversion of the format conversion, and a separation circuit and a format reverse conversion circuit for converting to an output digital signal, and when performing the interconnection of the channel signal unit, the time slot conversion in the time slot conversion circuit is performed. When the execution is performed in the unit of the channel signal and the interconnection in the unit of the highway is performed, an input signal input through the highway is virtually separated into a pair of an information signal and a management signal similarly to the channel signal. A line setting circuit, wherein a time slot is formed, and the time slot conversion circuit changes the time order of the time slot in accordance with the predetermined interconnection destination to be output.