JPS62200933A - Pcm multiplex block - Google Patents

Abstract

PURPOSE:To simplify the constitution by using a (p).(q) conversion MUX block in combination with an (r).(q) conversion MUX block and receiving a reception block from the (r).(q) conversion MUX block so as to omit partly the B/U conversion and the U/B conversion. CONSTITUTION:p=2MHz, q=8MHz are selected in the (p).(q) conversion MUX block M12, r=34MHz, q=8MHz are selected in the 1st (r).(q) conversion MUX block M23A, r=34MHz, q=8MHz are selected in the 2nd (r).(q) conversion MUX block M23B, q=8MHz is selected in a (q) interface block 34MINF and r=34MHz is selected in an (r) interface block and the D/IMUX block shows the constitution in chained lines in figure. Further, a control section CONT is provided. The M12MUX block is used in pairs with the M32MUX block on the condition and the reception block is received from the M23MUX block for the use.

Description

[Detailed Description of the Invention] [Summary] For example, the first
+8 MHz signal and 34M
A PC that performs second multiplexing and decoding between signals of Hz and
In the M multiplexing system, for the M12MUX block that performs the first multiplexing/decoding, the second multiplexing/decoding is performed.
On the connection side for the M23MUX block that performs decoding,
8MH! (AMI);:8MHz (NRZ) A PCM multiplexing block has been disclosed which has a simplified configuration by omitting conversion and receiving a reception clock from the M23MUX block.

[Industrial application field]

The present invention provides a PCM multiplex block, in particular 9 e.g. 2 M
HZ ;! 9 MHz multiplexing/decoding and 8 MHz
Ml 2 (2MH2;=!8M) used in a PCM multiplex system that performs 234 MHz multiplexing and decoding
H2) Regarding the MUX block, M 23 (8M
This invention relates to a PCM multiplexing block with a simplified configuration on the premise that it will be combined with a PCM multiplexing block (Hz, 34MHz) MUX block.

[Conventional technology]

Conventionally, as shown in FIG. 7, (i) a 2 MHz signal is multiplexed into an 8 MHz signal by Ml 2 (conversion between 2 MHz and 8 MHz) MUx units 1-0 to 1-3, and (ii) the obtained The 8MHz signal is connected to M23 (8
(Conversion between MHz and 34MHz) Multiplexed into 34MHz signal by MUX unit 2 + (iii) Line 3
(iv) decoded into an 8MHz signal by M23MUX unit 4, (v) Ml 2MU
A system is known in which a signal is decoded into a 2 MHz signal by X units 5-0 to 5-3.

When configuring such a system, conventionally, the method shown in Fig. 8 (A
) with the M12MUX unit as shown in the figure.

It was designed to be used in combination with an M23 MUX unit as shown in FIG. 8(B). In addition, in FIG. 8, reference numeral 6 is a rack for an M12 MUX unit, and on the rack 6, there is installed an M12 MUX unit in which two sets of blocks are combined into one unit.
Four MUX units 1 are mounted. Reference numeral 7 is a rack for an M23MUX unit, and on the rack 7, an M23MU unit with one set of blocks as one unit is mounted.
Four X units 2 (or 3) are placed.

Each M12MUX block and M23MUX block has an AMI signal interface to a circuit outside the block, and is configured so that processing is performed within the block using an NRZ signal.

Therefore, in the example of FIG. 7, in Ml 2MUX unit 1-0, 2MHz (AMI) is 2MHz
(NRZ), 2M/8M conversion is performed,
8MHz (NRZ) is converted to 8MHz (AMI) and guided to M23MUX unit 2. Also M
In 23MUX unit 2.

8MHz (AMI) is converted to 8MHz (NRZ), 8M-34M conversion is performed, and 34MHz (NRZ) is converted.
Z) is converted to 34MHz (AMI).

It will be output to line 3.

[Problem that the invention seeks to solve]

In the above conventional case, the M12MUX unit and the M23M
The UX unit and the UX unit are placed on separate racks, which is not preferable if you want to use the racks effectively depending on the system scale.

In addition, in the example shown in FIG. 7, 8MHz on the M23MUX unit side of the M12MUX unit 1-0
(NRZ)-=8MHz (AMI) conversion and M23M
Sealing M12M UX in UX unit 2: L −
1-y example 8 MHz (AMI) -=8
Even though MHz (NRZ) conversion can be omitted.

They are built into each unit and cannot be omitted.

[Means for solving problems]

The present invention is an Ml 2M device configured to solve the above points.
We provide a UX block, and Figure 1 shows Ml 2MUX.
1 shows a principle block diagram of the present invention showing the manner in which blocks are used. FIG.

In Figure 1, 8 indicates a rack, and 9 indicates a 2MHz/34M
Hz conversion unit, io is a 2MHz/8MHz conversion unit, 11 is a first 8MHz/34MHz' conversion unit, 12 is a second 8MHz/34MHz conversion unit,
13 is a 2MHz 8MHz/34MHz conversion unit, 1
4 represents a D/I unit. Further, M12 in the figure is a p'q conversion MUX block according to the present invention, and corresponds to pw2MHz and qm8MHz.

M23A is the first r''q conversion MUX block, and corresponds to r=34MHz and q=8MHz.

M23B is a second r''q conversion MUX block, and corresponds to r=34MHz and q=8MHz.

8MINF is a q interface block,
It supports Q=8MHz.

34MINF is an r interface block and supports r-34MHz.

D/IMUX is a D/I MUX block.

It has the configuration within the chain line shown in FIG. 1(H).

Further, C0NT represents a control section.

[Effect]

In the case shown in FIG.
Although not limited to the shown units, all units have substantially the same size and shape, and if necessary, the rM13J on rack 8 shown in FIG. 1(A). It is selectively placed in the position shown as .

1For example, if unit 9 is placed,
The unit 9 provides a transmitting side configuration shown on the left side of FIG. 7 or a receiving side configuration shown on the right side of the figure.

Note that in the units 9 to 14 shown in FIG.

Each block is assembled into a single unit.

For this reason, the conversion means described for conversion between the AMI signal and the NRZ signal in connection with FIG. 7 is omitted. In other words, (i) When connecting block rM12J to the paired block rM13AJ side in unit 9, NRZ signal-AMI signal conversion is omitted, and (i
i) When connecting block rM13AJ to the paired block “M12” side in unit 9, the AMI signal→N
RZ signal conversion is omitted, and all processing is performed with NRZ signals in unit 9 (the interface between unit 9 and external circuits is AMI (No. i), and the same applies to each unit 10 to 14. be.

Note that illustration is omitted (described later in FIG. 3).

Since the M12MUX block is assumed to be used in combination with the M23MUX block, the reception clock is received from the 1M23MUX block and used.

〔Example〕

Figure 2 (A), (B), (C), (D)
, (E-1) or E-14) is shown in Figure 1CB),
A system configuration diagram corresponding to the units shown in (C), (D), (E), and (F) is shown. Second
Figure (A) In the one shown, 2MHz and 34MHz
A conversion is performed. In the case shown in FIG. 2(B), conversion between 2 MHz and 8 MHz is performed.

Figure 2 (C) In the case shown, r 8 MHz
and 34 MHz. In the case shown in FIG. 2(D), conversion between 8 MHz and 34 MHz is also performed. Figure 2 (t!-1) to CB-14).

This corresponds to the case where a mixture of 2MH2 and 8MHz is converted between 34MHz and 34MHz.

FIG. 3 shows the configuration of an embodiment of the unit corresponding to FIG. 2 (E-11). The illustrated block rM12J, r
8MINFJ, rM23J, rcONT" corresponds to FIG.

The functions of the main parts in the figure are as follows. That is.

■ B/U Bipolar, unipolar conversion.

■ R, L, [1, Loopback signal from the opposite station is looped back at each channel on the lower order group side of the own station. That is, a signal that has entered channel CHI from the opposing station is sent back to the opposing station as is on channel CH1.

■ Signal conversion is performed using IIDB-311DB-3 coding rules.

■ PLL Converts the blank signal sent from the DMUX section into a normal signal.

■MUX Multiplexes 4CH signals into one.

■ DMUX, separates one signal into 4CH.

■ SCR Select a certain polynomial and perform conversion.

■ DSCR Select a certain polynomial and perform inverse transformation.

■L, L, B, turn back to the higher order group side by operating the switch on the own station side. That is, the signal that enters the channel CHI of the own station is looped back by the higher-order group of the own station and returns to the channel CHI.

As can be seen from the illustration in Figure 3, on the M23 AMUX block side of the M12 MUX block, the 8 MHz
It communicates with the M23 AMUX block using the (NRZ) signal. For this reason, the M23 AMUX block side is configured to have no B/U conversion or U/B conversion. Furthermore, the M12 MUX block receives the reception clock from the M23 AMUX block as a clock signal RCLK, and uses this.

FIG. 4 shows the first r-q conversion MUX block “M23AM
A more detailed example configuration of the "UX block" is shown below.

The functions of the main parts in the figure are as follows. That is.

■ R, L, B, Same as Figure 3.

- According to the signal from STF C0NT PO, the teeth of the clock CLK are removed and sent as the reception clock RCLK.

■ PL C0NT This signal allows P
Select either C or internal DUMY PC.

■ DUMY Input a signal from the PC clock CLK to STF C0NT that makes the tooth removal rate constant.

■ PGS clock generator. 34.3
Create a lock if necessary from 68MHz CLOCK.

■ Used when inserting data into variable slots in VIN PCM frame format.

■ Alarm A on PMTS PCM LINE
When LM is detected, a remote alarm is sent to the opposite station in a PCM frame.

■R? lTR Receives remote alarms from the opposite station.

■ Extract the variable slot data in the opposite way to Vout Vin.

@l 5YNC synchronization signal detection.

(1) 5YNCERR Detects out of synchronization.

@DIG ERRPCM Te(7) Bit error 1
It is carried out at 0-' to 10-''.

@AIS Signals from the opposite station all “1
“Detect.

@SCR, DSCR Same as Figure 3.

[Phase] Same as IIDB-3 Figure 3.

FIG. 5 shows a more detailed configuration of an embodiment of the p'q conversion MUX block rM12J, and FIG. 6 shows the configuration of the q interface.
A more detailed example configuration of block r8MINFJ is shown. The external circuit is shown on the left side of the figure. Moreover, MEM represents memory.

〔Effect of the invention〕

As explained above, according to the present invention, since the M12MUX block is used in combination with, for example, the M23MUX block, it is possible to partially omit B/U conversion and υ/B conversion, and it is also possible to receive the reception clock from another block. The configuration can be simplified.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is a system configuration diagram, FIG. 3 is an example configuration of a unit corresponding to FIG. 2 (E-11), and FIG. A more detailed example configuration of the q-transform MUX block. FIG. 5 shows a more detailed configuration of an embodiment of the p'q conversion MUX block, FIG. 6 shows a more detailed configuration of an embodiment of the q interface block, FIG. 7 shows a system configuration diagram, and FIG. 8 shows a conventional configuration. An explanatory diagram explaining the case is shown. In the figure, numeral 8 is a rack, and 9 to 14 are units t- and r, respectively.
M12J is the p-q conversion MUX block, M23AJ is the first r'q conversion MUX block. rM23BJ is the second r-q conversion MUX block. r8MINFJ is the q interface block. r341NFJ is the r interface block. rD/ I MUXJ represents the D/IMUX block.

Claims (1)

[Claims] pMHz signal, q (where q>p) MHz signal, r(
However, in a PCM multiplex system that handles r>q) MHz signals, a p/q conversion MUX block that is connected to the external circuit with a pMHz AMI signal and connected to the internal circuit with a qMHz NRZ signal. and an r/q conversion MUX block that is connected to the external circuit with an rMHz AMI signal and connected to the internal circuit with a qMHz NRZ signal, and the p/q conversion MUX block is connected to the rMHz AMI signal.・q conversion MUX
A PCM multiplexing block, which is used in combination with a PCM multiplexing block and configured to receive a reception clock from the r/q conversion MUX block.